CN101436096B - Core voltage control device - Google Patents
Core voltage control device Download PDFInfo
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- CN101436096B CN101436096B CN2007101887578A CN200710188757A CN101436096B CN 101436096 B CN101436096 B CN 101436096B CN 2007101887578 A CN2007101887578 A CN 2007101887578A CN 200710188757 A CN200710188757 A CN 200710188757A CN 101436096 B CN101436096 B CN 101436096B
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Abstract
The invention discloses a core voltage control device, which is suitable for a central processing unit. The core voltage control device comprises a level conversion unit, a time delay unit and a logical unit, wherein the input end of the level conversion unit receives a first voltage signal and is used for level conversion of the first voltage signal, and the output end of the level conversion unit generates a second voltage signal, wherein the first voltage signal indicates the stable electrifying state, and the second voltage signal indicates the size of the core voltage; the time delay unit performs time delay the second voltage signal, so as to generate a third voltage signal; and the logical unit is coupled to the time delay unit, and used for performing logic operation on the third voltage signal and a fourth voltage signal which is transmitted by a power supply and generating a fifth voltage signal to control whether a core voltage generator supplies the core voltage to the central processing unit or not, wherein the fourth voltage signal indicates the power state.
Description
Technical field
The invention relates to a kind of voltage-operated device, and particularly relevant for a kind of core voltage control device that is used for central processing unit.
Background technology
Computer system (or server) is after the start running, each assembly in the computer system (or server) can't be finished power on (power on) simultaneously, but can provide each assembly required voltage by the general program of powering on, wherein (center processing unit, core voltage CPU) is to provide the latest to central processing unit.And the above-mentioned program that powers on is in regular turn: at first, computer system (or server) powers on.Then, the required voltage of each assembly powered on all stable after, and produce the steady state signal that powers on.Afterwards, the steady state signal that will power on through time-delay after, enable (enable) signal with the core voltage that produces central processing unit.When the core voltage generator receives enable signal, to produce core voltage to central processing unit, so that central processing unit can normal operation.
In addition, computer system (or server) is in shutdown or when outage, and the power supply of all component can not be cut off simultaneously yet, still can according to the program of powering on seriatim stop supplies voltage make each assembly decommission to each assembly.Yet, if when computer system (or server) is shut down, immediately do not stop to produce the core voltage of central processing unit, and cause extra power consumption, and the still lasting running of partial circuit, also may make circuit produce misoperation.
Summary of the invention
The invention provides a kind of core voltage control device, by this can be effectively immediately when computer system (or server) shutdown or outage, the core voltage of central processing unit is given in stop supplies immediately, and reduces power consumption and avoid circuit to produce misoperation.
The present invention proposes a kind of core voltage control device, is applicable to central processing unit.This core voltage control device comprises level conversion unit, delay unit and logical block.The input end of level conversion unit receives first voltage signal, and first voltage signal carried out level conversion, and produce second voltage signal in its output terminal, wherein first voltage signal is indicated the steady state (SS) that powers on, and the size of second voltage signal indication core voltage.Delay unit is in order to second voltage signal of delaying time, to produce the tertiary voltage signal.Logical block is coupled to delay unit, carry out logical operation in order to the 4th voltage signal that tertiary voltage signal and power supply unit are transmitted, and produce the 5th voltage signal control core voltage generator and whether provide core voltage, the 4th voltage signal indication power supply status wherein to central processing unit.
In an embodiment of the present invention, above-mentioned level conversion unit comprises level translator (level shifter), first resistance, electric capacity, impact damper.Level translator receives first voltage signal, and determines whether be converted to the 6th voltage signal according to the level of first voltage signal.First termination of first resistance is received the 6th voltage signal, and second end of first resistance couples level translator.First end of electric capacity is coupled to second end of first resistance, and second end of electric capacity is coupled to ground voltage.The input end of impact damper is coupled to first end of electric capacity, and the output terminal of impact damper produces second voltage signal.
In an embodiment of the present invention, above-mentioned level translator comprises second resistance, the first transistor, the 3rd resistance, the 4th resistance and transistor seconds.First termination of second resistance is received first voltage signal.The base terminal of the first transistor is coupled to second end of second resistance, and the emitter terminal of the first transistor is coupled to ground voltage.First termination of the 3rd resistance is received the 6th voltage signal, and second end of the 3rd resistance is coupled to the collector terminal of the first transistor.First end of the 4th resistance is coupled to second end of the 3rd resistance.The base terminal of transistor seconds is coupled to second end of the 4th resistance, and the collector terminal of transistor seconds is coupled to first end of electric capacity, and the emitter terminal of transistor seconds is coupled to ground voltage.In another embodiment of the present invention, above-mentioned the first transistor and transistor seconds are the NPN bipolar transistor.
In an embodiment of the present invention, above-mentioned delay unit comprises the 5th resistance and second electric capacity.First termination of the 5th resistance is received the 6th voltage signal, and its second termination is received second voltage signal.First end of second electric capacity is coupled to second end of the 5th resistance, and its second end is coupled to ground voltage.
In an embodiment of the present invention, logical block comprise the 6th resistance, diode and with door.First termination of the 6th resistance is received the 6th voltage signal.The anode tap of diode is coupled to second end of the 6th resistance, and the cathode terminal of diode receives the 4th voltage signal.Receive the tertiary voltage signal with the first input end of door, couple the anode tap of diode with second end of door, and the output terminal of Yu Yumen produces the 5th voltage signal.
The present invention is by after carrying out first voltage signal (signal of the steady electricity condition that powers on) level conversion and delay, carry out logical operation with the 4th voltage signal (voltage signal that power supply unit provided) again, and produce the 5th voltage signal, so that whether the foundation of core voltage to central processing unit is provided as the core voltage generator.Thus, can effectively when computer system (or server) shutdown or outage, cut off the core voltage that offers central processing unit immediately,, and also can avoid circuit to produce misoperation with the power consumption of reduction central processing unit.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates the circuit diagram into the core voltage control device of one embodiment of the invention.
Embodiment
Fig. 1 illustrates the circuit diagram into the core voltage control device of one embodiment of the invention.And the core voltage control device 100 of present embodiment is applicable to central processing unit (not illustrating).Please refer to Fig. 1, core voltage control device 100 comprises level conversion unit 110, delay unit 120 and logical block 130.The input end of level conversion unit 110 receives the first voltage signal VS1, and the first voltage signal VS1 carried out level conversion, and produce the second voltage signal VS2 in the output terminal of delay circuit 110, wherein the first voltage signal VS1 is in order to the indication steady state (SS) that powers on, and the second voltage signal VS2 is in order to the size of indication core voltage.
Delay unit 120 is in order to the second voltage signal VS2 that delays time, to produce tertiary voltage signal VS3.Logical block 130 is coupled to delay unit 120, carry out logical operation in order to the 4th voltage signal VS4 that tertiary voltage signal VS3 and power supply unit (not illustrating) are transmitted, and produce the 5th voltage signal VS5 to core voltage generator (not illustrating), whether to provide the foundation of core voltage to central processing unit as control core voltage generator (not illustrating).That is to say that the meeting of core voltage generator is according to the level of the 5th voltage signal VS5, and whether decision provides central processing unit required core voltage.
For instance, if the 5th voltage signal VS5 is a logic high voltage level, then the core voltage generator can provide central processing unit required core voltage, so that central processing unit begins normal operation.If when the 5th voltage signal VS5 is logic low voltage level, then the core voltage generator can stop to provide the core voltage to central processing unit immediately, makes central processing unit decommission.In the present embodiment, the 4th voltage signal VS4 for example is with indicating a power supply status.That is to say,, then represent the power supply unit startup and power supply is provided if the 4th voltage signal VS4 is a logic high voltage level.If the 4th voltage signal VS4 is a logic low voltage level, represents that then power supply unit is closed and power supply no longer is provided.
Please continue with reference to Fig. 1, level conversion unit 110 comprises level translator (level shifter) 111, resistance R 1, capacitor C 1 and impact damper 112.Wherein, level translator 111 receives the first voltage signal VS1, and determines whether to be converted to the 6th voltage signal VS6 according to the level of the first voltage signal VS1.
For instance, if when the first voltage signal VS1 is logic low voltage level, what then level translator 111 can be corresponding is converted to the 6th voltage signal VS6 with the first voltage signal VS1.If the first voltage signal VS1 is a logic high voltage level, what then level translator 111 can be corresponding is converted to logic low voltage level with the first voltage signal VS1.
In addition, level translator 111 still comprises resistance R 2～R4 and transistor Tr 1, Tr2.First termination of resistance R 2 is received the first voltage signal VS1.The base terminal of transistor Tr 1 is coupled to second end of resistance R 2, and the emitter terminal of transistor Tr 1 is coupled to ground voltage GND.First termination of resistance R 3 is received the 5th voltage signal VS5, and its second end is coupled to the collector terminal of transistor Tr 1.First end of resistance R 4 is coupled to second end of resistance R 3.The base terminal of transistor Tr 2 is coupled to second end of resistance R 4, and the collector terminal of transistor Tr 2 is coupled to first end of capacitor C 1, and the emitter terminal of transistor Tr 2 is coupled to ground voltage GND.In the present embodiment, transistor Tr 1, Tr2 for example are the NPN bipolar transistor.
Hold above-mentionedly, first termination of resistance R 1 is received the 6th voltage signal VS6, and its second end couples level translator 111.First end of capacitor C 1 is coupled to second end of resistance R 1, and its second end is coupled to ground voltage GND.The input end of impact damper 112 is coupled to first end of capacitor C 1, and its output terminal produces the second voltage signal VS2.
Delay unit 120 comprises resistance R 5 and capacitor C 2.First termination of resistance R 5 is received the 6th voltage signal VS6, and its second termination is received the second voltage signal VS2.Its first end of capacitor C 2 is coupled to second end of resistance R 5, and its second end is coupled to ground voltage.
Logical block 130 comprise resistance R 6, diode D1 with door 131.First termination of resistance R 6 is received the 6th voltage signal VS6.The anode tap of diode D1 is coupled to second end of resistance R 6, and its cathode terminal receives the 4th voltage signal VS4.Receive tertiary voltage signal VS3 with the first input end of door 131, with door 131 second end be coupled to the anode tap of diode D, and produce the 5th voltage signal VS5 in output terminal with door 131.
In the integrated circuit start, at first, when the first voltage signal VS1 (that is signal of the steady state (SS) that powers on) is logic high voltage level, for example be 1.1V, make transistor Tr 1 conducting, and the 6th voltage signal VS6 sees through resistance R 3 and holds with being coupled to, make transistor Tr 2 not conductings.Because transistor Tr 2 not conductings, the 6th voltage signal VS6 can see through resistance R 1, impact damper 112 outputs, and the second voltage signal VS2 that makes level conversion unit 110 be produced is a logic high voltage level.Then, the second voltage signal VS2 can input to central processing unit (not illustrating), in order to the size of core voltage of indication central processing unit.In addition, the second voltage signal VS2 also can promptly produce tertiary voltage signal VS3 by after delay unit 120 time-delay, and inputs to and 131 first input end.
On the other hand, when the 4th voltage signal VS4 also was logic high voltage level simultaneously, after expression computer system (or server) start, power supply unit to be to begin to provide power supply, made not conducting of diode D.At this moment, the voltage signal that receives simultaneously at the first input end and second input end with door 131 all is a logic high voltage level, therefore, is logic high voltage level in the 5th voltage signal VS5 that exports with the output terminal of door 131.Wherein, the 5th voltage signal VS5 for example enables (enable) signal for the core voltage of central processing unit, and the core voltage generator is according to the voltage level of the 5th voltage signal VS5, to provide corresponding core voltage to central processing unit, allows central processing unit be able to normal operation.
Otherwise, if when a user closes the power-off or the power supply of computer system (or server) of computer system (or server) suddenly (for example having a power failure) suddenly, just represent that also the 4th voltage signal VS4 is converted to logic low voltage level, then diode D conducting, the signal that second input end feasible and door 131 receives is a logic low voltage level.Therefore, with the first input end of door 131 be logic high voltage level, and its second input end is a logic low voltage level, makes that the 5th voltage signal VS5 that exports with the output terminal of door 131 is a logic low voltage level.
Afterwards, the core voltage generator can be converted to logic low voltage level because of the 5th voltage signal VS5, and stops to provide the core voltage of central processing unit immediately, makes central processing unit decommission.Thus, the core voltage control device 100 of present embodiment really can be under computer system (or server) outage or the state of shutdown, immediately stop to provide the core voltage of central processing unit, make central processing unit decommission, to reduce power consumption and to avoid circuit to produce misoperation.
In sum, the present invention is by after carrying out first voltage signal (signal of the steady state (SS) that powers on) level conversion and delay, carry out logical operation with the 4th voltage signal (voltage signal that power supply unit provided) again, and produce the 5th voltage signal, and whether conduct provides the foundation of the core voltage of central processing unit.Thus, the present invention can be effectively when computer system (or server) be shut down or under the state of outage, cut off immediately and offer the core voltage of central processing unit, and then reach the power consumption that reduces central processing unit, and avoid the partly still lasting running of circuit and produce misoperation.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (6)
1. a core voltage control device is applicable to a central processing unit, and this core voltage control device comprises:
One level conversion unit, its input end receives one first voltage signal, in order to this first voltage signal is carried out level conversion, and produce one second voltage signal in its output terminal, wherein this first voltage signal is in order to indicate the steady state (SS) that powers on, and this second voltage signal is in order to indicate the size of a core voltage;
One delay unit is in order to this second voltage signal of delaying time, to produce a tertiary voltage signal; And
One logical block, be coupled to this delay unit, carry out logical operation in order to one the 4th voltage signal that this tertiary voltage signal and a power supply unit are transmitted, and produce one the 5th voltage signal, whether provide this core voltage to this central processing unit to control a core voltage generator, wherein the 4th voltage signal is indicated a power supply status.
2. core voltage control device as claimed in claim 1 is characterized in that, this level conversion unit comprises:
One level translator receives this first voltage signal, and determines whether to be converted to one the 6th voltage signal according to the level of this first voltage signal;
One first resistance, its first termination is received the 6th voltage signal, and its second end couples this level translator;
One electric capacity, its first end is coupled to second end of this first resistance, and its second end is coupled to a ground voltage; And
One impact damper, its input end are coupled to first end of this electric capacity, and its output terminal produces this second voltage signal.
3. core voltage control device as claimed in claim 2 is characterized in that, this level translator comprises:
One second resistance, its first end couple receives this first voltage signal;
One the first transistor, its base terminal are coupled to second end of this second resistance, and its emitter terminal is coupled to this ground voltage;
One the 3rd resistance, its first termination is received the 6th voltage signal, and its second end is coupled to the collector terminal of this first transistor;
One the 4th resistance, its first end is coupled to second end of the 3rd resistance; And
One transistor seconds, its base terminal are coupled to second end of the 4th resistance, and its collector terminal is coupled to first end of this electric capacity, and its emitter terminal is coupled to this ground voltage.
4. core voltage control device as claimed in claim 3 is characterized in that, this first transistor and this transistor seconds are the NPN bipolar transistor.
5. core voltage control device as claimed in claim 1 is characterized in that, this delay unit comprises:
One the 5th resistance, its first termination is received one the 6th voltage signal, and its second termination is received this second voltage signal; And
One second electric capacity, its first end is coupled to second end of the 5th resistance, and its second end is coupled to a ground voltage.
6. core voltage control device as claimed in claim 1 is characterized in that, this logical block comprises:
One the 6th resistance, its first termination is received one the 6th voltage signal;
One diode, its anode tap are coupled to second end of the 6th resistance, and its cathode terminal receives the 4th voltage signal; And
One with the door, its first input end receives this tertiary voltage signal, its second end couples the anode tap of this diode, and produces the 5th voltage signal in its output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101887578A CN101436096B (en) | 2007-11-15 | 2007-11-15 | Core voltage control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101887578A CN101436096B (en) | 2007-11-15 | 2007-11-15 | Core voltage control device |
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| Publication Number | Publication Date |
|---|---|
| CN101436096A CN101436096A (en) | 2009-05-20 |
| CN101436096B true CN101436096B (en) | 2010-08-11 |
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| CN2007101887578A Expired - Fee Related CN101436096B (en) | 2007-11-15 | 2007-11-15 | Core voltage control device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104115091B (en) | 2011-12-30 | 2017-12-26 | 英特尔公司 | Multi-layer CPU high currents are protected |
| CN105610425B (en) * | 2015-12-18 | 2019-01-11 | 珠海市杰理科技股份有限公司 | Power-on protective circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Wu Yajiao Inventor before: Huang Lan Inventor before: Liu Shihao |
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| TR01 | Transfer of patent right |
Effective date of registration: 20170914 Address after: Room 2, unit 1, building 301, Union Street, Wenchang street, Yongxing District, Xianghe, Hebei, Langfang Patentee after: Wu Yajiao Address before: Taipei City, Taiwan Chinese Shilin District Hougang Street No. 66 Patentee before: Inventec Corporation |
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| TR01 | Transfer of patent right | ||
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| CP02 | Change in the address of a patent holder |
Address after: 541002 Diecai District, Guilin City, the Guangxi Zhuang Autonomous Region, No. 147 Zhongshan North Road Patentee after: Wu Yajiao Address before: Room 2, unit 301, building 1, Wenchang street trade union District, Yongxing District, Xianghe County, Langfang, Hebei Patentee before: Wu Yajiao |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100811 Termination date: 20171115 |