CN203812872U - 双列直插封装的框架 - Google Patents

双列直插封装的框架 Download PDF

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CN203812872U
CN203812872U CN201420144273.9U CN201420144273U CN203812872U CN 203812872 U CN203812872 U CN 203812872U CN 201420144273 U CN201420144273 U CN 201420144273U CN 203812872 U CN203812872 U CN 203812872U
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dao
framework
chip
dip
fin
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余晋杉
沐运华
廖伟强
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Gree Electric Appliances Inc of Zhuhai
Zhuhai Gree Xinyuan Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型涉及一种双列直插封装的框架，包括基岛、芯片与内引脚，基岛为平板状，内引脚连接到基岛，所述芯片安装到所述基岛上；所述内引脚与所述基岛的平板面之间具有夹角，所述内引脚与所述基岛为一体成型，达到提高散热效果的目的。

Description

双列直插封装的框架
技术领域
本实用新型涉及半导体封装技术领域，特别是涉及一种双列直插封装技术中使用的框架。
背景技术
一般情况下，双列直插封装（DIP）形式的半导体产品使用平形框架，芯片通过焊料焊接在底部金属基岛上，基岛从封装底部外露散热。
这种封装形式的散热完全依靠晶粒自身来绝缘，对晶粒的绝缘性要求高，且贴附晶粒的基岛面积较小，基岛主要起到均匀晶粒的温度外，实际的散热性能较差。且芯片与内引脚之间使用金线或铝线连接，金线或铝线受直径限制，导热能力不足。
鉴于上述缺陷，本发明人经过长时间的研究和实践终于获得了本发明创造。
实用新型内容
基于此，有必要提供一种提高散热效果的双列直插封装的框架。
本实用新型的一种双列直插封装的框架，包括基岛、芯片与内引脚，基岛为平板状，内引脚连接到基岛，所述芯片安装到所述基岛上；
所述内引脚与所述基岛的平板面之间具有夹角，所述内引脚与所述基岛为一体成型。
作为一种可实施方式，所述芯片与所述基岛以焊接方式固定。
作为一种可实施方式，所述内引脚与所述基岛的材质为铜。
作为一种可实施方式，所述的双列直插封装的框架还包括散热片；
所述散热片设置在所述基岛上焊接所述芯片的另一侧平面上；
所述散热片与所述基岛以树脂粘接方式固定。
作为一种可实施方式，所述散热片的材质为铜。
作为一种可实施方式，所述树脂为高导热材料。
作为一种可实施方式，所述树脂完全覆盖在所述基岛设置所述散热片的平面上。
与现有技术比较本实用新型的有益效果在于：双列直插封装的框架中的内引脚与基岛形成一个整体，减少了传热距离，增大了热传递方向的垂直面积，从而提高了散热效果。
附图说明
图1为本实用新型的双列直插封装的框架的截面示意图；
图2为本实用新型的双列直插封装的框架的左视示意图；
图3为本实用新型的双列直插封装的框架的主视示意图。
具体实施方式
为了解决散热较差的问题，提出了一种双列直插封装的框架来提高散热效果。
以下结合附图，对本实用新型上述的和另外的技术特征和优点作更详细的说明。
请参阅图1所示，其为本实用新型的双列直插封装的框架的截面示意图，本实用新型的一种双列直插封装的框架100包括基岛110、芯片120与内引脚130。
基岛110为平板状，内引脚130连接到基岛110，芯片120安装到基岛110上。
请参阅图2所示，其为本实用新型的双列直插封装的框架的左视示意图，内引脚130与基岛110的平板面之间具有夹角，内引脚130通过折弯方式形成夹角，内引脚130与基岛110为一体成型。
双列直插封装的框架100的芯片120在导热过程中传递的热量按照Fourier导热定律计算：Q=λA(Th-Tc)/δ，
其中，A为芯片120与基岛110的接触面积，单位为m2；Th与Tc分别为芯片120与基岛110的温度；δ为芯片120与基岛110之间的距离，单位为m；λ为芯片的导热系数，单位为W/(m×℃）。
内引脚130与基岛110形成一个整体，减少了芯片120与基岛110之间的距离δ，增大了芯片120与基岛110的接触面积A，从而提高了散热效果。
如图1所示，内引脚130与芯片120之间使用铝线160或金线170进行连接。
作为一种可实施方式，芯片120与基岛110以焊接方式固定。芯片120与基岛110贴合的面上无绝缘层。
作为一种可实施方式，内引脚130与基岛110的材质为铜，铜的散热能力较强，能提高导热系数。
作为一种可实施方式，双列直插封装的框架100还包括散热片140。
散热片140设置在基岛110上焊接芯片120的另一侧平面上，散热片140与基岛110以树脂150粘接方式固定。树脂150的厚度很薄，δ值较小。
散热片140的表面平整，在需要额外增加散热器时，芯片120的热量可以直接通过散热片140传导到散热器上，消除了封装材料与空气的热阻，热量的传导更为顺畅。
作为一种可实施方式，散热片140的材质为铜，铜的散热能力较强。
作为一种可实施方式，树脂150为高导热材料。
作为一种可实施方式，树脂150完全覆盖在基岛110设置散热片140的平面上。
较优地，散热片140也可以完全覆盖整个基岛110，A值最大可以为基岛110的表面积，相应地，为贴附散热片140，树脂150也需要完全覆盖整个基岛110。
请参阅图3所示，其为本实用新型的双列直插封装的框架的主视示意图，双列直插封装的框架100在生产时，先将树脂150加热直至熔融，使用树脂150将散热片140粘贴在基岛110上，散热片140贴附完成后，如图3所示。然后使用成型树脂180将基岛110、芯片120与内引脚130形成的组合体进行封装，并露出散热片140连接基岛110的另一面。
以上所述实施例仅表达了本实用新型的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本实用新型专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本实用新型构思的前提下，还可以做出若干变形和改进，这些都属于本实用新型的保护范围。

Claims (7)

1.一种双列直插封装的框架，包括基岛、芯片与内引脚，基岛为平板状，内引脚连接到基岛，其特征在于，所述芯片安装到所述基岛上；
所述内引脚与所述基岛的平板面之间具有夹角，所述内引脚与所述基岛为一体成型。
2.根据权利要求1所述的双列直插封装的框架，其特征在于，所述芯片与所述基岛以焊接方式固定。
3.根据权利要求1所述的双列直插封装的框架，其特征在于，所述内引脚与所述基岛的材质为铜。
4.根据权利要求2所述的双列直插封装的框架，其特征在于，还包括散热片；
所述散热片设置在所述基岛上焊接所述芯片的另一侧平面上；
所述散热片与所述基岛以树脂粘接方式固定。
5.根据权利要求4所述的双列直插封装的框架，其特征在于，所述散热片的材质为铜。
6.根据权利要求4所述的双列直插封装的框架，其特征在于，所述树脂为高导热材料。
7.根据权利要求4所述的双列直插封装的框架，其特征在于，所述树脂完全覆盖在所述基岛设置所述散热片的平面上。
CN201420144273.9U 2014-03-27 2014-03-27 双列直插封装的框架 Expired - Lifetime CN203812872U (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915403A (zh) * 2014-03-27 2014-07-09 珠海格力电器股份有限公司 双列直插封装的框架
CN105914198A (zh) * 2016-06-21 2016-08-31 无锡华润矽科微电子有限公司 基于铜桥构造的封装结构及构造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915403A (zh) * 2014-03-27 2014-07-09 珠海格力电器股份有限公司 双列直插封装的框架
CN105914198A (zh) * 2016-06-21 2016-08-31 无锡华润矽科微电子有限公司 基于铜桥构造的封装结构及构造方法
CN105914198B (zh) * 2016-06-21 2018-11-27 无锡华润矽科微电子有限公司 基于铜桥构造的封装结构及构造方法

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Granted publication date: 20140903