CN203787977U - Battery pack power equalization circuit - Google Patents
Battery pack power equalization circuit Download PDFInfo
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- CN203787977U CN203787977U CN201320760122.1U CN201320760122U CN203787977U CN 203787977 U CN203787977 U CN 203787977U CN 201320760122 U CN201320760122 U CN 201320760122U CN 203787977 U CN203787977 U CN 203787977U
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Abstract
The utility model discloses a battery pack power equalization circuit, used to perform power equalization on a plurality of battery cells in a series-connected battery pack. Energy of a to-be-equalized battery is collected on a DC bus, and then voltage of the battery cells is collected through a data acquisition circuit, and a master control unit determines the battery cell which needs equalization processing. The battery cell is connected in the equalization circuit, and energy needed in the equalization processing is obtained from the DC bus, and energy needs releasing is released to the DC bus. On the DC bus side, final interaction of electric energy can be completed.
Description
Technical field
The application relates to battery management technical field, more particularly, relates to a kind of battery power equalizing circuit.
Background technology
Due to the fluctuation of material, processing procedure, the difference of service condition, all can cause battery to produce to a certain extent difference, causes the unbalanced problem between battery.A large amount of battery series-parallel connections in energy-storage system, the unbalanced meeting of battery causes significantly " wooden barrel effect ", does not carry out balanced control and will have a strong impact on system serviceability.
The balancing technique of existing battery management system for object be generally the energy-storage system that battery cell capacity is less, adopt the energy-storage travelling wave tubes such as inductance, electric capacity to carry out equilibrium control to battery, its euqalizing current is generally 3 amperes to the maximum.But, along with the fast development in domestic and international energy storage market, in large power energy storage system, monomer capacity high capacity cell more than rank in the time of kilo-ampere has obtained increasing use, the charging and discharging currents of high capacity cell is more than hundred peace levels, therefore, euqalizing current is the battery management system of 3 amperes to the maximum and can not meets the balanced demand of high capacity cell monomer far away.
Utility model content
In view of this, the application provides a kind of battery power equalizing circuit, cannot meet the problem of the balanced demand of high capacity cell monomer for solving existing battery power balancing technique.
To achieve these goals, the existing scheme proposing is as follows:
A kind of battery power equalizing circuit, carries out power equalization for the multiple cells to series battery, comprising:
Power bi-directional converting means, its DC side is connected with described series battery by DC bus, and AC is connected with ac bus, for described series battery is discharged and recharged to control;
Data acquisition circuit, is connected with described series battery, for gathering the voltage signal of described multiple cells and sending;
Main control unit, be connected with described data acquisition circuit, for the treatment of described voltage signal, and judge and need balanced cell and send cell select command according to result, and generate and send pulse width modulation (PWM) signal according to described result;
Power driving circuit, is connected with described main control unit, for receiving described pwm signal and carrying out after driving power amplifies sending;
Battery cell is selected circuit, is connected respectively with described main control unit, described series battery, and the described cell select command receiving for basis, by corresponding cell place in circuit;
DC/DC translation circuit, selects circuit to be connected with described DC bus, described power driving circuit, described battery cell respectively, for the battery cell of selecting being carried out to buck processing and power conversion according to pwm signal after treatment.
Preferably, described DC/DC translation circuit comprises: one-level DC/DC translation circuit and secondary DC/DC translation circuit;
Described one-level DC/DC translation circuit selects circuit, described power driving circuit, described secondary DC/DC translation circuit to be connected with described battery cell respectively, and described secondary DC/DC translation circuit is also connected with described power driving circuit, described DC bus respectively.
Preferably, described data acquisition circuit comprises operational amplifier, the first resistance, the second resistance, the 3rd resistance and the 4th resistance;
One end of described the first resistance is extremely connected with one of battery cell, and the other end is connected to the output of described operational amplifier by described the 3rd resistance;
Another of one end of described the second resistance and battery cell is extremely connected, and the other end is by described the 4th grounding through resistance;
The common port of described the first resistance and described the 3rd resistance is as the reverse input end of described operational amplifier;
The common port of described the second resistance and described the 4th resistance is as the in-phase input end of described operational amplifier;
The output of described operational amplifier connects described main control unit.
Preferably, the main control chip of described main control unit is digital signal processor DSP.
Preferably, described main control chip has 16 road AD conversion ports, for 16 series connection cells are carried out to voltage data processing.
Preferably, described main control unit comprises that module occurs PWM.
Preferably, described power driving circuit comprises: the first optocoupler, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the first triode and the second triode;
The first input end of described the first optocoupler connects forward voltage by described the 5th resistance, and the second input of described the first optocoupler is inputted described pwm signal;
The one termination power other end of described the 6th resistance is by described the 7th resistance and described the 8th grounding through resistance of connecting successively;
Described the 6th resistance and the common port of described the 7th resistance and the first output of described the first optocoupler are connected, the second output head grounding of described the first optocoupler;
The base stage of described the first triode is connected with the base stage of described the second triode, and the common port of described the 7th resistance and described the 8th resistance is connected with the base stage of described the first triode;
The collector electrode of described the first triode connects power supply, and the emitter of described the first triode is connected with the emitter of described the second triode, and the common port of the emitter of the emitter of described the first triode and described the second triode is as the output of described pwm signal;
The grounded collector of described the second triode.
Preferably, described secondary DC/DC translation circuit comprises the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the first inductance and the first electric capacity;
Described the first transistor, described transistor seconds, described the 3rd transistor, described the 4th transistor reverse parallel connection the first diode, the second diode, the 3rd diode and the 4th diode respectively;
Described the first transistor, described transistor seconds, described the 3rd transistor and described the 4th transistorized base stage are connected with described power driving circuit;
The emitter of described the first transistor is connected with the collector electrode of described transistor seconds, and the collector electrode of described the first transistor and the emitter of described transistor seconds are as the first end of described secondary DC/DC translation circuit;
Described the 3rd transistorized emitter is connected with described the 4th transistorized collector electrode, described the 3rd transistorized collector electrode and described the 4th transistorized emitter are as the second end of described secondary DC/DC translation circuit, and the second end of described secondary DC/DC translation circuit is connected with described DC bus;
The emitter of described the first transistor is connected by described the first inductance with described the 3rd transistorized emitter;
The emitter of described transistor seconds is connected with described the 4th transistorized emitter;
The second end of described secondary DC/DC translation circuit is parallel with described the first electric capacity.
Preferably, described one-level DC/DC translation circuit is the same with the circuit structure of described secondary DC/DC translation circuit, the first end of described secondary DC/DC translation circuit is connected with the second end of described one-level DC/DC translation circuit, and the first end of described one-level DC/DC translation circuit selects circuit to be connected with described battery cell.
Preferably, described battery selects circuit to comprise: multiple 3/8 coding chips, wherein three of each described 3/8 coding chip input interfaces are connected with described main control unit, described 3/8 coding chip Ba road output connects respectively the relay at each battery cell two ends by the second to the 9th optocoupler, each 3/8 coding chip can complete the selection of 4 battery cells.
Can find out from above-mentioned technical scheme, the disclosed power of battery equalizing circuit of the application is by gathering the voltage of battery cell and judging the battery cell that need to carry out equilibrium treatment, by in this battery cell access equalizing circuit, change and will be pooled on DC bus by the energy of balancing battery by DC/DC, the energy that will absorb in balancing procedure obtains from DC bus, the energy discharging is also discharged on DC bus, completes the final mutual of electric energy in DC bus side.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiment of the application, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the disclosed a kind of battery power equalizing circuit overall structure block diagram of the embodiment of the present application;
Fig. 2 is the disclosed another kind of battery power equalizing circuit overall structure block diagram of the embodiment of the present application;
Fig. 3 is the disclosed firsts and seconds DC/DC of the embodiment of the present application translation circuit schematic diagram;
Fig. 4 is the disclosed data acquisition circuit schematic diagram of the embodiment of the present application;
Fig. 5 is the disclosed power driving circuit schematic diagram of the embodiment of the present application;
Fig. 6 is that the disclosed battery cell of the embodiment of the present application is selected circuit theory diagrams.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only some embodiments of the present application, instead of whole embodiment.Based on the embodiment in the application, those of ordinary skill in the art are not paying all other embodiment that obtain under creative work prerequisite, all belong to the scope of the application's protection.
Referring to Fig. 1, Fig. 1 is the disclosed a kind of battery power equalizing circuit overall structure block diagram of the embodiment of the present application.
As shown in Figure 1, the equalizing circuit that the present embodiment provides comprises: power bi-directional converting means 100, its DC side is connected with described series battery 110 by DC bus 170, and AC is connected with ac bus 180, for described series battery 110 is discharged and recharged to control;
Particularly, power bi-directional converting means 100 is power electronic equipments that energy can two-way flow, can complete battery pair discharge and recharge control, in the time of the brownout of series battery 110, we can utilize the civil power of AC or photovoltaic electric energy to charge to series battery 110; In the time that AC does not have civil power and photovoltaic electric energy, we can utilize series battery 110 to discharge to AC network.
Data acquisition circuit 120, is connected with series battery 110, for gathering the voltage signal of described multiple cells and sending;
Particularly, data acquisition circuit 120 gathers the voltage signal of multiple series-connected cell monomers, and all voltage signals that gather are all sent to main control unit 130, for main control unit 130 analyzing and processing.
Main control unit 130, be connected with data acquisition circuit 120, for the treatment of described voltage signal, and judge and need balanced cell and send cell select command according to result, and generate and send pulse width modulation (PWM) signal according to described result;
Particularly, main control unit 130 can adopt the digital signal processor DSP (digital signal processor) with 16 road AD conversion ports, can meet the requirement of 16 battery cell voltage detecting.Main control unit 130 is built-in with PWM module occurs, and conveniently DC/DC switch power device is carried out to programming Control.Main control unit 130 receives the analog voltage signal that data acquisition circuit 120 sends, carry out AD conversion, data operation processing, judge and need to carry out balanced cell according to result after treatment, on the one hand the select command of this cell is sent to cell to select circuit 140, the pwm signal of production burst width modulated on the other hand, the state that carries out charge/discharge for controlling DC/DC translation circuit 160, makes it and is connected by balancing battery monomer.
Power driving circuit 150, is connected with described main control unit 130, for receiving described pwm signal and carrying out after driving power amplifies sending;
Battery cell is selected circuit 140, is connected respectively with described main control unit 130, described series battery 110, and the described cell select command receiving for basis, by corresponding cell place in circuit;
DC/DC translation circuit 160, be connected with described DC bus 170 respectively, described power driving circuit 150, described battery cell select circuit 140 to be connected, press and process and power conversion for the battery cell of selecting being carried out to isostatic uplift and depression according to pwm signal after treatment.
The disclosed power of battery equalizing circuit of the present embodiment is by gathering the voltage of battery cell and judging the battery cell that need to carry out equilibrium treatment, by in this battery cell access equalizing circuit, then will be pooled on DC bus 170 by the energy of balancing battery, the energy that will absorb in balancing procedure obtains from DC bus 170, and the energy that discharge is also discharged on DC bus 170.In addition, this design has also facilitated control and management.
It should be explained that, as shown in Figure 1, foregoing circuit can meet the equalization request of the battery cell of some, if the quantity of battery cell is too many, we can be by increasing the form of identical module, for multiple battery cells carry out power equalization processing.
Referring to Fig. 2, Fig. 2 is the disclosed another kind of battery power equalizing circuit overall structure block diagram of the embodiment of the present application.
As shown in Figure 2, on the basis of a upper embodiment, in the present embodiment by 160 points of DC/DC translation circuits in embodiment mono-for one-level DC/DC translation circuit 1600 and secondary DC/DC translation circuit 1601.Described one-level DC/DC translation circuit 1600 selects circuit 140, described power driving circuit 150, described secondary DC/DC translation circuit 1601 to be connected with described battery cell respectively, and described secondary DC/DC translation circuit 1601 is also connected with described power driving circuit 150, described DC bus 170 respectively.
Adopt two-stage design mode, can ensure on the one hand the convenience of the incision of the battery balanced management of monomer/cut out, on the other hand due to generally lower (majority is between 2V-12V) of voltage of large capacity single body battery, system DC bus 170 voltages are generally within the scope of 540V-820V, for reducing buck control difficulty, consider to adopt two-stage energy conversion mode to complete equalization task.
Referring to Fig. 3, Fig. 3 is the disclosed firsts and seconds DC/DC of the embodiment of the present application translation circuit schematic diagram.
As shown in Figure 3, one-level DC/DC translation circuit 1600 can be the same with the circuit topological structure of secondary DC/DC translation circuit 1601.Taking secondary DC/DC translation circuit 1601 as example, its circuit diagram is done to following description:
Secondary DC/DC translation circuit 1601 comprises the first transistor T1, transistor seconds T2, the 3rd transistor T 3, the 4th transistor T 4, the first inductance L 1 and the first capacitor C 1;
The first transistor T1, transistor seconds T2, the 3rd transistor T 3, the 4th transistor T 4 reverse parallel connection the first diode D1, the second diode D2, the 3rd diode D3 and the 4th diode D4 respectively;
The base stage of the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4 is connected with power driving circuit 150;
The emitter of the first transistor T1 is connected with the collector electrode of transistor seconds T2, and the emitter of the collector electrode of the first transistor T1 and transistor seconds T2 is as the first end U1 of secondary DC/DC translation circuit 1601;
The emitter of the 3rd transistor T 3 is connected with the collector electrode of the 4th transistor T 4, the emitter of the collector electrode of the 3rd transistor T 3 and the 4th transistor T 4 is as the second end U2 of secondary DC/DC translation circuit 1601, and the second end U2 of secondary DC/DC translation circuit 1601 is connected with DC bus 170;
The emitter of the first transistor T1 is connected by the first inductance L 1 with the emitter of the 3rd transistor T 3;
The emitter of transistor seconds T2 is connected with the emitter of the 4th transistor T 4;
The second end U2 of secondary DC/DC translation circuit 1601 is parallel with the first capacitor C 1.
It should be noted that, the structure of secondary DC/DC translation circuit 1601 is the same with one-level DC/DC translation circuit 1600, the annexation of the two is: for one-level DC/DC translation circuit 1600, U1 side is battery cell docking side, U2 docks with the U1 of secondary DC/DC translation circuit 1601, and the U2 of secondary DC/DC translation circuit 1601 docks with DC bus 170.For one-level DC/DC translation circuit 1600, can carry out multistep treatment according to the no-load voltage ratio demand of buck.
Buck operation principle is as follows:
(1) forward step-down: when T1 in circuit is as switching tube copped wave, T2, T3, T4 do not work in cut-off state, and circuit is typical Buck circuit, and U1 step-down obtains U2;
(2) forward boosts: when T4 in circuit is as switching tube copped wave, T1 keeps normal open, and T2, T3 do not work in cut-off state, and circuit is typical Boost booster circuit, and U1 boosts and obtains U2;
(3) oppositely step-down: in circuit, T4 is as switching tube copped wave, and T1, T2, T3 do not work in cut-off state, and circuit is reverse Buck circuit, and now U2 step-down obtains U1;
(4) oppositely boost: in circuit, T2 is as switching tube copped wave, and T3 keeps normal open, and T1, T4 do not work in cut-off state, circuit is reverse Boost circuit, and U2 boosts and obtains U1.
Wherein, the operating state of each switching tube is subject to the control of the pulse width modulation (PWM) signal that main control unit 130 sends, and by the switching of different operating state, completes the docking to different electric pressures in system by buck, has realized the equilibrium of high power battery.
Referring to Fig. 4, Fig. 4 is the disclosed data acquisition circuit schematic diagram of the embodiment of the present application.
As shown in Figure 4, in the present embodiment, data acquisition circuit comprises operational amplifier D1, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4;
One end A1 of described the first resistance R 1 is extremely connected with one of battery cell, and the other end is connected to the output terminals A 3 of described operational amplifier D1 by described the 3rd resistance R 3;
Another of one end A2 of described the second resistance R 2 and battery cell is extremely connected, and the other end is by described the 4th resistance R 4 ground connection;
The common port of described the first resistance R 1 and described the 3rd resistance R 3 is as the reverse input end of described operational amplifier D1;
The common port of described the second resistance R 2 and described the 4th resistance R 4 is as the in-phase input end of described operational amplifier D1;
The output terminals A 3 of described operational amplifier D1 connects described main control unit 130.
Particularly, if will carry out balanced management to battery cell, first must measure accurately the voltage of each battery cell.The present embodiment adopts the difference channel taking operational amplifier D1 as core devices to complete, A1 and A2 are respectively the both positive and negative polarity access point of any one battery cell, R1, R2, R3, R4 are difference channel ratio build-out resistor, can obtain needed output voltage range by the ratio relation of adjusting between these four resistance, A3 is the difference output end of monomer battery voltage, and the voltage analog of output is processed for main control unit 130.
Referring to Fig. 5, Fig. 5 is the disclosed power driving circuit schematic diagram of the embodiment of the present application.
As shown in Figure 5, the disclosed power driving circuit 150 of the present embodiment comprises: the first optocoupler G1, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the first triode Q1 and the second triode Q2;
The first input end of described the first optocoupler G1 connects forward voltage by described the 5th resistance R 5, and the second input of described the first optocoupler G1 is inputted described pwm signal;
The one termination power other end of described the 6th resistance R 6 is by described the 7th resistance R 7 and described the 8th resistance R 8 ground connection connected successively;
The common port of described the 6th resistance R 6 and described the 7th resistance R 7 is connected with the first output of described the first optocoupler G1, the second output head grounding of described the first optocoupler G1;
The base stage of described the first triode Q1 is connected with the base stage of described the second triode Q2, and the common port of described the 7th resistance R 7 and described the 8th resistance R 8 is connected with the base stage of described the first triode Q1;
The collector electrode of described the first triode Q1 connects power supply, the emitter of described the first triode Q1 is connected with the emitter of described the second triode Q2, and the common port of the emitter of the emitter of described the first triode Q1 and described the second triode Q2 is as the output of described pwm signal;
The grounded collector of described the second triode Q2.
Particularly, the present embodiment circuit adopts optocoupler to realize the high-low pressure isolation of master control system and power circuit, drives and adopts NPN and the PNP push-pull circuit that triode forms back-to-back to realize, and this circuit structure is simple, and instantaneous current drive capability is large, good operating stability.Wherein resistance R 8 is drive circuit protective resistance; static when optocoupler side breaks down or staff touches; capital is to insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor); bring destructive damage, adding resistance R 4 can play a good protection.
Referring to Fig. 6, Fig. 6 is that the disclosed battery cell of the embodiment of the present application is selected circuit theory diagrams.
The disclosed battery cell of the present embodiment selects circuit to comprise: multiple 3/8 coding chips.As shown in Figure 6, wherein three of each described 3/8 coding chip input interface S1, S2 are connected with universal port GPIO1, GPIO2, the GPIO3 of main control unit 130 with S3, described 3/8 coding chip Ba road output D
1-D
8the relay that connects respectively each battery cell two ends by the second to the 9th optocoupler G2-G9, each 3/8 coding chip can complete the selection of 4 battery cells.
It should be noted that, be respectively equipped with a relay at the two poles of the earth of each cell, can be by corresponding battery cell place in circuit by closed certain two relay.The number of supposing battery cell is N, and the number of relay is 2N.Referring to Fig. 6, we are taking battery B1 as example, at the positive and negative polarities B1 of battery B1
-and B1
+an each relay J 1 and J2 of existing, can be by battery B1 place in circuit by closed J1 and J2.
It should be noted that, each 3/8 decoder can complete the selection of 4 battery cells, because principle is identical, Fig. 6 has just drawn a part, and other Ji road design is identical.In order to complete the equilibrium to many battery cells, can increase the number of decoder.
Particularly, the course of work is: main control unit 130 sends battery cell select command to decoder by three universal port GPIO1, GPIO2, GPIO3, carries out battery selection.The corresponding D of selected battery
x (1-8)for low level output, not selected is high level output, and being output as the corresponding optocoupler of low level signal is conducting state, while only having optocoupler to be conducting state, its corresponding relay could be closed, and therefore corresponding battery cell is access in equalizing system by relay, accepts balanced management.
Finally, also it should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, article or the equipment that comprises described key element and also have other identical element.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment, between each embodiment identical similar part mutually referring to.
To the above-mentioned explanation of the disclosed embodiments, make professional and technical personnel in the field can realize or use the application.To be apparent for those skilled in the art to the multiple amendment of these embodiment, General Principle as defined herein can, in the case of not departing from the application's spirit or scope, realize in other embodiments.Therefore, the application will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a battery power equalizing circuit, carries out power equalization for the multiple cells to series battery, it is characterized in that, comprising:
Power bi-directional converting means, its DC side is connected with described series battery by DC bus, and AC is connected with ac bus, for described series battery is discharged and recharged to control;
Data acquisition circuit, is connected with described series battery, for gathering the voltage signal of described multiple cells and sending;
Main control unit, be connected with described data acquisition circuit, for the treatment of described voltage signal, and judge and need balanced cell and send cell select command according to result, and generate and send pulse width modulation (PWM) signal according to described result;
Power driving circuit, is connected with described main control unit, for receiving described pwm signal and carrying out after driving power amplifies sending;
Battery cell is selected circuit, is connected respectively with described main control unit, described series battery, and the described cell select command receiving for basis, by corresponding cell place in circuit;
DC/DC translation circuit, selects circuit to be connected with described DC bus, described power driving circuit, described battery cell respectively, for the battery cell of selecting being carried out to buck processing and power conversion according to pwm signal after treatment.
2. circuit according to claim 1, is characterized in that, described DC/DC translation circuit comprises: one-level DC/DC translation circuit and secondary DC/DC translation circuit;
Described one-level DC/DC translation circuit selects circuit, described power driving circuit, described secondary DC/DC translation circuit to be connected with described battery cell respectively, and described secondary DC/DC translation circuit is also connected with described power driving circuit, described DC bus respectively.
3. circuit according to claim 1, is characterized in that, described data acquisition circuit comprises operational amplifier, the first resistance, the second resistance, the 3rd resistance and the 4th resistance;
One end of described the first resistance is extremely connected with one of battery cell, and the other end is connected to the output of described operational amplifier by described the 3rd resistance;
Another of one end of described the second resistance and battery cell is extremely connected, and the other end is by described the 4th grounding through resistance;
The common port of described the first resistance and described the 3rd resistance is as the reverse input end of described operational amplifier;
The common port of described the second resistance and described the 4th resistance is as the in-phase input end of described operational amplifier;
The output of described operational amplifier connects described main control unit.
4. circuit according to claim 1, is characterized in that, the main control chip of described main control unit is digital signal processor DSP.
5. circuit according to claim 4, is characterized in that, described main control chip has 16 road AD conversion ports, for 16 series connection cells are carried out to voltage data processing.
6. circuit according to claim 1, is characterized in that, described main control unit comprises that module occurs PWM.
7. circuit according to claim 1, is characterized in that, described power driving circuit comprises: the first optocoupler, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the first triode and the second triode;
The first input end of described the first optocoupler connects forward voltage by described the 5th resistance, and the second input of described the first optocoupler is inputted described pwm signal;
The one termination power other end of described the 6th resistance is by described the 7th resistance and described the 8th grounding through resistance of connecting successively;
Described the 6th resistance and the common port of described the 7th resistance and the first output of described the first optocoupler are connected, the second output head grounding of described the first optocoupler;
The base stage of described the first triode is connected with the base stage of described the second triode, and the common port of described the 7th resistance and described the 8th resistance is connected with the base stage of described the first triode;
The collector electrode of described the first triode connects power supply, and the emitter of described the first triode is connected with the emitter of described the second triode, and the common port of the emitter of the emitter of described the first triode and described the second triode is as the output of described pwm signal;
The grounded collector of described the second triode.
8. circuit according to claim 2, is characterized in that, described secondary DC/DC translation circuit comprises the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the first inductance and the first electric capacity;
Described the first transistor, described transistor seconds, described the 3rd transistor, described the 4th transistor reverse parallel connection the first diode, the second diode, the 3rd diode and the 4th diode respectively;
Described the first transistor, described transistor seconds, described the 3rd transistor and described the 4th transistorized base stage are connected with described power driving circuit;
The emitter of described the first transistor is connected with the collector electrode of described transistor seconds, and the collector electrode of described the first transistor and the emitter of described transistor seconds are as the first end of described secondary DC/DC translation circuit;
Described the 3rd transistorized emitter is connected with described the 4th transistorized collector electrode, described the 3rd transistorized collector electrode and described the 4th transistorized emitter are as the second end of described secondary DC/DC translation circuit, and the second end of described secondary DC/DC translation circuit is connected with described DC bus;
The emitter of described the first transistor is connected by described the first inductance with described the 3rd transistorized emitter;
The emitter of described transistor seconds is connected with described the 4th transistorized emitter;
The second end of described secondary DC/DC translation circuit is parallel with described the first electric capacity.
9. circuit according to claim 8, it is characterized in that, described one-level DC/DC translation circuit is the same with the circuit structure of described secondary DC/DC translation circuit, the first end of described secondary DC/DC translation circuit is connected with the second end of described one-level DC/DC translation circuit, and the first end of described one-level DC/DC translation circuit selects circuit to be connected with described battery cell.
10. circuit according to claim 1, it is characterized in that, described battery selects circuit to comprise: multiple 3/8 coding chips, wherein three of each described 3/8 coding chip input interfaces are connected with described main control unit, described 3/8 coding chip Ba road output connects respectively the relay at each battery cell two ends by the second to the 9th optocoupler, each 3/8 coding chip can complete the selection of 4 battery cells.
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| CN201320760122.1U CN203787977U (en) | 2013-11-26 | 2013-11-26 | Battery pack power equalization circuit |
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| CN201320760122.1U CN203787977U (en) | 2013-11-26 | 2013-11-26 | Battery pack power equalization circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103618352A (en) * | 2013-11-26 | 2014-03-05 | 山东圣阳电源股份有限公司 | Battery pack power equalization circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103618352A (en) * | 2013-11-26 | 2014-03-05 | 山东圣阳电源股份有限公司 | Battery pack power equalization circuit |
| CN103618352B (en) * | 2013-11-26 | 2017-01-11 | 山东圣阳电源股份有限公司 | Battery pack power equalization circuit |
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