CN201667616U - Multiple power supply load circuit - Google Patents
Multiple power supply load circuit Download PDFInfo
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- CN201667616U CN201667616U CN201020150090XU CN201020150090U CN201667616U CN 201667616 U CN201667616 U CN 201667616U CN 201020150090X U CN201020150090X U CN 201020150090XU CN 201020150090 U CN201020150090 U CN 201020150090U CN 201667616 U CN201667616 U CN 201667616U
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Abstract
The utility model provides a multiple power supply load circuit, which comprises a DAC chip, wherein the DAC chip is provided with a plurality of output ports, each output port of the DAC chip is respectively connected with a voltage handling circuit, the output ends of two adjacent voltage handling circuits are connected through a serial connection group, and the serial connection group comprises a load resistor and an analog switch, wherein the voltage handling circuit comprises a first operation amplifier and a push-pull circuit which are sequentially connected, the positive direction end of the first operation amplifier is connected to the output port of the DAC chip, and the reverse direction end of the first operation amplifier is connected to the output end of the push-pull circuit. The utility model adopts the DAC chip for providing multiple paths of output voltage, and handles each path of output voltage by the voltage handling circuits provided by the utility model. The utility model is also provided with the analog switch between two adjacent voltage handling circuits, so the charging or discharging operation on multiple paths of loads at the same time can be realized.
Description
Technical field
The utility model relates to power load circuit, relates in particular to a kind of power load circuit that can carry out charge or discharge to multichannel loading.
Background technology
The power source loads device is mainly used in and is some particular electrical circuit power supply, or as the discharge load of some devices, present existing power source loads device can only singlely be finished a certain work, its function ratio is more single, what have can only export single channel voltage to serve as power supply, what have can only do load device, can't output voltage to serve as power supply, generally speaking, it lacks extended capability, can't satisfy the demand of multiple power supplies load, simultaneously, these present power source loads device circuit complex structures, needing increases nonlinear devices such as inductance or electric capacity, and this has increased production cost to a certain extent.
The utility model content
The utility model provides a kind of multiple power supplies load circuit for solving the technical problem that existing power source loads device can't satisfy the demand that the multiple power supplies load can be provided.
For solving the problems of the technologies described above, the technical solution of the utility model is:
A kind of multiple power supplies load circuit, comprise DAC chip with a plurality of output ports, each output port of described DAC chip all is connected with a voltage respectively and disposes circuit, the output that adjoining in twos described voltage is disposed circuit all links to each other by a string joint group, described series connection group comprises load resistance and analog switch, wherein, described voltage is disposed circuit and is comprised one first operational amplifier and a push-pull circuit that connects successively, the forward end of described first operational amplifier is connected to the output port of DAC chip, and backward end is connected to the output of described push-pull circuit.
Further, described push-pull circuit comprises first resistance with a common port, second resistance and the 3rd resistance, also comprise first transistor and second transistor, described first resistance, one common port of second resistance and the 3rd resistance is connected to the output of operational amplifier, the other end of described first resistance is connected to the base stage of first transistor, the other end of described second resistance is connected to the emitter of first transistor and second transistor, and be connected with the backward end of described first operational amplifier, the other end of described the 3rd resistance is connected to the base stage of described second transistor, the collector electrode of described first transistor connects high level, and the collector electrode of described second transistor connects negative level.
Further, the voltage range of described high level is+5v～+ 18v, the voltage range of described negative level is-5v～-18v.
Further, the voltage of described high level is+18v that the voltage of described negative level is-18v.
Further, described analog switch is a field-effect transistor.
Further, the grid of described field-effect transistor is connected to the output of corresponding IC protection chip, and the input of described IC protection chip is connected to the output that corresponding voltage is disposed circuit.
Further, the voltage that is connected to DAC chip head end output port or terminal output port is disposed the output of circuit by a string joint group ground connection.
Further, described multiple power supplies load circuit also comprises the calculus of differences amplifying circuit, and the two ends of described load resistance are connected to two inputs of calculus of differences amplifying circuit respectively.
Further, described calculus of differences amplifying circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and one second operational amplifier, one end of described the 4th resistance is connected to an end of load resistance, its other end is connected to an end of the 5th resistance and the positive input of second operational amplifier, the other end ground connection of described the 5th resistance, the other end of one termination load resistance of described the 6th resistance, its other end is connected to an end of the 7th resistance and is connected with the reverse input end of second operational amplifier, and the other end of described the 7th resistance is connected to the output of described second operational amplifier.
The utility model adopts the DAC chip that the multichannel output voltage is provided, and the voltage that every road output voltage adopts the utility model to provide is disposed circuit handle, the utility model also is provided with analog switch by disposing between the circuit at adjacent in twos voltage, thereby can realize simultaneously multichannel loading being carried out the operation of charge or discharge, and, because the multiple power supplies load circuit that the utility model provides does not need nonlinear devices such as more expensive relatively inductance of extra adding price or electric capacity, therefore can reduce production costs to a certain extent.
Description of drawings
Fig. 1 is the electrical block diagram of a kind of embodiment of multiple power supplies load circuit of providing of the utility model;
Fig. 2 is the DAC chip connection diagram of a kind of embodiment of multiple power supplies load circuit of providing of the utility model;
Fig. 3 is the schematic diagram of the IC protection chip of a kind of embodiment of multiple power supplies load circuit of providing of the utility model;
Fig. 4 is the electrical block diagram of calculus of differences amplifying circuit in the multiple power supplies load circuit that provides of the utility model.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
See also Fig. 1 to Fig. 4, the utility model provides a kind of multiple power supplies load circuit, comprise DAC chip 30 with a plurality of output ports, each output port of described DAC chip 30 all is connected with a voltage respectively and disposes circuit 10, the output that adjoining in twos described voltage is disposed circuit 10 all links to each other by a string joint group 20, described series connection group 20 comprises load resistance R and analog switch, wherein, described voltage is disposed circuit 10 and is comprised one first an operational amplifier U1 and a push-pull circuit that connects successively, the forward end of the described first operational amplifier U1 is connected to the output port of DAC chip 30, and backward end is connected to the output of described push-pull circuit.
As shown in Figure 1, the electrical block diagram of a kind of embodiment of multiple power supplies load circuit that provides for the utility model, in the present embodiment, described DAC chip 30 has 4 output ports, and having 4 road voltages, to dispose circuit 10 corresponding with it.According to content of the present utility model, in concrete implementation process, the series connection group 20 that described load resistance R and analog switch are formed can be at least 2 groups, 4 groups at the most, its be connected to described 4 the tunnel adjacent to one another voltage dispose between the output of circuit 10, when the series connection group 20 of described load resistance R and analog switch composition has 4 groups, in a kind of execution mode that the utility model provides, the voltage that is connected to DAC chip 30 head end output ports or terminal output port is disposed the output of circuit 10 by a string joint group 20 ground connection.For example in the present embodiment, its output that is connected to voltage disposal circuit 10 of DAC chip 30 head end output ports or terminal output port is organized 20 ground connection by the series connection of this load resistance R and analog switch composition.
With reference to Fig. 2, be DAC chip 30 connection diagrams of a kind of embodiment of multiple power supplies load circuit of providing of the utility model.PC40 by the outside provides after it is programmed, makes the voltage output of its operation and control DAC chip 30.With by control DAC chip 30 output multi-channel analog voltage V1, V2, V3, V4, and can be by changing the program setting of PC40, thereby control any one tunnel voltage output situation, reach Linear Control to late-class circuit.
Further, continuation is with reference to Fig. 1, described push-pull circuit comprises first resistance R 1 with a common port, second resistance R 2 and the 3rd resistance R 3, also comprise the first transistor Q1 and the second transistor Q2, described first resistance R 1, one common port of second resistance R 2 and the 3rd resistance R 3 is connected to the output of the first operational amplifier U1, the other end of described first resistance R 1 is connected to the base stage of the first transistor Q1, the other end of described second resistance R 2 is connected to the emitter of the first transistor Q1 and the second transistor Q2, and be connected with the backward end of the described first operational amplifier U1, the other end of described the 3rd resistance R 3 is connected to the base stage of the described second transistor Q2, the collector electrode of the described first transistor Q1 connects high level, and the collector electrode of the described second transistor Q2 connects negative level.
Further, the voltage range of described high level is+5v～+ 18v, the voltage range of described negative level is-5v～-18v.Under the preferable case, the voltage of described high level is+18v that the voltage of described negative level is-18v.
Further, in implementation process, described analog switch is a field-effect transistor.In the present embodiment, as shown in Figure 3, the grid of described field-effect transistor is connected to the BAL port of IC protection chip 50 correspondences, and the input port of described IC protection chip 50 is connected to the output that corresponding voltage is disposed circuit 10.In the utility model; described IC protection chip 50 can be selected the BM320 chip for use; when its input port is connected to the output of the voltage disposal circuit 10 corresponding with it; can obtain stable high level; so that the output of IC protection chip 50 can be exported high level, makes analog switch be in conducting state.
Further, the multiple power supplies load circuit also comprises the calculus of differences amplifying circuit as described in Figure, and the two ends of described load resistance R are connected to two inputs of calculus of differences amplifying circuit respectively.
Further, described calculus of differences amplifying circuit comprises the 4th resistance R 40, the 5th resistance R 50, the 6th resistance R 60, the 7th resistance R 70 and one second operational amplifier U100, one end of described the 4th resistance R 40 is connected to the end of load resistance R, its other end is connected to an end of the 5th resistance R 50 and the positive input of the second operational amplifier U100, the other end ground connection of described the 5th resistance R 50, the other end of one termination load resistance R of described the 6th resistance R 60, its other end is connected to an end of the 7th resistance R 70 and is connected with the reverse input end of the second operational amplifier U100, and the other end of described the 7th resistance R 70 is connected to the output of the described second operational amplifier U100.
Further, described multiple power supplies load circuit R also comprises the A/D conversion equipment, and the output of the described second operational amplifier U100 is connected to the input of described A/D conversion equipment.Described calculus of differences amplifying circuit detects the voltage signal at load resistance R two ends, after the process processing of this circuit, can convert described detected voltage signal to digital signal by the described A/D conversion equipment that the utility model provides, and described voltage signal be shown by the display device that those skilled in the art know.
Below, this embodiment that provides with regard to the utility model does an introduction to the operation principle of this multiple power supplies load circuit, and is as follows:
Referring to Fig. 1, the different voltage in DAC chip 30 outputs 4 road voltages to 4 tunnel is disposed the first operational amplifier input V1 of circuit 10, V2, V3, V4, voltage follow characteristic according to this operational amplifier, the output of disposing circuit 10 at described 4 road voltages forms 4 power supply outputs, promptly, VT1=V1, VT2=V2, VT3=V3, VT4=V4, and described voltage is disposed circuit 10 can regulated output voltage, for example, one group of data according to present embodiment provides can obtain VT1=V1=12.00V, VT2=V2=9.00V, VT3=V3=6.00V, VT4=V4=3.00V.And output VT1, VT2, VT3, VT4 that described 4 road voltages are disposed circuit 10 are connected to the input that IC protects chip 50 respectively; in the case; to the base stage output low level of field-effect transistor (M1, M2, M3, M4), field-effect transistor (M1, M2, M3, M4) is an off state respectively for output BAL1, BAL2, BAL3, the BAL4 of IC protection chip 50.When the output voltage V T1 of any one tunnel in the voltage disposal circuit 10 changes in the 12.48V-12.680V scope; because the pressure reduction between VT1 and the VT2 is in 3.48V-3.68V scope interval; when IC protection chip 50 detects this this pressure reduction; can export a high level that continues to the grid of field-effect transistor M1 by the BAL1 port; at this moment; field-effect transistor switch M1 conducting; form current circuit between the output VT1 of voltage disposal circuit 10 and the VT2; in the case; when described load resistance R13=33 Ω, the voltage 12.48V-12.680V at its two ends.Thereby according to ohm theorem Ir=Vr/R13, the magnitude range of the electric current I r of the load resistance R13 that can obtain flowing through is 0.105A-0.112A, and electric current flows to a2 by a1.At this moment, for power supply VT1 is discharge condition, then belong to charged state for power supply VT2, and because the push-pull circuit that transistor Q1 and transistor Q2 constitute provides operational amplifier corresponding current range, therefore power supply VT1 and power supply VT2 two-port voltage can not change, thereby keep the constant pressure and flow output state.And the like, the voltage output that IC protection chip 50 is disposed circuit 10 according to other any one road voltages changes the output that also can realize its constant current or constant voltage.
With reference to Fig. 4, when electric current flow through load resistance (R13, R14, R15, R16) one or more the time, detect the size of this electric current by the calculus of differences amplifying circuit that is separately positioned on a1 and a2, b1 and b2, c1 and c2 and d1 and d2 two ends.Simultaneously, this calculus of differences amplifying circuit can detect the change in voltage at described a1 and a2, b1 and b2, c1 and c2 and d1 and d2 two ends, and this change in voltage is fed back to IC protection chip, to control its work operation.
The utility model adopts DAC chip 30 that the multichannel output voltage is provided, and the voltage that every road output voltage adopts the utility model to provide is disposed circuit 10 handle, the utility model also is provided with analog switch by disposing between the circuit 10 at adjacent in twos voltage, thereby can realize simultaneously multichannel loading being carried out the operation of charge or discharge, and, because the multiple power supplies load circuit that the utility model provides does not need nonlinear devices such as more expensive relatively inductance of extra adding price or electric capacity, therefore can reduce production costs to a certain extent.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (9)
1. multiple power supplies load circuit, it is characterized in that, comprise DAC chip with a plurality of output ports, each output port of described DAC chip all is connected with a voltage respectively and disposes circuit, the output that adjoining in twos voltage is disposed circuit all links to each other by a string joint group, described series connection group comprises load resistance and analog switch, wherein, described voltage is disposed circuit and is comprised one first operational amplifier and a push-pull circuit that connects successively, the forward end of described first operational amplifier is connected to the output port of DAC chip, and backward end is connected to the output of described push-pull circuit.
2. multiple power supplies load circuit as claimed in claim 1, it is characterized in that, described push-pull circuit comprises first resistance with a common port, second resistance and the 3rd resistance, also comprise first transistor and second transistor, described first resistance, one common port of second resistance and the 3rd resistance is connected to the output of first operational amplifier, the other end of described first resistance is connected to the base stage of first transistor, the other end of described second resistance is connected to the emitter of first transistor and second transistor, and be connected with the backward end of described first operational amplifier, the other end of described the 3rd resistance is connected to the base stage of described second transistor, the collector electrode of described first transistor connects high level, and the collector electrode of described second transistor connects negative level.
3. multiple power supplies load circuit as claimed in claim 1 is characterized in that, the voltage range of described high level is+5v～+ 18v, the voltage range of described negative level is-5v～-18v.
4. multiple power supplies load circuit as claimed in claim 3 is characterized in that, the voltage of described high level is+18v that the voltage of described negative level is-18v.
5. multiple power supplies load circuit as claimed in claim 1 is characterized in that, described analog switch is a field-effect transistor.
6. multiple power supplies load circuit as claimed in claim 5 is characterized in that, the grid of described field-effect transistor is connected to the output of corresponding IC protection chip, and the input of described IC protection chip is connected to the output that corresponding voltage is disposed circuit.
7. multiple power supplies load circuit as claimed in claim 1 is characterized in that, the voltage that is connected to DAC chip head end output port or terminal output port is disposed the output of circuit by a string joint group ground connection.
8. multiple power supplies load circuit as claimed in claim 1 is characterized in that, described multiple power supplies load circuit also comprises the calculus of differences amplifying circuit, and the two ends of described load resistance are connected to two inputs of calculus of differences amplifying circuit respectively.
9. multiple power supplies load circuit as claimed in claim 8, it is characterized in that, described calculus of differences amplifying circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance and one second operational amplifier, one end of described the 4th resistance is connected to an end of load resistance, its other end is connected to an end of the 5th resistance and the positive input of second operational amplifier, the other end ground connection of described the 5th resistance, the other end of one termination load resistance of described the 6th resistance, its other end is connected to an end of the 7th resistance and is connected with the reverse input end of second operational amplifier, and the other end of described the 7th resistance is connected to the output of described second operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020150090XU CN201667616U (en) | 2010-03-29 | 2010-03-29 | Multiple power supply load circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020150090XU CN201667616U (en) | 2010-03-29 | 2010-03-29 | Multiple power supply load circuit |
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| Publication Number | Publication Date |
|---|---|
| CN201667616U true CN201667616U (en) | 2010-12-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201020150090XU Expired - Fee Related CN201667616U (en) | 2010-03-29 | 2010-03-29 | Multiple power supply load circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279293A (en) * | 2011-03-24 | 2011-12-14 | 深圳市瑞雷特电子技术有限公司 | Digital-analog compatible controlled electronic load |
| CN102353825A (en) * | 2011-06-03 | 2012-02-15 | 清华大学 | Resistor sampling isolation current detection circuit |
| WO2014101837A1 (en) * | 2012-12-28 | 2014-07-03 | 电子科技大学 | Multipath current source switching device |
| CN106291065A (en) * | 2016-10-17 | 2017-01-04 | 成都前锋电子仪器有限责任公司 | A kind of voltage sample circuit |
| CN107656572A (en) * | 2017-10-27 | 2018-02-02 | 北京大华无线电仪器有限责任公司 | The multichannel variable voltage source and its control method realized with digital analog converter |
| CN112904926A (en) * | 2021-02-22 | 2021-06-04 | 苏州博思得电气有限公司 | Multi-electrode voltage generator |
| CN113395046A (en) * | 2021-06-18 | 2021-09-14 | 电子科技大学 | Integrated operation and discharge flat window expanding device based on variable asymmetric power supply mechanism |
-
2010
- 2010-03-29 CN CN201020150090XU patent/CN201667616U/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279293A (en) * | 2011-03-24 | 2011-12-14 | 深圳市瑞雷特电子技术有限公司 | Digital-analog compatible controlled electronic load |
| CN102353825A (en) * | 2011-06-03 | 2012-02-15 | 清华大学 | Resistor sampling isolation current detection circuit |
| CN102353825B (en) * | 2011-06-03 | 2014-02-19 | 清华大学 | Resistor sampling isolation current detection circuit |
| RU2623494C2 (en) * | 2012-12-28 | 2017-06-27 | Юниверсити Оф Электроник Сайенс Энд Текнолоджи Оф Чайна | Multipositional device for switching current source |
| AU2013369771B2 (en) * | 2012-12-28 | 2016-08-04 | Sichuan Sunfor Light Co., Ltd. | Multipath current source switching device |
| WO2014101837A1 (en) * | 2012-12-28 | 2014-07-03 | 电子科技大学 | Multipath current source switching device |
| US9819195B2 (en) | 2012-12-28 | 2017-11-14 | Sichuan Sunfor Light Co., Ltd | Multipath current source switching device |
| CN106291065A (en) * | 2016-10-17 | 2017-01-04 | 成都前锋电子仪器有限责任公司 | A kind of voltage sample circuit |
| CN107656572A (en) * | 2017-10-27 | 2018-02-02 | 北京大华无线电仪器有限责任公司 | The multichannel variable voltage source and its control method realized with digital analog converter |
| CN112904926A (en) * | 2021-02-22 | 2021-06-04 | 苏州博思得电气有限公司 | Multi-electrode voltage generator |
| CN112904926B (en) * | 2021-02-22 | 2022-08-09 | 苏州博思得电气有限公司 | Multi-electrode voltage generator |
| CN113395046A (en) * | 2021-06-18 | 2021-09-14 | 电子科技大学 | Integrated operation and discharge flat window expanding device based on variable asymmetric power supply mechanism |
| CN113395046B (en) * | 2021-06-18 | 2022-06-03 | 电子科技大学 | Integrated operation and discharge flat window expanding device based on variable asymmetric power supply mechanism |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20101208 Termination date: 20160329 |