CN203774322U - 多晶片发光二极管封装结构 - Google Patents

多晶片发光二极管封装结构 Download PDF

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Publication number
CN203774322U
CN203774322U CN201320876776.0U CN201320876776U CN203774322U CN 203774322 U CN203774322 U CN 203774322U CN 201320876776 U CN201320876776 U CN 201320876776U CN 203774322 U CN203774322 U CN 203774322U
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led
package structure
layer
wafer package
insulating layer
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陈燕章
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SHENZHEN RIODDIN OPTOELECTRONICS TECHNOLOGY Co Ltd
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SHENZHEN RIODDIN OPTOELECTRONICS TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

Abstract

本实用新型公开了一种多晶片发光二极管封装结构，包括：金属基板、多个LED芯片及金属导线，金属基板上开设用于放置LED芯片的凹腔，凹腔的底部设置有铜基底层，金属基板的上表面依次成型有第一导热绝缘层、导线层及第二导热绝缘层，LED芯片设置在铜基底层上，相邻的两个LED芯片的间距为0.5～1mm，且相邻的两个LED芯片之间填充有金属铜，LED芯片上还覆盖有荧光粉层，金属导线一端与LED芯片电性连接，另一端穿过第二导热绝缘层与导线层电性连接，铜基底层的厚度为0.25～0.3mm。本实用新型是一种使用寿命长、减少成本、提高封装效率的多晶片发光二极管封装结构。

Description

多晶片发光二极管封装结构
技术领域
本实用新型涉发光二极管封装技术领域，尤其涉及一种使用寿命长、减少成本、提高封装效率的多晶片发光二极管封装结构。
背景技术
随着LED（发光二极管）照明技术的不断发展，LED的生产规模在不断扩大，LED的封装技术是其在生产制造过程中的关键的一环。LED封装是指发光芯片的封装，相比集成电路封装有较大不同。LED的封装不仅要求能够保护灯芯，而且还要能够透光。所以LED的封装对封装材料有特殊的要求。
因此，亟需一种使用寿命长、减少成本、提高封装效率的多晶片发光二极管封装结构。
实用新型内容
本实用新型的目的是提供一种使用寿命长、减少成本、提高封装效率的多晶片发光二极管封装结构。
为了实现上述目的，本实用新型提供一种多晶片发光二极管封装结构，包括：金属基板、LED芯片及金属导线，所述金属基板上开设用于放置LED芯片的凹腔，所述凹腔的底部设置有铜基底层，所述金属基板的上表面依次成型有第一导热绝缘层、导线层及第二导热绝缘层，所述LED芯片设置在所述铜基底层上，相邻的两个所述LED芯片的间距为0.5～1mm，且相邻的两个所述LED芯片之间填充有金属铜，所述LED芯片上还覆盖有荧光粉层，所述金属导线一端与所述LED芯片电性连接，另一端穿过所述第二导热绝缘层与所述导线层电性连接，所述铜基底层的厚度为0.25～0.3mm。
所述第一导热绝缘层的厚度为45～48nm。
所述导线层为金铝合金导线层，厚度为45～48nm。
所述第二导热绝缘层的厚度为48～55nm。
所述凹腔的腔壁上还设置有镍银合金反射膜层。
所述凹腔上还覆盖封装有光学透镜层。
所述凹腔的底部与腔壁的角度为120度。
所述金属导线为金线或金铝合金线。
与现有技术相比，本实用新型多晶片发光二极管封装结构中，由于设置有所述第二导热绝缘层，因此能够覆盖住所述导线层，能够防止所述导线层在长期的高温使用过程中，被氧化，而且直接将所述第二导热绝缘层覆盖于所述导线层上，因此能够提高寿命、减少成本、提高封装效率的多晶片发光二极管封装结构。
通过以下的描述并结合附图，本实用新型将变得更加清晰，这些附图用于解释本实用新型的实施例。
附图说明
图1为本实用新型多晶片发光二极管封装结构的剖面结构示意图。
具体实施方式
现在参考附图描述本实用新型的实施例，附图中类似的元件标号代表类似的元件。如上所述，如图1所示，本实用新型提供的多晶片发光二极管封装结构100，包括：金属基板1、LED芯片2及金属导线3，所述金属基板1上开设用于放置LED芯片2的凹腔4，所述凹腔4的底部设置有铜基底层5，所述金属基板1的上表面依次成型有第一导热绝缘层6、导线层7及第二导热绝缘层8，所述LED芯片2设置在所述铜基底层5上，相邻的两个所述LED芯片2的间距为0.5～1mm，且相邻的两个所述LED芯片2之间填充有金属铜11，所述LED芯片2上还覆盖有荧光粉层12，所述金属导线3一端与所述LED芯片2电性连接，另一端穿过所述第二导热绝缘层8与所述导线层7电性连接，所述铜基底层5的厚度为0.25～0.3mm。
所述第一导热绝缘层6的厚度为45～48nm。
所述导线层7为金铝合金导线层，厚度为45～48nm。
所述第二导热绝缘层8的厚度为48～55nm。
所述凹腔4的腔壁上还设置有镍银合金反射膜层9。
所述凹腔4上还覆盖封装有光学透镜层10。
所述凹腔4的底部与腔壁的角度为120度。
所述金属导线为金线或金铝合金线。
结合图1，本实用新型多晶片发光二极管封装结构100，由于设置有所述第二导热绝缘层8，因此能够覆盖住所述导线层7，能够防止所述导线层7在长期的高温使用过程中，被氧化，而且直接将所述第二导热绝缘层8覆盖于所述导线层7上，因此能够提高寿命、减少成本、提高封装效率的多晶片发光二极管封装结构。
以上所揭露的仅为本实用新型的优选实施例而已，当然不能以此来限定本实用新型之权利范围，因此依本实用新型申请专利范围所作的等同变化，仍属本实用新型所涵盖的范围。

Claims (8)

1.一种多晶片发光二极管封装结构，其特征在于，包括：金属基板、LED芯片及金属导线，所述金属基板上开设用于放置LED芯片的凹腔，所述凹腔的底部设置有铜基底层，所述金属基板的上表面依次成型有第一导热绝缘层、导线层及第二导热绝缘层，所述LED芯片设置在所述铜基底层上，相邻的两个所述LED芯片的间距为0.5～1mm，且相邻的两个所述LED芯片之间填充有金属铜，所述LED芯片上还覆盖有荧光粉层，所述金属导线一端与所述LED芯片电性连接，另一端穿过所述第二导热绝缘层与所述导线层电性连接，所述铜基底层的厚度为0.25～0.3mm。
2.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述第一导热绝缘层的厚度为45～48nm。
3.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述导线层为金铝合金导线层，厚度为45～48nm。
4.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述第二导热绝缘层的厚度为48～55nm。
5.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述凹腔的腔壁上还设置有镍银合金反射膜层。
6.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述凹腔上还覆盖封装有光学透镜层。
7.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述凹腔的底部与腔壁的角度为120度。
8.如权利要求1所述的多晶片发光二极管封装结构，其特征在于，所述金属导线为金线或金铝合金线。
CN201320876776.0U 2013-12-27 2013-12-27 多晶片发光二极管封装结构 Expired - Fee Related CN203774322U (zh)

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Termination date: 20161227