CN203774268U - Indium phosphide wafer annealing box - Google Patents
Indium phosphide wafer annealing box Download PDFInfo
- Publication number
- CN203774268U CN203774268U CN201420162958.6U CN201420162958U CN203774268U CN 203774268 U CN203774268 U CN 203774268U CN 201420162958 U CN201420162958 U CN 201420162958U CN 203774268 U CN203774268 U CN 203774268U
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- CN
- China
- Prior art keywords
- wafer
- support column
- base
- fixed leg
- platform
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000137 annealing Methods 0.000 title claims abstract description 36
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 title abstract 3
- 239000000463 material Substances 0.000 claims abstract description 13
- 239000010453 quartz Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000013519 translation Methods 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 abstract description 101
- 230000005484 gravity Effects 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 4
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000005611 electricity Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000014616 translation Effects 0.000 description 2
- 239000003708 ampul Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The utility model discloses an indium phosphide wafer annealing box comprising a pedestal, a material holding chamber, wafer platforms, support pillars, fixing pillars and a top cover. The material holding chamber is a cavity located between the pedestal and the water platforms; the water platforms are fixed on the pedestal; a plurality of the support pillars and the fixing pillars are arranged on each water platform and are distributed in a radiating manner; and wafers are arranged on the tops of the support pillars. The indium phosphide wafer annealing box solves the problems that the annealing surface appearances of the front surfaces and the back surfaces of the wafers are inconsistent, the wafer deformation is caused by gravity and the conventional wafer annealing box has no fixed material holding chamber, enables the wafers to have excellent electric uniformity, surface integrity and geometrical parameters, allows synchronous annealing of multiple wafers and increases the production efficiency.
Description
Technical field
The utility model is applicable to the processing technique field of semi-conducting material, particularly relates to a kind of inp wafer annealing box.
Background technology
Inp wafer annealing has become a kind of important process technology.By to wafer high annealing, can reduce the thermal stress that wafer is introduced in growth course, improve the electricity uniformity of wafer, reduce the fragment rate of wafer.Inp wafer annealing process is mainly the following steps: wafer cleaning, place in annealing of wafer box, and put into appropriate red phosphorus, be sealed in quartz ampoule, put into annealing furnace and carry out high annealing, take out wafer etc.Yet, use different wafer apparatus for placing, the effect of annealing is different.Conventional mode has two kinds, that is: wafer-level is placed and wafer setting placement.Wafer-level modes of emplacement is to be generally placed on the quartz plate of level in annealing box, but wafer lower surface is different with the degree that upper surface contacts from atmosphere, thereby affects electricity uniformity and the surface integrity of wafer.It is generally between the groove or double-deck baffle plate that are placed on annealing box that wafer is erect that wafer is erect modes of emplacement, avoided like this wafer to contact inconsistent problem with atmosphere, but wafer is inevitable, not vertical placement, impact due to gravity, can there is deformation in wafer, affect the geometric parameter (TTV, TIR, Warp, BOW) of wafer in long-time high-temperature annealing process.
Application number is that the patent of 200910194785.X discloses a kind of chip bearing apparatus, in this patent, bogey contacts with the part that does not form semiconductor figure in wafer, and realize the object of bearing wafer, and the wafer that adsorbs carried by the surface tension effects of deionized water, further, select stopping means to prevent that wafer is in shifting transportation, there is lateral displacement, this apparatus structure is simple, the feature that wafer compressive strength is little, can avoid the situation of wafer fracture in load bearing process to occur.When carrying out high annealing, need to meet wafer upper and lower surface consistent with atmosphere contact, this structure and wafer edge are loop contacts, affect atmosphere and enter wafer lower surface, impact annealing effect.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of inp wafer annealing box, and wafer upper and lower surface in annealing process is basically identical with the exposure level of atmosphere, avoids wafer generation deformation.
For solving the problems of the technologies described above, technical solution adopted in the utility model is: a kind of inp wafer annealing box, it is characterized in that comprising: base, material-containing chamber, wafer platform, support column, fixed leg and top cover, described base is strip groove shape structure, its top is provided with the top cover coordinating with base, between top cover and base, be laid with more than one wafer platform, the two end supports of described wafer platform is on the two side of base, groove between wafer platform and base is material-containing chamber, on each wafer platform, there are a plurality of support columns and a plurality of fixed leg, support column and fixed leg are divergence expression and distribute, and the height of fixed leg is higher than support column, wafer is positioned over support column top, and limit wafer translation by fixed leg.
Said structure is done further preferably, between the wafer platform of the laying on described base, left space.
Said structure is done further preferably, and described support column bottom is cylindrical structure, and top is hemisphere structure; The distributing of support column is distributed as 1 of wafer platform central spot, on equally spaced 2 concentric circless, every 45 °, has 1 cylinder, totally 17.
Said structure is done further preferably, and described fixed leg bottom is cylindrical structure, and top is hemisphere structure; A plurality of fixed leg distribution wafers outside concentric circles on, every 90 °, have 1 cylinder, totally 4.
Said structure is done further preferably, and described base, material-containing chamber, wafer platform, support column, fixed leg and top cover are all made with high purity quartz.
The beneficial effect that adopts technique scheme to produce is: the utility model is for the annealing process of inp wafer, make wafer upper and lower surface basically identical with the exposure level of atmosphere, electricity uniformity and the surface integrity of wafer have been improved, simultaneously, reduce the impact of gravity on wafer geometric parameter, solved wafer positive and negative annealing surface pattern inconsistent, because gravity factor causes wafer deformation, and can realize multi-disc and anneal simultaneously, the advantage such as enhance productivity.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Fig. 1 is structural profile view of the present utility model;
Fig. 2 is the vertical view that the utility model removes top cover, and wherein the wafer platform in left side is provided with wafer, and wafer platform middle and right side is not established wafer;
Wherein: 1, base, 2, material-containing chamber, 3, wafer platform, 4, support column, 5, fixed leg, 6, top cover, 7, wafer.
Embodiment
By reference to the accompanying drawings 1,2, the utility model is elaborated, so that advantage of the present utility model and feature can be easier to be understood by these those skilled in the art, thereby protection range of the present utility model made to more explicit defining.
The utility model is specifically related to a kind of inp wafer annealing box, specifically comprise base 1, material-containing chamber 2, wafer platform 3, support column 4, fixed leg 5 and top cover 6, all with high purity quartz, make, wherein base 1 is strip groove shape structure, or be semicircular chamber, its top is provided with the top cover 6 coordinating with base 1, between top cover 6 and base 1, be laid with more than one wafer platform 3, the two end supports of described wafer platform 3 is on the two side of base 1, groove between wafer platform 3 and base 1 is material-containing chamber 2, described material-containing chamber 2 can hold the source article of atmosphere, be generally solid-state red phosphorus, there is volume large, the advantages such as easy cleaning, on each wafer platform 3, there are a plurality of support columns 4 and a plurality of fixed leg 5, support column 4 and fixed leg 5 are divergence expression and distribute, and for carrying and fixed wafer, the height of fixed leg 5 is higher than support column 4, wafer is positioned over support column 4 tops, and by fixed leg 5 restriction wafer 7 translations.
On the basis of said structure, between the wafer platform 3 of laying that can be on base 1, leave space.The quantity of wafer platform 3 in addition, can be determined by required annealing inp wafer amount once, is applicable to annealing of wafer in batches.The border circular areas diameter at wafer platform 3 middle parts can be according to wafer 7 adjusted size.The wafer of 2 inches and 3 inches for example, border circular areas diameter can be adjusted to 60 millimeters and 85 millimeters, is applicable to multiple annealing of wafer.
A plurality of support columns 4 that distribute on each described wafer platform 3, border circular areas central point is 1, take that this puts on 2 equally spaced concentric circless in the center of circle and respectively has 8.Support column on concentric circles is for to have 1 every 45° angle.Concentrically ringed spacing can be according to wafer diameter adjustment, for example 2 inches and 3 inches of wafers, and spacing is respectively 10 millimeters and 18 millimeters.Utilize this kind of structure to guarantee that each support column is evenly distributed in bottom of wafer as far as possible, make wafer self gravitation more be evenly distributed on wafer, prevent that gravity factor from causing wafer that deformation occurs in high-temperature annealing process, reduces the impact of gravity on wafer geometric parameter.The bottom of each support column 4 is the cylinder of 2 millimeters of diameters, 5 millimeters of height, and top is that radius is the hemisphere of 1 millimeter.This kind of structure can make the contact range of bottom of wafer and support column 4 only have a point, it is 1 point of hemisphere top surface center, greatly reduced the contact area of wafer and annealing of wafer box, thereby make wafer upper and lower surface consistent with the degree of atmosphere contact, improve electricity uniformity and the surface integrity of wafer.
A plurality of fixed legs 5 that distribute on each described wafer platform 3 have 1 every 90 ° of angles, totally 4 on the concentric circles at wafer platform border circular areas edge.The bottom of each fixed leg 5 is the cylinder of 2 millimeters of diameters, 8 millimeters of height, and top is that radius is the hemisphere of 1 millimeter.Fixed leg 5 is highly greater than support column 4 height, when being rocked or shake, can stop wafer slippage or drop.
Claims (5)
1. inp wafer annealing box, it is characterized in that comprising: base (1), material-containing chamber (2), wafer platform (3), support column (4), fixed leg (5) and top cover (6), described base (1) is strip groove shape structure, its top is provided with the top cover (6) coordinating with base (1), between top cover (6) and base (1), be laid with more than one wafer platform (3), the two end supports of described wafer platform (3) is on the two side of base (1), groove between wafer platform (3) and base (1) is material-containing chamber (2), on each wafer platform (3), there are a plurality of support columns (4) and a plurality of fixed leg (5), support column (4) and fixed leg (5) are divergence expression and distribute, and the height of fixed leg (5) is higher than support column (4), wafer is positioned over support column (4) top, and by the translation of fixed leg (5) restriction wafer.
2. inp wafer according to claim 1 annealing box, is characterized in that leaving space between the wafer platform (3) of the laying on described base (1).
3. inp wafer annealing box according to claim 1, is characterized in that described support column (4) bottom is cylindrical structure, and top is hemisphere structure; The distributing of support column (4) is distributed as 1 of wafer platform (3) central spot, on equally spaced 2 concentric circless, every 45 °, has 1 cylinder, totally 17.
4. inp wafer annealing box according to claim 1, is characterized in that described fixed leg (5) bottom is cylindrical structure, and top is hemisphere structure; A plurality of fixed legs (5) distribution wafer outside concentric circles on, every 90 °, have 1 cylinder, totally 4.
5. according to the inp wafer annealing box described in any one in claim 1～4, it is characterized in that described base (1), material-containing chamber (2), wafer platform (3), support column (4), fixed leg (5) and top cover (6) all make with high purity quartz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420162958.6U CN203774268U (en) | 2014-04-04 | 2014-04-04 | Indium phosphide wafer annealing box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420162958.6U CN203774268U (en) | 2014-04-04 | 2014-04-04 | Indium phosphide wafer annealing box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203774268U true CN203774268U (en) | 2014-08-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420162958.6U Expired - Lifetime CN203774268U (en) | 2014-04-04 | 2014-04-04 | Indium phosphide wafer annealing box |
Country Status (1)
| Country | Link |
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| CN (1) | CN203774268U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928369A (en) * | 2014-04-04 | 2014-07-16 | 中国电子科技集团公司第十三研究所 | Indium phosphide wafer annealing box |
| CN110491774A (en) * | 2019-08-19 | 2019-11-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of surface treatment method of Sapphire Substrate and its crucible used |
-
2014
- 2014-04-04 CN CN201420162958.6U patent/CN203774268U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103928369A (en) * | 2014-04-04 | 2014-07-16 | 中国电子科技集团公司第十三研究所 | Indium phosphide wafer annealing box |
| CN103928369B (en) * | 2014-04-04 | 2016-07-13 | 中国电子科技集团公司第十三研究所 | Inp wafer annealing box |
| CN110491774A (en) * | 2019-08-19 | 2019-11-22 | 中国科学院苏州纳米技术与纳米仿生研究所 | A kind of surface treatment method of Sapphire Substrate and its crucible used |
| CN110491774B (en) * | 2019-08-19 | 2021-10-26 | 中国科学院苏州纳米技术与纳米仿生研究所 | Surface treatment method of sapphire substrate and crucible used by surface treatment method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140813 |
|
| CX01 | Expiry of patent term |