CN203773019U - Chip test system - Google Patents
Chip test system Download PDFInfo
- Publication number
- CN203773019U CN203773019U CN201420186734.9U CN201420186734U CN203773019U CN 203773019 U CN203773019 U CN 203773019U CN 201420186734 U CN201420186734 U CN 201420186734U CN 203773019 U CN203773019 U CN 203773019U
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- CN
- China
- Prior art keywords
- chip
- toggle switch
- electrically connected
- pair
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a chip test system which comprises a transistor curve tracer used for testing chips, and a chip test seat electrically connected with the transistor curve tracer. The chip test seat comprises a base. The lower surface of the base is provided with at least one pair of pins used for being connected with the transistor curve tracer in an inserting mode. The pair of pins fits a pair of test jacks on the transistor curve tracer. The upper surface of the base is provided with a first dial switch, a second dial switch and a chip fixture. One of the pins is electrically connected with the first dial switch, the first dial switch is electrically connected with the chip fixture, the chip fixture is electrically connected with the second dial switch, and the second dial switch is electrically connected with the other of the pins. The chip test system of the utility model makes chip test operation simple and test efficiency high.
Description
Technical field
The utility model relates to chip testing field, particularly a kind of chip test system that utilizes Tektronix370A transistor graphic instrument test chip.
Background technology
While utilizing at present Tektronix 370A transistor graphic instrument to semiconductor die testing, need to manually use the conductor connecting core sheet respective pins with plug to arrive in the respective socket of transistor graphic instrument, realize being connected of chip and transistor graphic instrument, thereby complete the test of follow-up different unit for electrical property parameters, this mode needs the artificial line of operating personnel, and do not stop to plug line trap and be connected on transistor graphic instrument, complex operation is easily made mistakes, and chip testing efficiency is low.
Utility model content
The purpose of this utility model is to overcome existing above-mentioned deficiency in prior art, provides a kind of simple to operate, the chip test system that chip testing efficiency is high.
In order to realize foregoing invention object, the technical solution adopted in the utility model is:
A kind of chip test system, comprise the Tektronix 370A transistor npn npn graphic instrument for chip is tested, also comprise the chip test base being electrically connected to described Tektronix 370A transistor npn npn graphic instrument, this chip test base comprises pedestal, described pedestal lower surface arranges at least one pair of for the pin of socket connection Tektronix 370A transistor npn npn graphic instrument, and one group of test jack on described pair of pins and Tektronix 370A transistor npn npn graphic instrument is adaptive; Described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, and another pin in described the second toggle switch and described pair of pins is electrically connected.
Preferably, described pin has 3 pairs, every pair of pins respectively with Tektronix 370A transistor npn npn graphic instrument on one group of test jack adaptive.
Described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
Described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
compared with prior art, the beneficial effects of the utility model:
During chip test system work of the present utility model, chip is put into chip fixture fixing, chip respective pins is electrically connected to two toggle switchs by chip fixture, and two toggle switchs are electrically connected to the pair of pins of chip test base lower surface respectively, during test, at least one pair of pin of chip test base lower surface is inserted on transistor graphic instrument in corresponding test jack, realize being electrically connected to of chip pin and transistor graphic instrument, the break-make that realizes test circuit by two toggle switchs on chip test base is controlled, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, also make chip testing efficiency greatly improve.
accompanying drawing explanation:
Fig. 1 is the schematic diagram of the chip test system in the utility model embodiment;
Fig. 2 is the structural representation of the chip test base in Fig. 1;
Fig. 3 is the chip fixture structural representation in Fig. 2;
Fig. 4 is the transistor graphic instrument schematic diagram in the utility model embodiment.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the utility model only limits to following embodiment, all technology realizing based on the utility model content all belong to scope of the present utility model.
Chip test system as shown in Figure 1, comprises the Tektronix 370A transistor npn npn graphic instrument 6 for chip is tested, and also comprises the chip test base being electrically connected to described Tektronix 370A transistor npn npn graphic instrument 6.Referring to Fig. 2, this chip test base comprises pedestal 1, described pedestal 1 lower surface arranges at least one pair of for connecting the pin 2 of transistor graphic instrument, pin described in the present embodiment 2 be take two pairs as example explanation, described transistor graphic instrument is Tektronix 370A transistor npn npn graphic instrument (see figure 4), on it, there are a plurality of test jack, described pair of pins 2 is adaptive with one group of test jack on this transistor graphic instrument, Fig. 2 is only schematic diagram, where pin 2 is to determine according to the test jack position on transistor graphic instrument if being arranged on pedestal 1 lower surface, both want adaptive mutually, so that aim at, peg graft.Described pedestal 1 upper surface is provided with the first toggle switch 3, the second toggle switch 4 and chip fixture 5.Referring to Fig. 3, a pin and described the first toggle switch 3 in described pair of pins 2 are electrically connected, described the first toggle switch 3 is electrically connected with described chip fixture 5, described chip fixture 5 is electrically connected with described the second toggle switch 4, and described the second toggle switch 4 is electrically connected with another pin in described pair of pins 2.Concrete, described the first toggle switch 3 is symmetricly set on described pedestal 1 upper surface two ends with described the second toggle switch 4, and described chip fixture 5 is between the first toggle switch 3 and the second toggle switch 4.Toggle switch (3,4) comprises a plurality of toggle switches unit, the present embodiment be take 2 waved switch unit as example explanation, a waved switch unit on each toggle switch, the pair of pins 2 of connecting test seat lower surface is distinguished in one end, one group of waved switch unit, and this group waved switch unit other end is electrically connected to described chip fixture 5 respectively again.Referring to Fig. 3, chip fixture comprises basis 501, has for chip fixing pickup groove 502 and the stitch 503 contacting with chip pin on body 501, and described stitch 503 is positioned at the two bottom sides of described pickup groove 502 and stretches out described body 501.Waved switch unit on toggle switch (3,4) is connected with the corresponding stitch 503 of chip fixture 5, and the corresponding test jack that test bench pin 2 inserts transistor graphic instrument, has so just realized the electric connection of chip and transistor graphic instrument.
Chip test system of the present utility model is that inventor utilizes for convenience Tektronix 370A transistor npn npn graphic instrument test chip and invents, for Tektronix 370A transistor npn npn graphic instrument, design specially, during work, chip is put into chip fixture 5 fixing, chip respective pins is by stitch 503 and two toggle switchs (3 on chip fixture 5, 4) be electrically connected to, and two toggle switchs (i.e. one group of waved switch unit) are electrically connected to the pair of pins 2 of chip test base lower surface respectively, during test, at least one pair of pin 2 of chip test base lower surface is inserted in the corresponding test jack of transistor graphic instrument, realize being electrically connected to of chip pin and transistor graphic instrument, by two toggle switchs on chip test base, realize the control of test circuit, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, also make chip testing efficiency greatly improve.
As preferred version of the present utility model, the pin 2 of described test bench lower surface has 3 pairs of (not shown), every pair of pins respectively with transistor graphic instrument on one group of test jack adaptive.Toggle switch comprises a plurality of toggle switches unit, a waved switch unit on each toggle switch, i.e. one group of waved switch unit pair of pins of connecting test seat lower surface respectively, this group waved switch unit other end is electrically connected to described chip fixture respectively again, chip fixture has the stitch contacting with chip pin, waved switch unit is connected with the corresponding stitch of chip fixture, test bench pin inserts the corresponding test jack of transistor graphic instrument, so just realized being connected of chip and transistor graphic instrument, each group jack on transistor graphic instrument is for testing different parameters, break-make by toggle switch unit on two toggle switchs during test combines, realize the connection of chip pin and the different test jack of transistor graphic instrument, can conveniently carry out multiple parameters test, testing efficiency further improves.
By reference to the accompanying drawings embodiment of the present utility model is had been described in detail above, but the utility model is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various modifications or remodeling.
Claims (4)
1. a chip test system, comprise the Tektronix 370A transistor npn npn graphic instrument for chip is tested, it is characterized in that, also comprise the chip test base being electrically connected to described Tektronix 370A transistor npn npn graphic instrument, this chip test base comprises pedestal, described pedestal lower surface arranges at least one pair of for the pin of socket connection Tektronix 370A transistor npn npn graphic instrument, and one group of test jack on described pair of pins and Tektronix 370A transistor npn npn graphic instrument is adaptive; Described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, and another pin in described the second toggle switch and described pair of pins is electrically connected.
2. chip test system according to claim 1, is characterized in that, described pin has 3 pairs, every pair of pins respectively with Tektronix 370A transistor npn npn graphic instrument on one group of test jack adaptive.
3. chip test system according to claim 1, is characterized in that, described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
4. according to the chip test system described in claim 1-3 any one, it is characterized in that, described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420186734.9U CN203773019U (en) | 2014-04-16 | 2014-04-16 | Chip test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420186734.9U CN203773019U (en) | 2014-04-16 | 2014-04-16 | Chip test system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203773019U true CN203773019U (en) | 2014-08-13 |
Family
ID=51290196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420186734.9U Expired - Fee Related CN203773019U (en) | 2014-04-16 | 2014-04-16 | Chip test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203773019U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049194A (en) * | 2014-04-16 | 2014-09-17 | 成都先进功率半导体股份有限公司 | Chip testing system |
-
2014
- 2014-04-16 CN CN201420186734.9U patent/CN203773019U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104049194A (en) * | 2014-04-16 | 2014-09-17 | 成都先进功率半导体股份有限公司 | Chip testing system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140813 Termination date: 20160416 |