CN103926429A - Chip test socket - Google Patents
Chip test socket Download PDFInfo
- Publication number
- CN103926429A CN103926429A CN201410154263.8A CN201410154263A CN103926429A CN 103926429 A CN103926429 A CN 103926429A CN 201410154263 A CN201410154263 A CN 201410154263A CN 103926429 A CN103926429 A CN 103926429A
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- chip
- toggle switch
- pair
- electrically connected
- pin
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- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a chip test socket which comprises a base. The lower surface of the base is provided with at least one pair of pins used for being connected with a transistor graphic instrument. The pair of pins are matched with a set of test jacks in the transistor graphic instrument. The upper surface of the base is provided with a first dial switch, a second dial switch and a chip clamp. One of the pair of pins is electrically connected with the first dial switch, the first dial switch is electrically connected with the chip clamp, the chip clamp is electrically connected with the second dial switch, and the second dial switch is electrically connected with the other pin of the pair of pins. According to the chip test socket, a chip test is easy to operate and high in test efficiency.
Description
Technical field
The present invention relates to chip testing field, particularly a kind of chip test base that utilizes Tektronix370A transistor graphic instrument test chip.
Background technology
While utilizing at present Tektronix 370A transistor graphic instrument to semiconductor die testing, need to manually use the conductor connecting core sheet respective pins with plug to arrive in the respective socket of transistor graphic instrument, realize being connected of chip and transistor graphic instrument, thereby complete the test of follow-up different unit for electrical property parameters, this mode needs the artificial line of operating personnel, and do not stop to plug line trap and be connected on transistor graphic instrument, complex operation is easily made mistakes, and chip testing efficiency is low.
Summary of the invention
The object of the invention is to overcome existing above-mentioned deficiency in prior art, provide a kind of simple to operate, the chip test base that chip testing efficiency is high.
In order to realize foregoing invention object, the technical solution used in the present invention is:
A chip test base, comprises pedestal, and described pedestal lower surface arranges at least one pair of for connecting the pin of transistor graphic instrument, and one group of test jack on described pair of pins and transistor graphic instrument is adaptive; Described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, and another pin in described the second toggle switch and described pair of pins is electrically connected.
Described transistor graphic instrument is Tektronix 370A transistor npn npn graphic instrument.
Preferably, described pin has 3 pairs, every pair of pins respectively with transistor graphic instrument on one group of test jack adaptive.
Described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
Described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
compared with prior art, beneficial effect of the present invention:
When chip test base of the present invention is used, chip is put into chip fixture fixing, chip respective pins is electrically connected to two toggle switchs by chip fixture, and two toggle switchs are electrically connected to the pair of pins of chip test base lower surface respectively, during test, at least one pair of pin of chip test base lower surface is inserted on transistor graphic instrument in corresponding test jack, realize being electrically connected to of chip pin and transistor graphic instrument, the break-make that realizes test circuit by two toggle switchs on chip test base is controlled, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, also make chip testing efficiency greatly improve.
accompanying drawing explanation:
Fig. 1 is the structural representation of the chip test base in the embodiment of the present invention.
Fig. 2 is the chip fixture structural representation in Fig. 1.
Fig. 3 is the circuit block diagram of the chip test base in the embodiment of the present invention.
Fig. 4 is the transistor graphic instrument schematic diagram in the embodiment of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following embodiment, all technology realizing based on content of the present invention all belong to scope of the present invention.
Chip test base as shown in Figure 1, comprise pedestal 1, described pedestal 1 lower surface arranges at least one pair of for connecting the pin 2 of transistor graphic instrument, pin described in the present embodiment 2 be take two pairs as example explanation, described transistor graphic instrument is Tektronix 370A transistor npn npn graphic instrument (see figure 4), on it, there are a plurality of test jack, described pair of pins 2 is adaptive with one group of test jack on this transistor graphic instrument, Fig. 1 is only schematic diagram, where pin 2 is to determine according to the test jack on transistor graphic instrument if being arranged on pedestal lower surface, both want adaptive mutually, so that aim at, peg graft.Described pedestal 1 upper surface is provided with the first toggle switch 3, the second toggle switch 4 and chip fixture 5.Referring to Fig. 3, a pin and described the first toggle switch 3 in described pair of pins 2 are electrically connected, described the first toggle switch 3 is electrically connected with described chip fixture 5, described chip fixture 5 is electrically connected with described the second toggle switch 4, and described the second toggle switch 4 is electrically connected with another pin in described pair of pins 2.Concrete, described the first toggle switch 3 is symmetricly set on described pedestal 1 upper surface two ends with described the second toggle switch 4, and described chip fixture 5 is between the first toggle switch 3 and the second toggle switch 4.Toggle switch (3, 4) comprise a plurality of toggle switches unit, the present embodiment be take 2 waved switch unit as example explanation, a waved switch unit on each toggle switch, the pair of pins 2 of connecting test seat lower surface is distinguished in one end, one group of waved switch unit, this group waved switch unit other end is electrically connected to described chip fixture 5 respectively again, referring to Fig. 2, chip fixture comprises basis 501, on body 501, have for chip fixing pickup groove 502 and the stitch 503 contacting with chip pin, described stitch 503 is positioned at the two bottom sides of described pickup groove 502 and stretches out described body 501.Waved switch unit on toggle switch (3,4) is connected with the corresponding stitch 503 of chip fixture 5, and the corresponding test jack that test bench pin 2 inserts transistor graphic instrument, has so just realized the electric connection of chip and transistor graphic instrument.
Chip test base of the present invention is that inventor utilizes for convenience Tektronix 370A transistor npn npn graphic instrument test chip and invents, for Tektronix 370A transistor npn npn graphic instrument, design specially, during use, chip is put into chip fixture 5 fixing, chip respective pins is by stitch 503 and two toggle switchs (3 on chip fixture 5, 4) be electrically connected to, and two toggle switchs (i.e. one group of waved switch unit) are electrically connected to the pair of pins 2 of chip test base lower surface respectively, during test, at least one pair of pin 2 of chip test base lower surface is inserted in the corresponding test jack of transistor graphic instrument, realize being electrically connected to of chip pin and transistor graphic instrument, by two toggle switchs on chip test base, realize the control of test circuit, operating personnel only need plug chip test base and connect, remove manual line from, simple to operate being difficult for makes mistakes, also make chip testing efficiency greatly improve.
As preferred version of the present invention, the pin 2 of described test bench lower surface has 3 pairs of (not shown), every pair of pins respectively with transistor graphic instrument on one group of test jack adaptive.Toggle switch comprises a plurality of toggle switches unit, a waved switch unit on each toggle switch, i.e. one group of waved switch unit pair of pins of connecting test seat lower surface respectively, this group waved switch unit other end is electrically connected to described chip fixture respectively again, chip fixture has the stitch contacting with chip pin, waved switch unit is connected with the corresponding stitch of chip fixture, test bench pin inserts the corresponding test jack of transistor graphic instrument, so just realized being connected of chip and transistor graphic instrument, each group jack on transistor graphic instrument is for testing different parameters, break-make by toggle switch unit on two toggle switchs during test combines, realize the connection of chip pin and the different test jack of transistor graphic instrument, can conveniently carry out multiple parameters test, testing efficiency further improves.
By reference to the accompanying drawings the specific embodiment of the present invention is had been described in detail above, but the present invention is not restricted to above-mentioned embodiment, in the spirit and scope situation of claim that does not depart from the application, those skilled in the art can make various modifications or remodeling.
Claims (5)
1. a chip test base, comprises pedestal, it is characterized in that, described pedestal lower surface arranges at least one pair of for connecting the pin of transistor graphic instrument, and one group of test jack on described pair of pins and transistor graphic instrument is adaptive; Described pedestal upper surface is provided with the first toggle switch, the second toggle switch and chip fixture, a pin and described the first toggle switch in described pair of pins are electrically connected, described the first toggle switch and described chip fixture are electrically connected, described chip fixture and described the second toggle switch are electrically connected, and another pin in described the second toggle switch and described pair of pins is electrically connected.
2. chip test base according to claim 1, is characterized in that, described transistor graphic instrument is Tektronix 370A transistor npn npn graphic instrument.
3. chip test base according to claim 1, is characterized in that, described pin has 3 pairs, every pair of pins respectively with transistor graphic instrument on one group of test jack adaptive.
4. chip test base according to claim 1, is characterized in that, described the first toggle switch and described the second toggle switch are symmetricly set on described pedestal upper surface two ends, and described chip fixture is between the first toggle switch and the second toggle switch.
5. according to the chip test base described in claim 1-4 any one, it is characterized in that, described chip fixture comprises body, and this body has for the fixing pickup groove of chip and stitch for contacting with chip pin, and described stitch is positioned at the two bottom sides of described pickup groove and stretches out described body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410154263.8A CN103926429A (en) | 2014-04-16 | 2014-04-16 | Chip test socket |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410154263.8A CN103926429A (en) | 2014-04-16 | 2014-04-16 | Chip test socket |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103926429A true CN103926429A (en) | 2014-07-16 |
Family
ID=51144721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410154263.8A Pending CN103926429A (en) | 2014-04-16 | 2014-04-16 | Chip test socket |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103926429A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105630527A (en) * | 2014-11-04 | 2016-06-01 | 鸿富锦精密工业(武汉)有限公司 | BIOS (Basic Input Output System) chip burning clamp |
| CN109490738A (en) * | 2018-11-05 | 2019-03-19 | 南京中电熊猫晶体科技有限公司 | A kind of measuring device of crystal oscillator diode characteristic |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262581B1 (en) * | 1998-04-20 | 2001-07-17 | Samsung Electronics Co., Ltd. | Test carrier for unpackaged semiconducter chip |
| CN2704050Y (en) * | 2003-12-12 | 2005-06-08 | 上海新建仪器设备有限公司 | Surface-pasted semiconductor device test seat |
| CN101226233A (en) * | 2007-01-19 | 2008-07-23 | 旺宏电子股份有限公司 | Method and apparatus for testing chip testing mechanism |
| CN101452030A (en) * | 2007-11-28 | 2009-06-10 | 京元电子股份有限公司 | Test device with switching element on socket substrate |
| CN203519658U (en) * | 2013-09-03 | 2014-04-02 | 苏州创瑞机电科技有限公司 | Automatic test socket of megapixel-level CMOS optical chip module |
| CN203838179U (en) * | 2014-04-16 | 2014-09-17 | 成都先进功率半导体股份有限公司 | Chip testing base |
-
2014
- 2014-04-16 CN CN201410154263.8A patent/CN103926429A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6262581B1 (en) * | 1998-04-20 | 2001-07-17 | Samsung Electronics Co., Ltd. | Test carrier for unpackaged semiconducter chip |
| CN2704050Y (en) * | 2003-12-12 | 2005-06-08 | 上海新建仪器设备有限公司 | Surface-pasted semiconductor device test seat |
| CN101226233A (en) * | 2007-01-19 | 2008-07-23 | 旺宏电子股份有限公司 | Method and apparatus for testing chip testing mechanism |
| CN101452030A (en) * | 2007-11-28 | 2009-06-10 | 京元电子股份有限公司 | Test device with switching element on socket substrate |
| CN203519658U (en) * | 2013-09-03 | 2014-04-02 | 苏州创瑞机电科技有限公司 | Automatic test socket of megapixel-level CMOS optical chip module |
| CN203838179U (en) * | 2014-04-16 | 2014-09-17 | 成都先进功率半导体股份有限公司 | Chip testing base |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105630527A (en) * | 2014-11-04 | 2016-06-01 | 鸿富锦精密工业(武汉)有限公司 | BIOS (Basic Input Output System) chip burning clamp |
| CN109490738A (en) * | 2018-11-05 | 2019-03-19 | 南京中电熊猫晶体科技有限公司 | A kind of measuring device of crystal oscillator diode characteristic |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20140716 |
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| RJ01 | Rejection of invention patent application after publication |