CN203745823U - Control signal generating circuit - Google Patents
Control signal generating circuit Download PDFInfo
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- CN203745823U CN203745823U CN201320828620.5U CN201320828620U CN203745823U CN 203745823 U CN203745823 U CN 203745823U CN 201320828620 U CN201320828620 U CN 201320828620U CN 203745823 U CN203745823 U CN 203745823U
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Abstract
The utility model discloses a control signal generating circuit in the technical field of signal processing. The control signal generating circuit comprises a signal acquisition circuit, a signal processing circuit and a logic output circuit, wherein the signal acquisition circuit is used for acquiring a pulse signal of first equipment, the signal processing circuit is used for delaying the rising edge of the pulse signal to obtain a first signal and advancing the falling edge of the pulse signal to obtain a second signal, and the logic output circuit is used for carrying out logic processing to the pulse signal, the first signal and the second signal to obtain a control signal, delayed relative to the rising edge of the pulse signal and advanced relative to the falling edge of the pulse signal, of second equipment. The control signal generating circuit can be applied to a variety of man-machine interactive devices and has a wide range of application; the circuit is simple to implement, less susceptible to interference of external environments and is accurate in result; and no expensive processors are used, other software is not needed, and the manufacturing cost and the cost of software are greatly reduced.
Description
Technical field
The utility model relates to signal processing technology field, relates in particular to a kind of control signal generative circuit.
Background technology
Electronic product is extensively present in modern production and life, for people's work and life provide a great convenience.
Along with scientific and technological development, there is the electronic equipment of a lot of human-computer interaction classes.This class of electronic devices is generally divided into two large divisions.Part equipment is the part that is through user with it or needs user to grip, i.e. sports equipment, and as LED lamp, infrared lamp, signal transmitting bar etc., this equipment component is for the operation of marking users; Another part equipment fixed placement in place, carries out signals collecting and signal processing, i.e. fixed equipment by being through operation or the action to user of equipment that equipment with it of user or user grip.Signals collecting realizes by video capture conventionally, as camera or other signal receiver.The equipment of common human-computer interaction class has motion simulator, electronic game machine etc.
This type of human-computer interaction equipment in use, is normally first opened sports equipment, and then opens the signal of fixed equipment acquisition and processing sports equipment.While stopping using, first close fixed equipment and then closing movement equipment.That is, sports equipment is opened rear fixed equipment and is just opened, and sports equipment is closed front fixed equipment and will be closed.Consider from the angle of signal to be exactly, sports equipment sends fixed equipment after commencing signal and just starts to gather the signal of sports equipment, and the front fixed equipment of sports equipment shutdown signal will stop gathering the signal of sports equipment.
This process can, by manually realizing, also can be equipped with corresponding software realization by starting control device.The using method of existing startup control device is: utilize the input/output port of chip, follow the switch of controlling camera device according to the switching time of receiver apparatus, achieve the switching function of above-mentioned sports equipment and fixed equipment.But can take like this input/output port of miscellaneous equipment, and need independent processor to realize this process, like this, both taken this with regard to few input/output port, increase again the expense of purchasing processor, increase the manufacturing cost of human-computer interaction equipment, be unfavorable for the universal of human-computer interaction equipment.
Summary of the invention
Take input/output port, the high deficiency of manufacturing cost in order to solve the startup opertaing device existing in existing human-computer interaction equipment, the utility model provides a kind of control signal generative circuit.
The technical solution of the utility model is: a kind of control signal generative circuit, for generate the control signal of the second equipment according to the pulse signal of the first equipment, so that the second equipment is also closed in advance with respect to the first equipment delayed start-up; This control signal generative circuit comprises: signal acquisition circuit, signal processing circuit and logic output circuit;
Described signal acquisition circuit is for obtaining the pulse signal of described the first equipment;
Described signal processing circuit obtains first signal for the rising edge of described pulse signal is carried out to delay operation; And the negative edge of described pulse signal is operated in advance and obtains secondary signal;
Described logic output circuit is for carrying out logical process to described pulse signal, first signal and secondary signal, obtains the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge.
Preferably, described signal processing circuit comprises that waveform changing circuit, rising edge delay circuit and negative edge shift to an earlier date circuit;
Described rising edge delay circuit comprises that the first current potential arranges circuit and the first comparator circuit;
Described negative edge shifts to an earlier date circuit and comprises that the second current potential arranges circuit and the second comparator circuit;
The output terminal of circuit is set described the first current potential and the second input end of the first comparator circuit is connected;
The output terminal of circuit is set described the second current potential and the second input end of the second comparator circuit is connected;
The input end of described waveform changing circuit is connected with described signal acquisition circuit, and the output terminal of described waveform changing circuit is connected with the first input end of described the first comparator circuit and the first input end of the second comparator circuit respectively.
Preferably, described waveform changing circuit for by described pulse signal from rising edge to negative edge between waveform transformation be amplitude monotonically increasing signal, and by described pulse signal from negative edge to rising edge between waveform transformation be the signal of amplitude monotone decreasing.
Preferably, described the first current potential arranges circuit and comprises the first resistance and the second resistance; The first end of described the first resistance is connected with power supply; The second end of described the first resistance is connected with the first end of described the second resistance; The second end ground connection of described the second resistance; The first end of described the second resistance is connected with the second input end of described the first comparator circuit;
Described the second current potential arranges circuit and comprises the 3rd resistance and the 4th resistance; The first end of described the 3rd resistance is connected with power supply; The second end of described the 3rd resistance is connected with the first end of described the 4th resistance; The second end ground connection of described the 4th resistance; The first end of described the 4th resistance is connected with the second input end of described the second comparator circuit;
Described the first comparator circuit comprises the first comparer; The second input end of described the first comparer is connected with the output terminal that described the first current potential arranges circuit; The first input end of described the first comparer is connected with the output terminal of described waveform changing circuit;
Described the second comparator circuit comprises the second comparer; The second input end of described the second comparer is connected with the output terminal that described the second current potential arranges circuit; Described the second comparer first input end is connected with the output terminal of described waveform changing circuit.
Preferably, described waveform changing circuit comprises the 5th resistance and the first electric capacity; The first end of described the 5th resistance is connected with described signal acquisition circuit; The second end of described the 5th resistance is connected with the first end of described the first electric capacity; The second end ground connection of described the first electric capacity; The first end of described the first electric capacity is connected with the first input end of described the first comparator circuit and the first input end of the second comparator circuit respectively.
Preferably, described logic output circuit comprises the first logical circuit and the second logical circuit;
Described the first logical circuit carries out logic xor operation for the described secondary signal of the described first signal to described the first comparator circuit output and the output of the second comparator circuit;
Described the second logical circuit carries out logical and operation for output signal and described pulse signal to described the first logical circuit;
The first input end of described the first logical circuit is connected with the output terminal of described the first comparator circuit; The second input end of described the first logical circuit is connected with the output terminal of described the second comparator circuit; The first input end of described the second logical circuit is connected with the output terminal of described the first logical circuit; The second input end of described the second logical circuit is connected with described signal acquisition circuit.
Preferably, described circuit further comprises: executive circuit, for the control signal by described the second equipment, described the second equipment is controlled.
Preferably, described executive circuit comprises the 6th resistance and triode;
The first end of described the 6th resistance is connected with the output terminal of described the second logical circuit; The base stage of described triode is connected with the second end of described the 6th resistance; The collector of described triode and described the second equipment connection; The grounded emitter of described triode.
Preferably, the current potential of the first end of described the second resistance is lower than the current potential of the first end of described the 4th resistance; The current potential of the first end of described the 4th resistance is lower than described amplitude monotonically increasing signal.
Preferably, described the first equipment is LED lamp, infrared lamp or sensor;
The second equipment is camera, audio collection device, range finder or hygrosensor.
First the utility model obtains the pulse signal of described the first equipment, then the rising edge of described pulse signal is carried out to delay operation and obtains first signal; And the negative edge of described pulse signal is operated in advance and obtains secondary signal, the time that delay operation starts and the in advance time of EO can be set as required flexibly, can be applicable to multiple man-machine interaction device, applied widely; By to delay operation and in advance the secondary signal that obtains of operation carry out simple logical process, just can obtain the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge, process is simple, is not subject to external environmental interference, and result is accurate; Do not use expensive processor, do not need other softwares yet, greatly reduced manufacturing cost and software cost.
Brief description of the drawings
Fig. 1 is the circuit structure diagram of embodiment 1;
Fig. 2 is the circuit connection diagram of embodiment 1;
Fig. 3 is the oscillogram of the first equipment of embodiment 1;
Fig. 4 is the oscillogram that the oscillogram of the first equipment of embodiment 1 obtains through waveform transformation;
Fig. 5 is starting circuit by time delay the waveform of Fig. 4 being carried out to oscillogram after treatment of embodiment 1;
Fig. 6 be embodiment 1 pass through finish in advance circuit the waveform of Fig. 4 carried out to oscillogram after treatment;
Fig. 7 obtains oscillogram after the waveform processing of passing through the waveform of the first logical circuit to Fig. 5 and Fig. 6 of embodiment 1;
Fig. 8 is that second logical circuit that passes through of embodiment 1 obtains oscillogram after to the waveform processing of Fig. 7;
Fig. 9 is the circuit connection diagram of embodiment 2.
Embodiment
For making object, technical scheme and the advantage of the utility model embodiment clearer, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly described, obviously, described embodiment is the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model provides a kind of control signal generative circuit, takies input/output port, the high deficiency of manufacturing cost to solve the startup opertaing device existing in existing human-computer interaction equipment.
The utility model is only controlled the zero hour and the finish time of the sports equipment to human-computer interaction equipment, and the signal of the sports equipment that after sports equipment not being opened, fixed equipment detects is processed.
Embodiment 1
The technical scheme of the present embodiment is: a kind of control signal generative circuit, for generate the control signal of the second equipment according to the pulse signal of the first equipment, so that the second equipment is also closed in advance with respect to the first equipment delayed start-up; Described the first equipment is that LED lamp, infrared lamp or sensor signal receive or sensing apparatus; The second equipment is the signal collecting devices such as camera, audio collection device (for example gathering the equipment of voice), range finder or hygrosensor.This control signal generative circuit comprises:
1, signal acquisition circuit, for obtaining the pulse signal of described the first equipment;
2, signal processing circuit, obtains first signal for the rising edge of described pulse signal is carried out to delay operation; And the negative edge of described pulse signal is operated in advance and obtains secondary signal;
3, logic output circuit, for described pulse signal, first signal and secondary signal are carried out to logical process, obtains the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge.
Described signal acquisition circuit is connected with described signal processing circuit and logic output circuit respectively; Described signal processing circuit is connected with logic output circuit.The circuit structure diagram of the present embodiment as shown in Figure 1.
First the utility model obtains the pulse signal of described the first equipment, then the rising edge of described pulse signal is carried out to delay operation and obtains first signal; And the negative edge of described pulse signal is operated in advance and obtains secondary signal, the time that delay operation starts and the in advance time of EO can be set as required flexibly, can be applicable to multiple man-machine interaction device, applied widely; By to delay operation and in advance the secondary signal that obtains of operation carry out simple logical process, just can obtain the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge, process is simple, is not subject to external environmental interference, and result is accurate; Do not use expensive processor, do not need other softwares yet, greatly reduced manufacturing cost and software cost.
The described signal acquisition circuit of the present embodiment is generally the signal receiver with the sports equipment wireless connections of human-computer interaction equipment, is generally pulse-width modulation PWM signal.Due to state or the unlatching of sports equipment, close, be reacted on signal pwm signal and square-wave signal similar, for convenience, the utility model replaces pwm signal with standard square-wave signal, the experiment proved that, it is identical that pwm signal and square-wave signal are applied in actual effect in the utility model.
Square-wave signal or be high level, or be low level, between high level and low level, be transient change, cannot start time delay and finish in advance by the amplitude of square-wave signal to arrange.So, square-wave signal need to be converted to amplitude continually varying waveform in time.
The described signal processing circuit of the present embodiment comprises that waveform changing circuit, rising edge delay circuit and negative edge shift to an earlier date circuit;
(1) described rising edge delay circuit comprises that the first current potential arranges circuit and the first comparator circuit;
The output terminal of circuit is set described the first current potential and the second input end of the first comparator circuit is connected;
(2) described negative edge shifts to an earlier date circuit and comprises that the second current potential arranges circuit and the second comparator circuit;
The output terminal of circuit is set described the second current potential and the second input end of the second comparator circuit is connected;
(3) described waveform changing circuit for by described pulse signal (this example is square-wave signal) from rising edge to negative edge between waveform transformation be amplitude monotonically increasing signal; And by described pulse signal (being square-wave signal in this example) from negative edge to rising edge between waveform transformation be the signal of amplitude monotone decreasing.
The input end of described waveform changing circuit is connected with described signal acquisition circuit; The output terminal of described waveform changing circuit is connected with the first input end of described the first comparator circuit and the first input end of the second comparator circuit respectively.
Can select following actual device to realize the annexation of signal processing circuit described above:
Described waveform changing circuit comprises the 5th resistance R 5 and the first capacitor C 1; The first end of described the 5th resistance R 5 is connected with described signal acquisition circuit (being the signal receiver shown in Fig. 2); The second end of described the 5th resistance R 5 is connected with the first end of described the first capacitor C 1; The second end ground connection of described the first capacitor C 1; The first end of described the first capacitor C 1 is connected with the signal input part (i.e. the first end of the first comparer A1) of described the first comparator circuit and the signal input part (i.e. the first end of the second comparer A2) of the second comparator circuit respectively.
Described the first current potential arranges circuit and comprises the first resistance R 1 and the second resistance R 2; The first end of described the first resistance R 1 is connected with power vd D; The second end of described the first resistance R 1 is connected with the first end of described the second resistance R 2; The second end ground connection of described the second resistance R 2; The first end (the first current potential arranges the output terminal of circuit) of described the second resistance R 2 is connected with the second input end of described the first comparator circuit.The resistance of the resistance of the first resistance R 1 and the second resistance R 2 arranges according to the amplitude ratio that accounts for electric signal of electric signal corresponding to time delay zero hour, as, when the amplitude half that is electric signal of electric signal corresponding to time delay zero hour, the resistance of the first resistance R 1 is identical with the resistance of the second resistance R 2; When time delay zero hour, the amplitude of corresponding electric signal is electric signal 30% time, and the resistance value ratio of the first resistance R 1 and the second resistance R 2 is 7:3, and other situation is similar.Finally to realize the current potential of first end of described the second resistance R 2 lower than the current potential of the first end (the second current potential arranges the output terminal of circuit) of described the 4th resistance R 4; The current potential of the first end of described the 4th resistance R 4 is lower than described amplitude monotonically increasing signal.
Described the first comparator circuit comprises the first comparer A1; The output terminal (i.e. the first end of the second resistance R 2) that the second input end (i.e. the second input end of the first comparator circuit) and described the first current potential of described the first comparer A1 arranges circuit is connected; The first input end (i.e. the first input end of the first comparator circuit) of described the first comparer A1 is connected with the output terminal (i.e. the first end of the first capacitor C 1) of described waveform changing circuit.
Described the second current potential arranges circuit and comprises the 3rd resistance R 3 and the 4th resistance R 4; The first end of described the 3rd resistance R 3 is connected with power vd D; The second end of described the 3rd resistance R 3 is connected with the first end of described the 4th resistance R 4; The second end ground connection of described the 4th resistance R 4; The first end (the second current potential arranges the output terminal of circuit) of described the 4th resistance R 4 is connected with the second input end of described the second comparator circuit.The setting up procedure of the resistance of the 3rd resistance R 3 and the resistance of the 4th resistance R 4 is identical with the setting up procedure of the second resistance R 2 with the first resistance R 1.
Described the second comparator circuit comprises the second comparer A2; The output terminal (i.e. the first end of the 4th resistance R 4) that the second input end (i.e. the second input end of the second comparator circuit) and described the second current potential of described the second comparer A2 arranges circuit is connected; The first input end (i.e. the first input end of the second comparator circuit) of described the second comparer A2 is connected with the output terminal (i.e. the first end of the first capacitor C 1) of described waveform changing circuit.
The described logic output circuit of the present embodiment comprises the first logical circuit and the second logical circuit;
(1) described the first logical circuit carries out logic xor operation for the output signal to described the first comparator circuit and the output signal of the second comparator circuit;
(2) pulse signal (this example is square-wave signal) that described the second logical circuit obtains for output signal to described the first logical circuit and described signal acquisition circuit (being the signal receiver shown in Fig. 2) carries out logical and operation;
The first input end of described the first logical circuit is connected with the output terminal of described the first comparator circuit; The second input end of described the first logical circuit is connected with the output terminal of described the second comparator circuit; The first input end of described the second logical circuit is connected with the output terminal of described the first logical circuit; The second input end of described the second logical circuit and the output terminal of described signal acquisition circuit are connected.
Can select following actual device to realize the annexation of logic output circuit described above:
Described the first logical circuit comprises XOR gate E1; The output terminal (i.e. the output terminal of the first comparer A1) of the first end of described XOR gate E1 and described the first comparator circuit is connected; The second end of described XOR gate E1 is connected with the output terminal of described the second comparator circuit (i.e. the output terminal of the second comparer A2).
Described the second logical circuit comprises and door E2; Describedly be connected with the door first end of E2 and the output terminal of described the first logical circuit (being the output terminal of XOR gate E1); Describedly be connected with door the second end of E2 and the output terminal of described signal acquisition circuit.Now, the output terminal output of described and door E2 is exactly that the time delay of the pulse signal (being square-wave signal in this example) that obtains of corresponding described signal acquisition circuit (being the signal receiver shown in Fig. 2) starts and shift to an earlier date end signal.
An actual circuit connection diagram of the present embodiment as shown in Figure 2.
By square-wave signal, the wave form varies in the present embodiment circuit illustrates that time delay that the present embodiment obtains corresponding described electric signal starts and shift to an earlier date the process of end signal below.
(1) obtain the pulse signal of described the first equipment, i.e. square-wave signal, represents with W1, as shown in Figure 3.Wherein, ordinate f represents amplitude; Horizontal ordinate t represents the time; Same tag in following figure is identical with Fig. 3, repeats no more;
(2) by waveform changing circuit, square-wave signal is processed, the waveform W2 obtaining, as shown in Figure 4;
(3) waveform W2 is obtained to waveform W3 after rising edge delay circuit is processed, as shown in Figure 5, wherein, f1 represents amplitude corresponding to the time delay t1 zero hour;
(4) waveform W2 is obtained to waveform W4 after negative edge shifts to an earlier date processing of circuit, as shown in Figure 6, wherein, f2 represents amplitude corresponding to the t2 finish time in advance;
(5) waveform W3 and waveform W4 after processing, the first logical circuit are obtained to waveform W5, as shown in Figure 7;
(6) waveform W5 and square-wave signal after processing, the second logical circuit are obtained to waveform W6, as shown in Figure 8.
Embodiment 3
The control signal generative circuit that the present embodiment provides further comprises executive circuit; Described executive circuit is for controlling described the second equipment by the control signal of described the second equipment.
Described executive circuit is on-off element or electric element normally.The described executive circuit of the present embodiment comprises the 6th resistance and triode; The 6th resistance R 6 is for limiting electric current; Triode D1 is for moving according to waveform W6.
The first end of described the 6th resistance R 6 is connected (i.e. the output terminal of described and an E2) and is connected with the output terminal of described the second logical circuit; The second end of described the 6th resistance R 6 is connected with the base stage of described triode D1; The collector of described triode D1 and described the second equipment connection; The grounded emitter of described triode D1.
An actual circuit connection diagram of the present embodiment as shown in Figure 9.Wherein, D2 represents the second equipment; Resistance R 7 is for limiting the electric current of the second equipment D2 that flows through.Correspondence in Fig. 9 in the explanation of other device and embodiment 1 is described identical, repeats no more herein.
The utility model only need to the signal of the sports equipment in human-computer interaction equipment carry out signal process and logic judge just can control the opening and closing of fixed equipment (controlled device).Can be applicable to multiple man-machine interaction device, applied widely; By to delay operation and in advance the secondary signal that obtains of operation carry out simple logical process, just can obtain the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge, process is simple, is not subject to external environmental interference, and result is accurate; Do not use expensive processor, do not need other softwares yet, greatly reduced manufacturing cost and software cost.
The foregoing is only preferred embodiment of the present utility model, be not intended to limit protection domain of the present utility model.All any amendments of doing, be equal to replacement, improvement etc. within spirit of the present utility model and principle, be all included in protection domain of the present utility model.
Claims (10)
1. a control signal generative circuit, for generate the control signal of the second equipment according to the pulse signal of the first equipment, so that the second equipment is also closed in advance with respect to the first equipment delayed start-up; It is characterized in that, this control signal generative circuit comprises: signal acquisition circuit, signal processing circuit and logic output circuit;
Described signal acquisition circuit is for obtaining the pulse signal of described the first equipment;
Described signal processing circuit obtains first signal for the rising edge of described pulse signal is carried out to delay operation; And the negative edge of described pulse signal is operated in advance and obtains secondary signal;
Described logic output circuit is for carrying out logical process to described pulse signal, first signal and secondary signal, obtains the control signal of the second equipment shifting to an earlier date with respect to the time delay of described pulse signal rising edge and negative edge.
2. circuit as claimed in claim 1, is characterized in that, described signal processing circuit comprises that waveform changing circuit, rising edge delay circuit and negative edge shift to an earlier date circuit;
Described rising edge delay circuit comprises that the first current potential arranges circuit and the first comparator circuit;
Described negative edge shifts to an earlier date circuit and comprises that the second current potential arranges circuit and the second comparator circuit;
The output terminal of circuit is set described the first current potential and the second input end of the first comparator circuit is connected;
The output terminal of circuit is set described the second current potential and the second input end of the second comparator circuit is connected;
The input end of described waveform changing circuit is connected with described signal acquisition circuit, and the output terminal of described waveform changing circuit is connected with the first input end of described the first comparator circuit and the first input end of the second comparator circuit respectively.
3. circuit as claimed in claim 2, it is characterized in that, described waveform changing circuit for by described pulse signal from rising edge to negative edge between waveform transformation be amplitude monotonically increasing signal, and by described pulse signal from negative edge to rising edge between waveform transformation be the signal of amplitude monotone decreasing.
4. circuit as claimed in claim 3, is characterized in that, described the first current potential arranges circuit and comprises the first resistance and the second resistance; The first end of described the first resistance is connected with power supply; The second end of described the first resistance is connected with the first end of described the second resistance; The second end ground connection of described the second resistance; The first end of described the second resistance is connected with the second input end of described the first comparator circuit;
Described the second current potential arranges circuit and comprises the 3rd resistance and the 4th resistance; The first end of described the 3rd resistance is connected with power supply; The second end of described the 3rd resistance is connected with the first end of described the 4th resistance; The second end ground connection of described the 4th resistance; The first end of described the 4th resistance is connected with the second input end of described the second comparator circuit;
Described the first comparator circuit comprises the first comparer; The second input end of described the first comparer is connected with the output terminal that described the first current potential arranges circuit; The first input end of described the first comparer is connected with the output terminal of described waveform changing circuit;
Described the second comparator circuit comprises the second comparer; The second input end of described the second comparer is connected with the output terminal that described the second current potential arranges circuit; Described the second comparer first input end is connected with the output terminal of described waveform changing circuit.
5. circuit as claimed in claim 4, is characterized in that, described waveform changing circuit comprises the 5th resistance and the first electric capacity; The first end of described the 5th resistance is connected with described signal acquisition circuit; The second end of described the 5th resistance is connected with the first end of described the first electric capacity; The second end ground connection of described the first electric capacity; The first end of described the first electric capacity is connected with the first input end of described the first comparator circuit and the first input end of the second comparator circuit respectively.
6. the circuit as described in any one in claim 2 to 5, is characterized in that, described logic output circuit comprises the first logical circuit and the second logical circuit;
Described the first logical circuit carries out logic xor operation for the described secondary signal of the described first signal to described the first comparator circuit output and the output of the second comparator circuit;
Described the second logical circuit carries out logical and operation for output signal and described pulse signal to described the first logical circuit;
The first input end of described the first logical circuit is connected with the output terminal of described the first comparator circuit; The second input end of described the first logical circuit is connected with the output terminal of described the second comparator circuit; The first input end of described the second logical circuit is connected with the output terminal of described the first logical circuit; The second input end of described the second logical circuit is connected with described signal acquisition circuit.
7. circuit as claimed in claim 6, is characterized in that, described circuit further comprises: executive circuit, for the control signal by described the second equipment, described the second equipment is controlled.
8. circuit as claimed in claim 7, is characterized in that, described executive circuit comprises the 6th resistance and triode;
The first end of described the 6th resistance is connected with the output terminal of described the second logical circuit; The base stage of described triode is connected with the second end of described the 6th resistance; The collector of described triode and described the second equipment connection; The grounded emitter of described triode.
9. circuit as claimed in claim 4, is characterized in that, the current potential of the first end of described the second resistance is lower than the current potential of the first end of described the 4th resistance; The current potential of the first end of described the 4th resistance is lower than described amplitude monotonically increasing signal.
10. circuit as claimed in claim 1, is characterized in that, described the first equipment is LED lamp, infrared lamp or sensor;
The second equipment is camera, audio collection device, range finder or hygrosensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320828620.5U CN203745823U (en) | 2013-12-13 | 2013-12-13 | Control signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320828620.5U CN203745823U (en) | 2013-12-13 | 2013-12-13 | Control signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203745823U true CN203745823U (en) | 2014-07-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320828620.5U Withdrawn - After Issue CN203745823U (en) | 2013-12-13 | 2013-12-13 | Control signal generating circuit |
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| CN (1) | CN203745823U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744322A (en) * | 2013-12-13 | 2014-04-23 | 青岛歌尔声学科技有限公司 | Control signal generating circuit |
-
2013
- 2013-12-13 CN CN201320828620.5U patent/CN203745823U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103744322A (en) * | 2013-12-13 | 2014-04-23 | 青岛歌尔声学科技有限公司 | Control signal generating circuit |
| CN103744322B (en) * | 2013-12-13 | 2016-08-17 | 青岛歌尔声学科技有限公司 | A kind of control signal generative circuit |
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