CN203691357U - Automatic gain control circuit used for audio frequency processing - Google Patents
Automatic gain control circuit used for audio frequency processing Download PDFInfo
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- CN203691357U CN203691357U CN201420035810.6U CN201420035810U CN203691357U CN 203691357 U CN203691357 U CN 203691357U CN 201420035810 U CN201420035810 U CN 201420035810U CN 203691357 U CN203691357 U CN 203691357U
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Abstract
The utility model relates to an automatic gain control circuit used for audio frequency processing. The automatic gain control circuit is characterized in that the automatic gain control circuit comprises a gain control module, an output driving amplifier, a waveform shaping module, a threshold comparison module, a gain counting module, a time control module and a reference module. By adopting the automatic gain control circuit used for the audio frequency processing, the gain of the circuit is automatically reduced when an output signal exceeds a preset threshold, so that the output signals are enabled to be below the threshold, clipped audio signals caused by over-large output signals are effectively avoided, the sound quality is improved, and the comfort level of hearing is enhanced.
Description
Technical field
The utility model relates to a kind of automatic gain control circuit, especially relates to a kind of automatic gain control circuit for audio frequency processing.
Background technology
Along with developing rapidly of the industries such as microelectric technique, computer networking technology and the communication technology, automatic gain control circuit is more and more known by people and is applied to widely in the middle of every field.Automatic gain control circuit is a kind of in the situation that input signal amplitude alters a great deal, and makes amplitude output signal keep automatic control circuit constant or that only change in more among a small circle.In field of audio processing, input audio signal fluctuation is too large, can cause output to cut top, has so significantly " distorsion " on loud speaker, can bring obvious both poor sound quality acoustically and uncomfortable.The shortcomings such as traditional use analog multiplier is realized the ambipolar circuit of automatic gain control, has manufacturing procedure many, and quiescent dissipation is large, and it is also larger to use CMOS to realize analog multiplier circuit scale.
Utility model content
The applicant, for above-mentioned problem, is studied improvement, and a kind of automatic gain control circuit that is applied to audio frequency processing is provided, and effectively avoids excessive and cause audio signal to cut top by output signal, improves tonequality, improves sense of hearing comfort level.
In order to solve the problems of the technologies described above, the utility model adopts following technical scheme:
For an automatic gain control circuit for audio frequency processing, comprising:
Waveform-shaping module 103, connects the output of described output driver module 102, and output waveform is carried out to halfwave rectifier;
Threshold value comparison module 104, connect described waveform-shaping module 103 outputs, connect external pin VH simultaneously, by the input voltage comparison of described waveform-shaping module 103 output signals and pin VH, in the time that waveform-shaping module 103 output signals are greater than the input voltage of pin VH, threshold value comparison module 104 ride gain counting modules 105 start plus coujnt, in the time that the lasting 50mS of waveform-shaping module 103 output signals is less than the input voltage of pin VH, threshold value comparison module 104 ride gain counting modules 105 start subtraction counting, other situation gain counting module 105 remains unchanged,
Further:
Described gain control module 101 comprises the first resistance R 21, the second resistance R 22, the 3rd resistance R 23 and the 4th resistance R 24; Described output driver module 102 comprises driving amplifier 201, the 5th resistance R 25 and the 6th resistance R 26; The first resistance R 21 connects the audio signal of external pin VIN input, the other end of the first resistance R 21 connects the anode first of the second resistance R 22 and driving amplifier 201 and inputs (+1IN), the other end connecting analog ground of the second resistance R 22, the 3rd resistance R 23 connects the audio signal of external pin VIN input, the other end of the 3rd resistance R 23 connects the anode second of the 4th resistance R 24 and driving amplifier 201 and inputs (+2IN), the other end connecting analog ground of the 4th resistance R 24; The 5th resistance R 25 connects the negative terminal input of driving amplifier 201 and in analog, and the 6th resistance R 26 connects output and the negative terminal input of driving amplifier 201.
In described driving amplifier 201, first constant-current source I1 one end connects power vd D, the other end connects the first switch SW 31, first switch SW 31 other ends connect second switch SW32, connect one end, the drain terminal of a NMOS pipe N1 and the grid end of grid end, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 of capacitor C 31 simultaneously, other one end of second switch SW32 connects the second constant-current source I2, and other one end of the second constant-current source I2 connects ground, and other one end of capacitor C 31 connects ground, the source of the one NMOS pipe N1 connects the 3rd constant-current source I3, and other one end of the 3rd constant-current source I3 connects ground, and the source of the 2nd NMOS pipe N2 connects the 4th constant-current source I4, and other one end of the 4th constant-current source I4 connects ground, the drain terminal of the 2nd NMOS pipe N2 connects drain terminal and the grid end of a PMOS pipe P1, connect the grid end of the 3rd PMOS pipe P3 simultaneously, the source of the one PMOS pipe P1 connects power supply, the drain terminal of the 3rd NMOS pipe N3 connects the 6th constant-current source I6, other one end of the 6th constant-current source I6 connects power supply, the source of the 3rd NMOS pipe N3 connects the source of the 5th constant-current source I5 and the 4th NMOS pipe N4, other one end of the 5th constant-current source I5 connects ground, the drain terminal of the 4th NMOS pipe N4 connects drain terminal and the grid end of the 2nd PMOS pipe P2, connect the grid end of the 4th PMOS pipe P4 simultaneously, the grid end of the 4th NMOS pipe N4 connects grid end and the drain terminal of the 5th NMOS pipe N5, connect the 7th constant-current source I7 simultaneously, other one end of the 7th constant-current source I7 connects power supply, the source of the 2nd PMOS pipe P2 connects power supply, the source of the 5th NMOS pipe N5 connects drain terminal and the grid end of the 6th NMOS pipe N6, the source ground connection of the 6th NMOS pipe N6, the source termination power of the 3rd PMOS pipe P3, the drain terminal of the 3rd PMOS pipe P3 connects the source of the 5th PMOS pipe P5 and the source of the 6th PMOS pipe P6, the drain terminal of the 5th PMOS pipe P5 connects the drain terminal of the 7th PMOS pipe P7, the drain terminal of the 5th PMOS pipe P5 is connected to the second level of amplifier simultaneously, the drain terminal of the 6th PMOS pipe P6 connects the drain terminal of the 8th PMOS pipe P8, the drain terminal of the 6th PMOS pipe P6 is connected to the second level of amplifier simultaneously, the source termination power of the 4th PMOS pipe P4, the drain terminal of the 7th PMOS pipe P7 connects the source of the 7th PMOS pipe P7 and the source of the 6th PMOS pipe P6, the grid end of the 5th PMOS pipe P5 is that driving amplifier 201 anodes second are inputted (+2IN), the grid end of the 7th PMOS pipe P7 is that driving amplifier 201 anodes first are inputted (+1IN), the grid end of the 6th PMOS pipe P6 connects the grid end of the 8th PMOS pipe P8, for driving amplifier 201 negative terminal inputs.
1～No. 8 pin of its packaging body is respectively: power vd D, in analog BYPASS, audio signal input VIN, GND, output VOUT, release time regulating resistance end NCR, Timing capacitance terminal NCC, threshold level VH.
Technique effect of the present utility model is:
The disclosed a kind of automatic gain control circuit for audio frequency processing of the utility model, in the time that output signal exceedes setting threshold, automatically reduce circuit gain, make stable output signal under threshold value, effectively avoid because the excessive audio signal that causes of output signal is cut top, improve tonequality, improve sense of hearing comfort level.
Brief description of the drawings
Fig. 1 is electrical block diagram of the present utility model.
Fig. 2 is gain control module and the circuit diagram of exporting driver module.
Fig. 3 is that driving amplifier input circuit switches schematic diagram.
Fig. 4 is waveform-shaping module and threshold value comparison module schematic diagram.
Fig. 5 is time control module schematic diagram.
Fig. 6 is packaging body pin layout viewing of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
As shown in Figure 1, the utility model comprises gain control module 101, output driving amplifier 102, waveform-shaping module 103, threshold value comparison module 104, gain counting module 105, time control module 106, base modules 107.Benefit control module 101 is provided with signal input part, and input signal is connected to circuit external pin VIN, according to the enumeration data adjustment System gain of gain counting module 105, output driver module 102 connects the output of described gain control module 101, and the output signal of gain control module 101 is amplified and outputed to circuit external pin VOUT, waveform-shaping module 103 connects the output VOUT of output driver module 102, and output waveform is carried out to halfwave rectifier, and the signal after halfwave rectifier, just can be used for and the threshold voltage of pin VH setting compares, threshold value comparison module 104, connect described waveform-shaping module 103 outputs, connect external pin VH simultaneously, by the input voltage comparison of described waveform-shaping module 103 output signals and pin VH, in the time that waveform-shaping module 103 output signals are greater than the input voltage of pin VH, threshold value comparison module 104 ride gain counting modules 105 start plus coujnt, in the time that the lasting 50mS of waveform-shaping module 103 output signals is less than the input voltage of pin VH, threshold value comparison module 104 ride gain counting modules 105 start subtraction counting, other situation gain counting module 105 remains unchanged, gain counting module 105, connect the output of described threshold value comparison module 104, when waveform-shaping module 103 output signals are greater than the input voltage of pin VH, adjust one group of binary counting data of output, and by these group binary counting Data Control gain control module 101 compressor circuit gains, time control module 106 connect threshold comparison modules 104 and gain counting module 105, and be connected to circuit external pin NCC and pin NCR, utilize the charging interval of the external electric capacity of external pin NCC to control the triggered time, utilize the external resistance control release time of external pin NCR, when output waveform exceedes VH threshold voltage, circuit is set out state, built-in constant-current source has determined the attack time to the external capacitor fast charging of NCC pin, when circuit output waveform continues 50mS lower than VH threshold voltage, circuit enters release condition, determine release time by the external resistance of pin NCR to the external capacitor discharge of pin NCC, base modules 107 connects gain control module 101 and output driver module 102 external pin BYPASS, for gain control module 101 and output driver module 102 provide voltage and current biasing.
As shown in Figure 1, 2, gain control module 101 is connected to output driver module 102, has jointly realized and will after the amplification of pin VIN input signal or compression, output to pin VOUT.Gain control module 101 comprises the first resistance R 21, the second resistance R 22, the 3rd resistance R 23 and the 4th resistance R 24; Output driver module 102 comprises driving amplifier 201, the 5th resistance R 25 and the 6th resistance R 26; The first resistance R 21 connects the audio signal of external pin VIN input, the other end of the first resistance R 21 connects the anode first of the second resistance R 22 and driving amplifier 201 and inputs (+1IN), the other end connecting analog ground of the second resistance R 22, the 3rd resistance R 23 connects the audio signal of external pin VIN input, the other end of the 3rd resistance R 23 connects the anode second of the 4th resistance R 24 and driving amplifier 201 and inputs (+2IN), the other end connecting analog ground of the 4th resistance R 24; The 5th resistance R 25 connects the negative terminal input of driving amplifier 201 and in analog, and the 6th resistance R 26 connects output and the negative terminal input of driving amplifier 201.Gain control module 101 is to realize gain by two electric resistance partial pressure loops to control, and the first resistance R 21 and the second resistance R 22 form loop 1, the three resistance R 23 and the 4th resistance R 24 forms loop 2.In output driver module 102, the 5th resistance R 25 connects the negative terminal input of driving amplifier 201 and in analog, and the 6th resistance R 26 connects output and the negative terminal input of exporting driving amplifiers 201, has formed 2 times of amplifications.At pin VOUT output voltage during lower than pin VH threshold voltage, circuit working is at normal mode, the counting module 105 ride gain control module 101 loop 1 dividing potential drop ratios that now gain are 0/ (R21+R22), also control the driving amplifier 201 of output driver module 102 simultaneously and select loop 1 as anode input, now circuit gain is 6dB.In the time that pin VOUT output voltage exceedes the threshold voltage of pin VH, circuit starts compression gains, gain counting module 105 ride gain control module 101 loop 2 voltage ratio R23/ (R23+R24) reduce, also control the driving amplifier 201 of output driver module 102 simultaneously and select loop 2 as anode input, circuit gain declines.If pin VOUT output voltage still exceedes the threshold voltage of pin VH, gain counting module 105 ride gain control module 101 loop 1 voltage ratio R21/ (R21+R22) reduce, control the driving amplifier 201 of output driver module 102 simultaneously and select loop 1 as anode input, circuit gain declines again.If pin VOUT output voltage still exceedes the threshold voltage of pin VH, the loop 2 voltage ratio R23/ (R23+R24) of gain counting module 105 ride gain control modules 101 reduce again, control the driving amplifier 201 of output driver module 102 selects loop 2 to input as anode simultaneously, circuit gain declines, so repeatedly until pin VOUT output voltage, lower than the threshold voltage of pin VH, has so just been realized compression gains.
As shown in Figure 3, in driving amplifier 201, first constant-current source I1 one end connects power vd D, the other end connects the first switch SW 31, the first switch SW 31 connects other end second switch SW32, connects one end, the drain terminal of a NMOS pipe N1 and the grid end of grid end, the 2nd NMOS pipe N2 and the 3rd NMOS pipe N3 of capacitor C 31 simultaneously, and other one end of second switch SW32 connects the second constant-current source I2, other one end of the second constant-current source I2 connects ground, and other one end of capacitor C 31 connects ground, the source of the one NMOS pipe N1 connects the 3rd constant-current source I3, and other one end of the 3rd constant-current source I3 connects ground, and the source of the 2nd NMOS pipe N2 connects the 4th constant-current source I4, and other one end of the 4th constant-current source I4 connects ground, the drain terminal of the 2nd NMOS pipe N2 connects drain terminal and the grid end of a PMOS pipe P1, connect the grid end of the 3rd PMOS pipe P3 simultaneously, the source of the one PMOS pipe P1 connects power supply, the drain terminal of the 3rd NMOS pipe N3 connects the 6th constant-current source I6, other one end of the 6th constant-current source I6 connects power supply, the source of the 3rd NMOS pipe N3 connects the source of the 5th constant-current source I5 and the 4th NMOS pipe N4, other one end of the 5th constant-current source I5 connects ground, the drain terminal of the 4th NMOS pipe N4 connects drain terminal and the grid end of the 2nd PMOS pipe P2, connect the grid end of the 4th PMOS pipe P4 simultaneously, the grid end of the 4th NMOS pipe N4 connects grid end and the drain terminal of the 5th NMOS pipe N5, connect the 7th constant-current source I7 simultaneously, other one end of the 7th constant-current source I7 connects power supply, the source of the 2nd PMOS pipe P2 connects power supply, the source of the 5th NMOS pipe N5 connects drain terminal and the grid end of the 6th NMOS pipe N6, the source ground connection of the 6th NMOS pipe N6, the source termination power of the 3rd PMOS pipe P3, the drain terminal of the 3rd PMOS pipe P3 connects the source of the 5th PMOS pipe P5 and the source of the 6th PMOS pipe P6, the drain terminal of the 5th PMOS pipe P5 connects the drain terminal of the 7th PMOS pipe P7, the drain terminal of the 5th PMOS pipe P5 is connected to the second level of amplifier simultaneously, the drain terminal of the 6th PMOS pipe P6 connects the drain terminal of the 8th PMOS pipe P8, the drain terminal of the 6th PMOS pipe P6 is connected to the second level of amplifier simultaneously, the second level of amplifier is conventional structure, in figure, do not draw, the source termination power of the 4th PMOS pipe P4, the drain terminal of the 7th PMOS pipe P7 connects the source of the 7th PMOS pipe P7 and the source of the 6th PMOS pipe P6, the grid end of the 5th PMOS pipe P5 is that driving amplifier 201 anodes second are inputted (+2IN), the grid end of the 7th PMOS pipe P7 is that driving amplifier 201 anodes first are inputted (+1IN), the grid end of the 6th PMOS pipe P6 connects the grid end of the 8th PMOS pipe P8, for driving amplifier 201 negative terminal inputs.
Control the first switch SW 31 and second switch SW32 opening and closing by gain counting module 105, when the first switch SW 31 is opened, second switch SW32 closes, now the first constant-current source I1 charges to capacitor C 31, voltage VF1 slowly raises, along with VF1>VTHN (NMOS manages unlatching), the 3rd constant-current source I3 starts from 0 increase, mirror-image constant flow source I4=I3 also increases since 0, the one PMOS pipe P1 now starts conducting, by lead-in wire VP2, I4 is mirrored to the grid end of the constant-current source P3 of difference 2, the constant-current source current value of difference 2 also increases since 0.Simultaneously the electric current of the 3rd NMOS pipe N3 also equals I4, and so at I4 during from 0 increase, the electric current of the 4th NMOS pipe N4 starts to take effect from I5, has I here
n3+ I
n4=I5, the 2nd PMOS pipe P2 is by electric current I
n4by lead-in wire VP1, this current mirror is arrived to the grid end of the constant-current source P4 of difference 1.The constant-current source bias electric current of difference 1 starts slowly to reduce like this.Along with NCC pin external capacitor C51 charging voltage raises, difference 2 constant-current source bias electric currents slowly increase since 0, and the constant-current source bias electric current of difference 1 starts slowly to reduce from I5 simultaneously, and the value reducing equals the value that difference 2 constant-current source bias electric currents increase.The effect of the differential levels of driving amplifier 201 is that differential input signal is enlarged into the second level of difference current to amplifier, and the difference current of difference 1 has so:
I
+1-I
-1＝(V
+1-V
-1)×G1
Wherein I+1 is the anode pmos current of difference 1, I
-1for difference 1 negative terminal PMOS electric current, V
+ 1for difference 1 anode input voltage, V
-1for difference 1 negative terminal input voltage, G1 is difference 1 equivalent gain.Can obtain so equally difference 2:
I
+2-I
-2＝(V
+2-V
-2)×G2
The electric current of so whole difference is that difference 1 adds difference 2:
I
+-I
-＝(V
+1-V
-1)×G1+(V
+2-V
-2)×G2
Here in the time that SW31 opens, G1 slowly reduces, and G2 slowly increases, and the anode of so just having realized driving amplifier 201 is switched to the loop 2 of gain control module 101 from the loop 1 of gain control module 101, and there will not be sudden change.Finally, when charging voltage in Fig. 3 exceedes VF2=2VTHN, difference 1 constant-current source bias current reduction is 0, and driving amplifier 201 has been realized amplifying return circuit and has thoroughly been switched to loop 2.
Otherwise, when the first switch SW 31 is closed, second switch SW32 opens by the second constant-current source I2 to capacitor discharge, now along with the lower voltage in the external capacitor C 51 of NCC pin, difference 1 bias current increases, difference 2 bias currents reduce, until external capacitor C 51 voltages of NCC pin are less than VTHN, the anode of having realized driving amplifier 201 is switched to the loop 1 of gain control module 101 from the loop 2 of gain control module 101.
As shown in Figure 4, be waveform-shaping module 103 and threshold value comparison module 104 schematic diagrames.Waveform-shaping module 103 comprises sign-changing amplifier 401, comparator 402 and switch SW 43, the input of sign-changing amplifier 401 connects the signal output voltage of pin VOUT, the output of sign-changing amplifier 401 is connected to switch SW 43, comparator 402 anode inputs connect the signal output voltage of pin VOUT, comparator 402 negative terminal input connecting analog ground, the output of comparator 402 is connected to switch SW 43, other one end of switch SW 43 connects the signal output voltage of pin VOUT, waveform-shaping module 103 by the signal output voltage of pin VOUT by comparator 402 with compare in analog, when exceeding in analog, the signal output voltage waveform of pin VOUT selects the signal output voltage of pin VOUT, the signal output voltage waveform of pin VOUT select lower than in analog time pin VOUT signal output voltage waveform oppositely, so just realize rectification.The comparator of waveform passing threshold comparison module 104 after rectification and the threshold voltage comparison of pin VH, judge whether the signal output voltage of pin VOUT exceedes the threshold voltage of pin VH, and whether carry out decision circuitry needs compression gains.In the time that the signal output voltage of pin VOUT exceedes the threshold voltage of pin VH, the comparator ride gain counting module 105 of threshold value comparison module 104 starts counting, and (counter is 0 under normal mode, represent that system gain is+6dB), once, in Fig. 3, two input circuit dividing potential drop ratios reduce the anode input circuit that simultaneously switches the driving amplifier 201 of exporting driver module 102 to the every plus coujnt of gain counting module 105.
As shown in Figure 5, for the schematic diagram of time control module 106, constant-current source I53 is connected to switch SW 51, the other end of switch SW 51 is connected to switch SW 52, be connected to the external capacitor C 51 of electrical level judging module 502 and pin NCC simultaneously, the other end of switch SW 52 is connected to the external resistance R 52 of pin NCR, threshold value comparison module 104 is connected to switch SW 51 and delay counter 501, delay counter 501 is also connected to switch SW 52 simultaneously, and electrical level judging module 502 is connected to gain counting module 105 simultaneously.In the time that threshold value comparison module 104 detects that the signal output voltage of pin VOUT is greater than the threshold voltage of pin VH, switch SW 51 is opened, constant-current source I51 is to the external capacitor charging of pin NCC, because constant-current source is very large, can quickly charge to high level, the signal that electrical level judging module 502 outputs to gain counting module 105 is high level, and gain counting module 105 starts plus coujnt, and circuit starts compressor circuit gain.In the time that threshold value comparison module 104 detects that the signal output voltage of pin VOUT is less than the threshold voltage of pin VH, first switch SW 51 is closed, in delay counter 501 delay times, the signal output voltage of pin VOUT continues the threshold voltage lower than pin VH, then opening switch SW 52, outer meeting resistance by pin NCR discharges to the external capacitor of pin NCC, in the time discharging into low level, circuit enters release mode and reduces compression gains.
As shown in Figure 6, in the present embodiment, be respectively for 1～No. 8 pin of the packaging body of the automatic gain control circuit of audio frequency processing: power vd D, in analog BYPASS, audio signal input VIN, GND, output VOUT, release time regulating resistance end NCR, Timing capacitance terminal NCC, threshold level VH.
Claims (4)
1. for an automatic gain control circuit for audio frequency processing, it is characterized in that comprising:
Gain control module (101), is provided with signal input part, according to the enumeration data adjustment System gain of gain counting module (105);
Export driver module (102), connect the output of described gain control module (101), the output signal of gain control module (101) is amplified to output;
Waveform-shaping module (103), connects the output of described output driver module (102), and output waveform is carried out to halfwave rectifier;
Threshold value comparison module (104), connect described waveform-shaping module (103) output, connect external pin (VH) simultaneously, by the input voltage comparison of described waveform-shaping module (103) output signal and pin (VH), in the time that waveform-shaping module (103) output signal is greater than the input voltage of pin (VH), threshold value comparison module (104) ride gain counting module (105) starts plus coujnt, in the time that the lasting 50mS of waveform-shaping module (103) output signal is less than the input voltage of pin (VH), threshold value comparison module (104) ride gain counting module (105) starts subtraction counting, other situation gain counting module (105) remains unchanged,
Gain counting module (105), connect the output of described threshold value comparison module (104), when waveform-shaping module (103) output signal is greater than the input voltage of pin (VH), adjust one group of binary counting data of output, and by this group binary counting Data Control gain control module (101) compressor circuit gain;
Time control module (106), connect described threshold value comparison module (104) and gain counting module (105), and be connected to circuit external pin (NCC) and pin (NCR), utilize the charging interval of the external electric capacity of external pin (NCC) to control the triggered time, utilize the external resistance control release time of external pin (NCR);
Base modules (107), connect described gain control module (101) and output driver module (102), for described gain control module (101) and output driver module (102) provide voltage and current biasing.
2. according to the automatic gain control circuit for audio frequency processing claimed in claim 1, it is characterized in that: described gain control module (101) comprises the first resistance (R21), the second resistance (R22), the 3rd resistance (R23) and the 4th resistance (R24), described output driver module (102) comprises driving amplifier (201), the 5th resistance (R25) and the 6th resistance (R26), the first resistance (R21) connects the audio signal of external pin VIN input, the other end of the first resistance (R21) connects the anode first of the second resistance (R22) and driving amplifier (201) and inputs (+1IN), the other end connecting analog ground of the second resistance (R22), the 3rd resistance (R23) connects the audio signal of external pin VIN input, the other end of the 3rd resistance (R23) connects the anode second of the 4th resistance (R24) and driving amplifier (201) and inputs (+2IN), the other end connecting analog ground of the 4th resistance (R24), the 5th resistance (R25) connects the negative terminal input and in analog of driving amplifier (201), output and the negative terminal input of the 6th resistance (R26) connection driving amplifier (201).
3. according to the automatic gain control circuit for audio frequency processing claimed in claim 2, it is characterized in that: in described driving amplifier (201), the first constant-current source (I1) one end connects power supply (VDD), the other end connects the first switch (SW31), the first switch (SW31) other end connects second switch (SW32), connect one end of electric capacity (C31) simultaneously, drain terminal and the grid end of the one NMOS pipe (N1), the grid end of the 2nd NMOS pipe (N2) and the 3rd NMOS pipe (N3), other one end of second switch (SW32) connects the second constant-current source (I2), other one end of the second constant-current source (I2) connects ground, other one end of electric capacity (C31) connects ground, the source of the one NMOS pipe (N1) connects the 3rd constant-current source (I3), other one end of the 3rd constant-current source (I3) connects ground, the source of the 2nd NMOS pipe (N2) connects the 4th constant-current source (I4), and other one end of the 4th constant-current source (I4) connects ground, the drain terminal of the 2nd NMOS pipe (N2) connects drain terminal and the grid end of a PMOS pipe (P1), connect the grid end of the 3rd PMOS pipe (P3) simultaneously, the source of the one PMOS pipe (P1) connects power supply, the drain terminal of the 3rd NMOS pipe (N3) connects the 6th constant-current source (I6), other one end of the 6th constant-current source (I6) connects power supply, the source of the 3rd NMOS pipe (N3) connects the source of the 5th constant-current source (I5) and the 4th NMOS pipe (N4), other one end of the 5th constant-current source (I5) connects ground, the drain terminal of the 4th NMOS pipe (N4) connects drain terminal and the grid end of the 2nd PMOS pipe (P2), connect the grid end of the 4th PMOS pipe (P4) simultaneously, the grid end of the 4th NMOS pipe (N4) connects grid end and the drain terminal of the 5th NMOS pipe (N5), connect the 7th constant-current source (I7) simultaneously, other one end of the 7th constant-current source (I7) connects power supply, the source of the 2nd PMOS pipe (P2) connects power supply, the source of the 5th NMOS pipe (N5) connects drain terminal and the grid end of the 6th NMOS pipe (N6), the source ground connection of the 6th NMOS pipe (N6), the source termination power of the 3rd PMOS pipe (P3), the drain terminal of the 3rd PMOS pipe (P3) connects the source of the 5th PMOS pipe (P5) and the source of the 6th PMOS pipe (P6), the drain terminal of the 5th PMOS pipe (P5) connects the drain terminal of the 7th PMOS pipe (P7), the drain terminal of the 5th PMOS pipe (P5) is connected to the second level of amplifier simultaneously, the drain terminal of the 6th PMOS pipe (P6) connects the drain terminal of the 8th PMOS pipe (P8), the drain terminal of the 6th PMOS pipe (P6) is connected to the second level of amplifier simultaneously, the source termination power of the 4th PMOS pipe (P4), the drain terminal of the 7th PMOS pipe (P7) connects the source of the 7th PMOS pipe (P7) and the source of the 6th PMOS pipe (P6), the grid end of the 5th PMOS pipe (P5) is that driving amplifier (201) anode second is inputted (+2IN), the grid end of the 7th PMOS pipe (P7) is that driving amplifier (201) anode first is inputted (+1IN), the grid end of the 6th PMOS pipe (P6) connects the grid end of the 8th PMOS pipe (P8), for the input of driving amplifier (201) negative terminal.
4. according to the automatic gain control circuit for audio frequency processing claimed in claim 1, it is characterized in that: 1～No. 8 pin of its packaging body is respectively: power supply (VDD), (BYPASS), audio signal input (VIN) in analog, (GND), output (VOUT), regulating resistance end release time (NCR), Timing capacitance terminal (NCC), threshold level (VH).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420035810.6U CN203691357U (en) | 2014-01-20 | 2014-01-20 | Automatic gain control circuit used for audio frequency processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420035810.6U CN203691357U (en) | 2014-01-20 | 2014-01-20 | Automatic gain control circuit used for audio frequency processing |
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| Publication Number | Publication Date |
|---|---|
| CN203691357U true CN203691357U (en) | 2014-07-02 |
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| CN201420035810.6U Expired - Fee Related CN203691357U (en) | 2014-01-20 | 2014-01-20 | Automatic gain control circuit used for audio frequency processing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395149A (en) * | 2017-07-28 | 2017-11-24 | 矽力杰半导体技术(杭州)有限公司 | Acoustic signal processing method, device and integrated circuit |
-
2014
- 2014-01-20 CN CN201420035810.6U patent/CN203691357U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395149A (en) * | 2017-07-28 | 2017-11-24 | 矽力杰半导体技术(杭州)有限公司 | Acoustic signal processing method, device and integrated circuit |
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