CN204031076U - A kind of circuit of continuous adjusting D class power amplifier power - Google Patents
A kind of circuit of continuous adjusting D class power amplifier power Download PDFInfo
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- CN204031076U CN204031076U CN201420188190.XU CN201420188190U CN204031076U CN 204031076 U CN204031076 U CN 204031076U CN 201420188190 U CN201420188190 U CN 201420188190U CN 204031076 U CN204031076 U CN 204031076U
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Abstract
The utility model relates to electronic technology field, discloses a kind of circuit of continuous adjusting D class power amplifier power, and this circuit comprises: amplitude limiter circuit and D class power amplification circuit, and D class power amplification circuit comprises integrator electronic circuit; Amplitude limiter circuit is attempted by between these integrator electronic circuit input and output; Input using the output of this integrator electronic circuit as this amplitude limiter circuit, amplitude limiter circuit comprises trsanscondutance amplifier electronic circuit, current mirror electronic circuit and limiter transistor, the difference of the voltage of input saturation circuit and default deboost is converted to current value by trsanscondutance amplifier electronic circuit, and the input of integrator electronic circuit is shunted; Current mirror electronic circuit provides bias current for trsanscondutance amplifier electronic circuit, and limiter transistor is carried out level shift to default deboost.This circuit intelligent, can be less at the audio signal voltage of input, while not needing power restriction, closes each transistorized electric current in amplitude limiter circuit, reduces power consumption, simplifies circuit structure.
Description
Technical field
The utility model relates to electronic technology field, particularly a kind of circuit of continuous adjusting D class power amplifier power.
Background technology
Along with the raising that people require sound technique, a series of high-power audio power amplifiers also produce in succession.Power amplifier is called for short power amplifier, and people, in the time using power amplifier, also pay special attention to the fail safe of power amplifier, and one of them requirement is exactly to avoid under emergency situations, the loud speaker in power amplifier being burnt.
As shown in Figure 1, it is design power limiting circuit in power amplifier that prior art is avoided the scheme of under emergency situations, the loud speaker in D class power amplifier being burnt, and this power limit circuit is by regulating the mode of input voltage to reach the object of Power Limitation.This power limit circuit comprises amplitude limiter circuit and D class power amplification circuit, and amplitude limiter circuit is positioned at the front end of whole power limit circuit, and D class power amplification circuit is positioned at the rear end of whole power limit circuit, and amplitude limiter circuit is connected with D class power amplification circuit.In use, in prime amplifier, adopt pressure limiting circuit, pressure limiting circuit is the amplitude limiter circuit shown in Fig. 1, in the time that the amplitude of input signal exceedes the pre-set limit voltage of pressure limiting circuit, prime output signal peak value produces slicing, this waveform, after the power amplifier in D class power amplification circuit, produces a confined amplifying signal of voltage amplitude, those skilled in the art will appreciate that power amplifier output voltage is limited in
between.
For prime signal voltage amplitude is limited; need to all be restricted ceiling voltage and minimum voltage; wherein; MN1 and MN2 are low level clamper tube; MP1 and MP2 are high level clamper tube; OP1 is the amplifier of restriction low-voltage; the concrete circuit structure of OP1 as shown in Figure 2; OP2 is the high-tension amplifier of restriction; the concrete circuit structure of OP2 as shown in Figure 3; when input signal amplitude is during lower than VDD/2-Vs, OP1 exports high level, by clamper tube MN1(or MN2) input signal is limited in to VDD/2-Vs; When input signal amplitude is during higher than VDD/2+Vs, OP2 output low level, by clamper tube MP1(or MP2) input signal is limited in to VDD/2+Vs; In the time that input signal amplitude is between VDD/2-Vs and VDD/2+Vs, OP1 output low level, OP2 output low level, MP1, MP2, MN1, MN2 are all in off state.In OP1, P1, P2 and P7 are mirror current source, and P3～P6, N1～N4 form Foldable cascade amplifier, and VB1, VB2 are bias supply, and P8 is level shift pipe, offset MN1(or MN2) threshold voltage.In OP2, N5, N6 and N11 are mirror current source, and N7～N10, P9～P12 form Foldable cascade amplifier, and VB3, VB4 are bias supply, and N12 is level shift pipe, offset MP1(or MP2) threshold voltage.
In sum, what adopt due to power limit circuit of the prior art is that prime signal voltage amplitude is limited, and therefore needs ceiling voltage and minimum voltage to be all restricted, and circuit is realized complicated.When the audio signal voltage of input is less, while not needing power restriction, amplitude limiter circuit still needs work, needs consumed power, and therefore, power limit circuit of the prior art is not intelligent.
Utility model content
The purpose of this utility model is to provide a kind of circuit of continuous adjusting D class power amplifier power, this circuit intelligent, can be less in the audio signal voltage amplitude of input, while not needing power restriction, automatically close each transistorized electric current in this amplitude limiter circuit, reduce the power consumption of amplitude limiter circuit, simplified circuit structure.
For solving the problems of the technologies described above, execution mode of the present utility model provides a kind of circuit of continuous adjusting D class power amplifier power, comprises amplitude limiter circuit and D class power amplification circuit, comprising:
Described D class power amplification circuit comprises integrator electronic circuit; Described amplitude limiter circuit is attempted by between the input and output of described integrator electronic circuit; Input using the output of described integrator electronic circuit as described amplitude limiter circuit;
Described amplitude limiter circuit comprises trsanscondutance amplifier electronic circuit, current mirror electronic circuit and limiter transistor, the input voltage of described amplitude limiter circuit and the difference of described default deboost are converted to current value by described trsanscondutance amplifier electronic circuit, and the input of described integrator electronic circuit is shunted; Described current mirror electronic circuit provides bias current for described trsanscondutance amplifier electronic circuit, and described limiter transistor is carried out level shift to described default deboost.
The utility model execution mode in terms of existing technologies, the circuit intelligent of the continuous adjusting D class power amplifier power providing, amplitude limiter circuit is placed in the inside of D class power amplifier, be attempted by between the input and output of integrator electronic circuit by this amplitude limiter circuit, input using the output of integrator electronic circuit as described amplitude limiter circuit, when specific works, if the output voltage amplitude of integrator electronic circuit is equal to or greater than default deboost, transistor turns in amplitude limiter circuit, starts amplitude limiter circuit; If the output voltage amplitude of integrator electronic circuit is less than default deboost, the transistor in amplitude limiter circuit turn-offs, and disconnects amplitude limiter circuit; Therefore, this circuit can be less at the audio signal voltage of input, while not needing power restriction, automatically shuts down each transistorized electric current in this amplitude limiter circuit, thereby reduced the power consumption of amplitude limiter circuit.
Preferably, described trsanscondutance amplifier electronic circuit comprises p channel transistor P1～P8 and N channel transistor N1～N6; Described current mirror electronic circuit comprises p channel transistor P9, P10 and N channel transistor N7～N9; Described limiter transistor is N10;
Wherein, the source electrode of described P1, described P2, described P3, described P4, described P5, described P6, described P7, described P8, described P9 and described P10 all connects supply voltage VDD; The grid of the grid of the grid of described P1, the drain electrode of described P5, described P6 and drain electrode, described P7 is all connected with the drain electrode of described N4; The grid of described N1, the grid of described N2 and drain electrode are all connected with the drain electrode of described P2; The grid of described P2, the grid of described P3 and drain electrode, the drain electrode of described P4 and the grid of described P8 are all connected with the drain electrode of described N3; The grid of described P4, described P5, described P9, the grid of described P10 and drain electrode are all connected with the drain electrode of described N8; The grid of the grid of described N5 and drain electrode, described N6 is all connected with the drain electrode of described P7; The grid of described N3 and described N4, the drain electrode of described N10 and grid are all connected with the drain electrode of described P9; After linking together, the grid of described N7, described N8 and described N9 is connected with current source;
The source grounding of described N1, described N2, described N5, described N6, described N7, described N8 and described N9; The source electrode of described N3 and described N4 is respectively as first input end and second input of described amplitude limiter circuit; The drain electrode of described P8 and described N6 links together as the first output of described amplitude limiter circuit; The drain electrode of described P1 and the drain electrode of described N1 link together as the second output of described amplitude limiter circuit; The drain electrode of described N7 is all connected deboost Vs with the source electrode of described N10.
Input using the output of integrator electronic circuit as amplitude limiter circuit, namely the voltage of integrator electronic circuit output is input to the source electrode of N3 or the source electrode of N4, in the time that the output voltage amplitude of integrator electronic circuit is less than default deboost, voltage amplitude cannot reach N3 and the desired amplitude of N4 conducting, therefore, N3 and N4 are all in off state, now, N3 and N4 inside do not have electric current to pass through, so, because other electronic devices in whole amplitude limiter circuit are all serially connected with N3 or N4, so, in other electronic devices in whole amplitude limiter circuit, do not have electric current to pass through yet, therefore, can be understood as whole amplitude limiter circuit is off-state, be do not have in harness, trsanscondutance amplifier output current is 0, amplitude limiter circuit can not have influence on the normal output of power amplifier, in the time that the output voltage amplitude of integrator electronic circuit is equal to or greater than default deboost, voltage amplitude has reached N3 or the desired amplitude of N4 conducting, therefore, N3 or N4 can conductings in turn in every half period of audio signal, now, N3 and N4 inside have electric current to pass through in turn, so, because other electronic devices in whole amplitude limiter circuit are all serially connected with N3 or N4, so, in other electronic devices in whole amplitude limiter circuit, the transistor that forms current mirror with N3 or N4 also has electric current to pass through in turn, therefore, it is in running order can be understood as whole amplitude limiter circuit.Draw electric current to shunt integrator electronic circuit by the output after trsanscondutance amplifier, the amplitude of integrator electronic circuit output voltage is restricted, pass through again PWM modulation circuit, rear class gate driver and the switching power tube of D class power amplification circuit rear end, after low-pass filtering, the restricted voltage signal of output amplitude, plays the effect of Power Limitation.When a little less than input signal, the amplitude limiter circuit in the utility model does not participate in work, consumes hardly unnecessary power.The utility model has been realized the object that continuous power regulates simultaneously, has obtained better auditory effect, can improve client's perception.
Brief description of the drawings
Fig. 1 is the power limit circuit figure of D class power amplifier in prior art;
Fig. 2 is the particular circuit configurations figure of OP1 in D class power amplifier in prior art;
Fig. 3 is the particular circuit configurations figure of OP2 in D class power amplifier in prior art;
Fig. 4 is the circuit theory schematic diagram of the continuous adjusting D class power amplifier power in the utility model the first execution mode;
Fig. 5 is the circuit diagram of the continuous adjusting D class power amplifier power in the utility model the first execution mode;
Fig. 6 is the circuit diagram that regulates continuously amplitude limiter circuit in the circuit of D class power amplifier power in the utility model the first execution mode;
Fig. 7 is the oscillogram that regulates continuously a kind of input signal of amplitude limiter circuit in the circuit of D class power amplifier power in the utility model the first execution mode;
Fig. 8 is the oscillogram that regulates continuously a kind of input signal of amplitude limiter circuit in the circuit of D class power amplifier power in the utility model the first execution mode.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, each execution mode of the present utility model is explained in detail.But, persons of ordinary skill in the art may appreciate that in the each execution mode of the utility model, in order to make reader understand the application better, many ins and outs are proposed.But, even without these ins and outs and the many variations based on following execution mode and amendment, also can realize the each claim of the application technical scheme required for protection.
The utility model the first execution mode provides a kind of circuit of continuous adjusting D class power amplifier power, and as shown in Figure 4, this regulates the circuit of D class power amplifier power to comprise amplitude limiter circuit and D class power amplification circuit continuously.Integrator electronic circuit and regulate electronic circuit composition D class power amplification circuit, wherein, regulates electronic circuit to comprise PWM(Pulse Width Modulation, pulse width modulation) modulation circuit, gate driver (Gate Driver) and switching power tube; Integrator electronic circuit is for input signal and output error are carried out to integral operation, and comparator and triangular-wave generator composition PWM modulation circuit, for integrator electronic circuit output signal and triangle wave voltage are compared, produce pwm signal; Gate driver is for driving switch power tube.Amplitude limiter circuit is attempted by between integrator electronic circuit and input and output, for limiting the output voltage amplitude of integrator electronic circuit.
As shown in Figure 5, amplitude limiter circuit is the part in dotted line frame in Fig. 5, and in Fig. 5, except the part composition D class power amplification circuit of amplitude limiter circuit, this D class power amplification circuit is same as the prior art.
Concrete, as shown in Figure 5, this D class power amplification circuit comprises integrator electronic circuit and regulates electronic circuit; Regulate electronic circuit to comprise PWM modulation circuit, gate driver and switching power tube M1～M4, integrator electronic circuit comprises: capacitor C 1～C6, resistance R 11, R12, R13, R21, R22 and R23, integrator A1 and A2; This integrator electronic circuit is second-order integrator, forms closed feedback loop with amplitude limiter circuit.PWM modulation circuit comprises triangular-wave generator, comparator B1 and B2.
Wherein, the first end of R11 and R21 connects respectively forward input voltage and reverse input voltage; Forward input voltage can be positive voltage, can represent with (IN+), and oppositely input voltage can be negative voltage, can represent with (IN-).C1, C2 and C3 order are connected, and C4, C5 and C6 order are connected, and the second end of R11 is connected with positive pole, the in-phase input end of A1 and the first end of R12 of C1 simultaneously, and the positive pole of C1 is connected with the first output of amplitude limiter circuit; The second end of R21 is connected with positive pole, the inverting input of A1 and the first end of R22 of C4 simultaneously, and the positive pole of C4 is connected with the second output of amplitude limiter circuit; The reversed-phase output of A1 is connected with negative pole, the first end of R13 and the positive pole of C2 of C1 simultaneously, the in-phase output end of A1 is connected with negative pole, the first end of R23 and the positive pole of C5 of C4 simultaneously, the second end of R13 is connected with negative pole, the in-phase input end of A2 and the positive pole of C3 of C2 simultaneously, and the second end of R23 is connected with negative pole, the inverting input of A2 and the positive pole of C6 of C5 simultaneously; The negative pole of C3, the reversed-phase output of A2 are connected with the in-phase input end of B1 and the first input end of amplitude limiter circuit simultaneously; The negative pole of C6, the in-phase output end of A2 are connected with the in-phase input end of B2 and the second input of amplitude limiter circuit simultaneously; The inverting input of B1 is all connected with triangular-wave generator TRIP with the inverting input of B2; The output of B1 and B2 uses as the input of gate driver, the output of the equal connection door driver of grid of M1 and M2; The output of the equal connection door driver of grid of M3 and M4; The reversed-phase output of M1 and the drain electrode of M2 and the second end phase downlink connection D class power amplification circuit of R12, the reversed-phase output of this D class power amplification circuit can be used
represent, the in-phase output end of M3 and the drain electrode of M4 and the second end phase downlink connection D class power amplification circuit of R22, the in-phase output end of this D class power amplification circuit can be used
represent; The source electrode of M1 and M4 is connected supply voltage power power-supply PVDD; The source grounding of M2 and M3.Wherein, M1 and M4 are p channel transistor, and M2 and M3 are N channel transistor.
As shown in Figure 6, amplitude limiter circuit comprises trsanscondutance amplifier electronic circuit, current mirror electronic circuit and limiter transistor, and trsanscondutance amplifier electronic circuit and current mirror electronic circuit are connected in parallel, and limiter transistor is serially connected in current mirror electronic circuit.Trsanscondutance amplifier electronic circuit comprises p channel transistor P1～P8 and N channel transistor N1～N6; Current mirror electronic circuit comprises p channel transistor P9, P10 and N channel transistor N7～N9; Current mirror electronic circuit can provide bias current for trsanscondutance amplifier electronic circuit, and limiter transistor is N10; N3, N4 and N10 mirror image, form source follower.Wherein, the source electrode of P1, P2, P3, P4, P5, P6, P7, P8, P9 and P10 all connects supply voltage VDD; After linking together, the grid of N7, N8 and N9 is connected with current source; The grid of P1, the drain electrode of P6 are connected with the drain electrode of N4; The grid of N1, the grid of N2 and drain electrode are all connected with the drain electrode of P2; The grid of P2 and P3 is all connected with the drain electrode of P4; The drain electrode of P3 and the grid of P8 are all connected with the drain electrode of N3; The grid of P4, P5, P9, the grid of P10 and drain electrode are all connected with the drain electrode of N8; The grid of P6 and P7 is connected with the drain electrode of P5; The grid of the grid of N5 and drain electrode, N6 is all connected with the drain electrode of P7; The grid of N3 and N4, the drain electrode of N10 and grid are all connected with the drain electrode of P9; The source grounding of N1, N2, N5, N6, N7, N8 and N9; The source electrode of N3 and N4 is respectively as first input end and second input of amplitude limiter circuit, and first input end and the second input can represent with V1 and V2 respectively; The drain electrode of P8 and N6 links together as the first output of amplitude limiter circuit, and the first output can represent with V01; The drain electrode of P1 and the drain electrode of N1 link together as the second output of amplitude limiter circuit, and the first output can represent with V02; The grid of N7 and N8 is all connected with the grid of N9; The drain electrode of N7 is all connected deboost Vs with the source electrode of N10.The mirror image ratio of the mirror image ratio of the electric current by N1 and N2 and the electric current by N5 and N6 is K:1, and K is not equal to 0 number.The mirror image ratio of the mirror image ratio of the electric current by P2 and P3 and the electric current by P6 and P7 is 1:1.The open-loop gain of the feedback loop that can form by the size adjustment amplitude limiter circuit of adjusting K value like this.
When specific works, first input end using the first end of R11 as integrator electronic circuit, the second input using the input of R21 as integrator electronic circuit, the input signal of the first input end of integrator electronic circuit is through the in-phase input end of R11 input A1, signal one tunnel of the reversed-phase output output of A1 is through the in-phase input end of R13 input A2, another road feeds back to the in-phase input end of A1 through C1, signal one tunnel of the inverting input output of A2 enters the first input end of amplitude limiter circuit, and another road feeds back to the in-phase input end of A2 through C3; In like manner,
The input signal of the second input of integrator electronic circuit is through the inverting input of R21 input A1, signal one tunnel of the in-phase output end output of A1 is through the inverting input of R23 input A2, another road feeds back to the inverting input of A1 through C4, signal one tunnel of the in-phase input end output of A2 enters the second input of amplitude limiter circuit, and another road feeds back to the inverting input of A2 through C6.
In the time amplitude limiter circuit being connected to integrator electronic circuit and gate driver electronic circuit, concrete method of attachment is: the first input end of amplitude limiter circuit is connected with the negative pole of C3 and the reversed-phase output of A2 simultaneously, wherein, the first input end of amplitude limiter circuit can be the source electrode of N3; The second input of amplitude limiter circuit is connected with the negative pole of C6 and the in-phase output end of A2, and the second input of amplitude limiter circuit can be the source electrode of N4; The first output of amplitude limiter circuit is connected with the positive pole of C1; The second output of amplitude limiter circuit is connected with the positive pole of C4.
The circuit below contrasting in Fig. 5 and Fig. 6 regulates the course of work of the circuit of D class power amplifier power simply to describe to this continuously.Because the differential output signal of integrator A2 is the signal of full symmetric, therefore amplitude limiter circuit only need to be to first cycle of signal or second cycle limit, and control mode is more succinct.Taking the lower half time limit width to signal as example, in the time that the output voltage amplitude of integrator A2 is in deboost, the output voltage of A2, as the input of transistor N3 or N4, cannot reach N3 or the desired magnitude of voltage of N4 conducting, therefore, N3 or N4 are in off state, accordingly, other transistors in amplitude limiter circuit, also in off state, that is to say, amplitude limiter circuit, in off-state, regulates the circuit of D class power amplifier power to export distortionless amplifying signal continuously; In the time that the output voltage amplitude of integrator electronic circuit is more than or equal to default deboost, the output voltage of A2 is as the input of transistor N3 or N4, can meet N3 or the desired magnitude of voltage of N4 conducting, therefore, N3 or N4 are in conducting state, accordingly, other transistors in amplitude limiter circuit also can be switched on, and that is to say, amplitude limiter circuit is activated, under the degenerative effect of loop, the output voltage of integrator electronic circuit is limited in setting voltage.
If the triangular wave peak value of the PWM modulating circuit modulates signal TRIP of D class power amplifier is V
t, the supply voltage of power power-supply PVDD is V
p, the voltage gain of the circuit output end of the power power from integrator output terminal to continuous adjusting D class power amplifier is A=V
p/ V
t, when the default deboost of amplitude limiter circuit is V
stime, the output ceiling voltage amplitude that those skilled in the art can extrapolate power amplifier is (VDD/2-V
s) × V
p/ V
t, corresponding input audio signal amplitude is
the voltage amplitude that this input audio signal amplitude is input audio signal, in the time that input audio signal is less than this amplitude, amplitude limiter circuit is not worked, and in the time that input audio signal is more than or equal to this amplitude, amplitude limiter circuit will start.Rationally regulate V
svalue, just can control output voltage amplitude (VDD/2-V
s) × V
p/ V
tvalue, so also just power amplifier can be limited in different power outputs.In addition V,
svalue can carry out continuous setup, that is to say can be by regulating continuously V
smagnitude of voltage, the power of the circuit to this D class power amplifier power can regulate continuously.
In the structure of the amplitude limiter circuit shown in Fig. 6, P1～P8 and N1～N6 forms trsanscondutance amplifier, P9～P10 and N7～N9 forms current mirror, for trsanscondutance amplifier provides bias current, Vs termination is set deboost, N3, N4 and N10 mirror image, form source follower, those skilled in the art will appreciate that under the effect of feedback loop, the source voltage of V1 and V2 is limited in Vs+VgsN10-VgsN3 ≈ Vs.Wherein, VgsN10 represents the maximum of added voltage between the source electrode of N10 and grid, and VgsN3 represents the maximum of added voltage between the source electrode of N10 and grid.Because V1 and V2 signal are integrator differential output signal, therefore, work as V
swhen <VDD/2, the only conducting in turn within every half audio signal cycle of N3 pipe and N4 pipe, the existing course of work of analyzing in two kinds of situation this trsanscondutance amplifier electronic circuit:
1, suppose that default deboost is V
s, in the time that the input voltage amplitude of input trsanscondutance amplifier electronic circuit is less than default deboost, the magnitude of voltage of V1 is greater than V
stime, (be V1>V
sor V2>V
s), the voltage magnitude of V1 is less than V
s, as shown in Figure 7, corresponding input audio signal amplitude is less than
inside does not have electric current to pass through, and therefore, P1～P8, N1～N6 pipe does not all have electric current to pass through, and trsanscondutance amplifier output current is 0, and amplitude limiter circuit can not have influence on the normal output of power amplifier.
2, (V1<V in the time that the input voltage amplitude of input trsanscondutance amplifier electronic circuit is greater than default deboost
sor V2<V
s), as shown in Figure 8, corresponding input audio signal amplitude is greater than
now N3 pipe or the conducting in turn within every half audio signal cycle of N4 pipe, example, N3 is in first cycle conducting, and N4 is in second cycle conducting.It is I that those skilled in the art can extrapolate the electric current passing through in N3 pipe (or N4 pipe)
n3, N4=gm
n3, N4× (V
s-V
1), wherein, gm
n3, N4represent the mutual conductance of N3 pipe (or N4 pipe), therefore, P1～P8, N1～N3 or P5～P8, N4～N6 pipe have electric current to pass through in turn, by VO2(after trsanscondutance amplifier or VO1) output current be I
o2=gm
n3, N4× (V
s-V
1) × K(K is current mirror ratio), this electric current is shunted integrator, make the amplitude limitation of integrator electronic circuit output voltage more than Vs, pass through again PWM modulation circuit, rear class gate driver and switching power tube M1～M4, after low-pass filtering, the restricted voltage signal of output amplitude, plays the effect of Power Limitation.
The utility model execution mode in terms of existing technologies, the circuit intelligent of the continuous adjusting D class power amplifier power providing, amplitude limiter circuit is attempted by between the input and output of integrator electronic circuit, input using the output of integrator electronic circuit as amplitude limiter circuit, namely the voltage of integrator electronic circuit output is input to the source electrode of N3 or the source electrode of N4, in the time that the output voltage amplitude of integrator electronic circuit is less than default deboost, voltage amplitude cannot reach N3 and the desired amplitude of N4 conducting, therefore, N3 and N4 are all in off state, now, N3 and N4 inside do not have electric current to pass through, so, because other electronic devices in whole amplitude limiter circuit are all serially connected with N3 or N4, so, in other electronic devices in whole amplitude limiter circuit, do not have electric current to pass through yet, therefore, can be understood as whole amplitude limiter circuit is off-state, be do not have in harness, trsanscondutance amplifier output current is 0, amplitude limiter circuit can not have influence on the normal output of power amplifier, in the time that the output voltage amplitude of integrator electronic circuit is equal to or greater than default deboost, voltage amplitude has reached N3 or the desired amplitude of N4 conducting, therefore, N3 or N4 can conductings in turn in every half period of input audio signal, now, N3 or N4 inside have electric current to pass through in turn, so, because other electronic devices in whole amplitude limiter circuit are all serially connected with N3 or N4, so, in other electronic devices in whole amplitude limiter circuit, form in the transistor of current mirror and also have in turn electric current to pass through with N3 or N4, therefore, it is in running order can be understood as whole amplitude limiter circuit.Draw electric current to shunt integrator electronic circuit by the output after trsanscondutance amplifier, the amplitude of integrator electronic circuit output voltage is restricted, pass through again PWM modulation circuit, rear class gate driver and switching power tube, after low-pass filtering, the restricted voltage signal of output amplitude, plays the effect of Power Limitation.When a little less than input signal, the amplitude limiter circuit in the utility model does not participate in work, consumes hardly unnecessary power.The utility model has been realized the object that continuous power regulates simultaneously, has obtained better auditory effect, can improve client's perception.
Persons of ordinary skill in the art may appreciate that the respective embodiments described above are to realize specific embodiment of the utility model, and in actual applications, can do various changes to it in the form and details, and do not depart from spirit and scope of the present utility model.
Claims (4)
1. a circuit that regulates continuously D class power amplifier power, comprises amplitude limiter circuit and D class power amplification circuit, it is characterized in that,
Described D class power amplification circuit comprises integrator electronic circuit; Described amplitude limiter circuit is attempted by between the input and output of described integrator electronic circuit; Input using the output of described integrator electronic circuit as described amplitude limiter circuit;
Described amplitude limiter circuit comprises trsanscondutance amplifier electronic circuit, current mirror electronic circuit and limiter transistor, the voltage of the described amplitude limiter circuit of input and the difference of default deboost are converted to current value by described trsanscondutance amplifier electronic circuit, and the input of described integrator electronic circuit is shunted; Described current mirror electronic circuit provides bias current for described trsanscondutance amplifier electronic circuit, and described limiter transistor is carried out level shift to described default deboost.
2. the circuit of continuous adjusting D class power amplifier power according to claim 1, is characterized in that, described trsanscondutance amplifier electronic circuit comprises p channel transistor P1～P8 and N channel transistor N1～N6; Described current mirror electronic circuit comprises p channel transistor P9, P10 and N channel transistor N7～N9; Described limiter transistor is N10;
Wherein, the source electrode of described P1, described P2, described P3, described P4, described P5, described P6, described P7, described P8, described P9 and described P10 all connects supply voltage VDD; The grid of the grid of the grid of described P1, the drain electrode of described P5, described P6 and drain electrode, described P7 is all connected with the drain electrode of described N4; The grid of described N1, the grid of described N2 and drain electrode are all connected with the drain electrode of described P2; The grid of described P2, the grid of described P3 and drain electrode, the drain electrode of described P4 and the grid of described P8 are all connected with the drain electrode of described N3; The grid of described P4, described P5, described P9, the grid of described P10 and drain electrode are all connected with the drain electrode of described N8; The grid of the grid of described N5 and drain electrode, described N6 is all connected with the drain electrode of described P7; The grid of described N3 and described N4, the drain electrode of described N10 and grid are all connected with the drain electrode of described P9; After linking together, the grid of described N7, described N8 and described N9 is connected with current source;
The source grounding of described N1, described N2, described N5, described N6, described N7, described N8 and described N9; The source electrode of described N3 and described N4 is respectively as first input end and second input of described amplitude limiter circuit; The drain electrode of described P8 and described N6 links together as the first output of described amplitude limiter circuit; The drain electrode of described P1 and the drain electrode of described N1 link together as the second output of described amplitude limiter circuit; The drain electrode of described N7 is all connected deboost Vs with the source electrode of described N10.
3. the circuit of continuous adjusting D class power amplifier power according to claim 2, is characterized in that, the mirror image ratio of the mirror image ratio of the electric current by described P2 and described P3 and the electric current by described P6 and described P7 is 1:1.
4. the circuit of continuous adjusting D class power amplifier power according to claim 2, is characterized in that, described D class power amplification circuit also comprises adjusting electronic circuit;
Described integrator electronic circuit comprises: capacitor C 1～C6, resistance R 11, R12, R13, R21, R22 and R23, operational amplifier A 1 and A2; Described adjusting electronic circuit comprises triangular-wave generator TRIP, comparator B1 and B2; Gate driver and switching power tube M1～M4;
Wherein, the first end of described R11 and described R21 connects respectively forward input voltage and reverse input voltage; Described C1, described C2 and described C3 order are connected, described C4, described C5 and described C6 order are connected, the second end of described R11 is connected with the in-phase input end of the positive pole of described C1, described A1 and the first end of described R12 simultaneously, and the positive pole of described C1 is connected with the first output of described amplitude limiter circuit; The second end of described R21 is connected with the inverting input of the positive pole of described C4, described A1 and the first end of described R22 simultaneously, and the positive pole of described C4 is connected with the second output of described amplitude limiter circuit; The reversed-phase output of described A1 is connected with the first end of the negative pole of described C1, described R13 and the positive pole of described C2 simultaneously, the in-phase output end of described A1 is connected with the first end of the negative pole of described C4, described R23 and the positive pole of described C5 simultaneously, the second end of described R13 is connected with the in-phase input end of the negative pole of described C2, described A2 and the positive pole of described C3 simultaneously, and the second end of described R23 is connected with the inverting input of the negative pole of described C5, described A2 and the positive pole of described C6 simultaneously; The negative pole of described C3, the reversed-phase output of described A2 are connected with the in-phase input end of described B1 and the first input end of described amplitude limiter circuit simultaneously; The negative pole of described C6, the in-phase output end of described A2 are connected with the in-phase input end of described B2 and the second input of described amplitude limiter circuit simultaneously; The inverting input of described B1 is all connected with described TRIP with the inverting input of described B2; The output of described B1 and described B2 uses as the input of described gate driver, and the grid of described switching power tube M1 and described M2 all connects the output of described gate driver; The grid of described switching power tube M3 and described M4 all connects the output of described gate driver; The reversed-phase output of described M1 and D class power amplification circuit described in the drain electrode of described M2 and the second end phase downlink connection of described R12, the in-phase output end of described M3 and D class power amplification circuit described in the drain electrode of described M4 and the second end phase downlink connection of described R22; The source electrode of described M1 and described M4 is connected described power power-supply PVDD; The source grounding of described M2 and described M3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420188190.XU CN204031076U (en) | 2014-04-17 | 2014-04-17 | A kind of circuit of continuous adjusting D class power amplifier power |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420188190.XU CN204031076U (en) | 2014-04-17 | 2014-04-17 | A kind of circuit of continuous adjusting D class power amplifier power |
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| CN204031076U true CN204031076U (en) | 2014-12-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106487343A (en) * | 2015-08-31 | 2017-03-08 | 恩智浦有限公司 | Drive circuit for the power stage of class-D amplifier |
| CN108736848A (en) * | 2018-08-20 | 2018-11-02 | 上海艾为电子技术股份有限公司 | A kind of digital audio frequency power amplifier and electronic equipment |
| CN113541480A (en) * | 2021-09-15 | 2021-10-22 | 武汉市聚芯微电子有限责任公司 | Voltage-stabilizing power regulating circuit, power regulating device and electronic device |
-
2014
- 2014-04-17 CN CN201420188190.XU patent/CN204031076U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106487343A (en) * | 2015-08-31 | 2017-03-08 | 恩智浦有限公司 | Drive circuit for the power stage of class-D amplifier |
| CN106487343B (en) * | 2015-08-31 | 2022-02-08 | 恩智浦有限公司 | Driver circuit for a power stage of a class D amplifier |
| CN108736848A (en) * | 2018-08-20 | 2018-11-02 | 上海艾为电子技术股份有限公司 | A kind of digital audio frequency power amplifier and electronic equipment |
| CN108736848B (en) * | 2018-08-20 | 2023-09-08 | 上海艾为电子技术股份有限公司 | Digital audio power amplifier and electronic equipment |
| CN113541480A (en) * | 2021-09-15 | 2021-10-22 | 武汉市聚芯微电子有限责任公司 | Voltage-stabilizing power regulating circuit, power regulating device and electronic device |
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