CN203675092U - Low-power dynamic three-state CMOS or gate circuit - Google Patents

Abstract

The utility model discloses a low-power dynamic three-state CMOS or gate circuit comprising a preset circuit, an input circuit, and an output circuit for controlling a determining latch. The preset circuit comprises nMOS transistors N4 and N10. The input circuit comprises nMOS transistors N5, N6, N7, and N8. The output circuit for controlling a determining latch comprises pMOS transistors P1, P2, and P3 and nMOS transistors N1, N2, N3, and N9. The source electrode of the pMOS transistor P1 is connected with the operating voltage VDD. The source electrodes of the nMOS transistors N1 and N2 are connected with ground. The source electrodes of the nMOS transistors N4 and N10 are connected with voltage equal to a half of VDD. The gate electrodes of the N4 and N10 in the preset circuit are connected with a clock signal CP and the drain electrodes of the N4 and N10 are respectively connected with NOT Q and Q. The low-power dynamic three-state CMOS or gate circuit has beneficial effects of low delay, low wiring area, low power consumption, good logic flexibility, and increased information amount.

Description

The dynamic three value CMOS OR circuit of a kind of low-power consumption

Technical field

The utility model relates to a kind of CMOS OR circuit, and more specifically, it relates to the dynamic three value CMOS OR circuit of a kind of low-power consumption.

Background technology

In recent years, low-power consumption has become one of key factor of restriction VLSI circuit design, and its importance is mainly reflected in two aspects: the first, and along with the raising of VLSI integrated level and the improvement of technique, its density and complexity increase.If can not well control power consumption, the heat that chip produces can cause function reduction and produce even misdeed of stability problem, increases the cost of encapsulation and heat radiation simultaneously; The second, huge power consumption is also used the portable set of battery to affect use because battery easily exhausts.

The advantage such as the integrated level high, low in energy consumption (particularly quiescent dissipation is very little) of cmos circuit, antijamming capability are strong, makes cmos circuit become the major technique of integrated circuit.And the scope of application of CMOS technology constantly changes, the innovation of the technology such as deep sub-micron technique and silicon planner technology design and encapsulation makes device density reach unprecedented height, for the dream that realizes electronic system all functions (SOC) in a silicon chip provides new opportunity.

Along with the fast development of integrated circuit technology, wiring area has become the main factor of restriction chip area, and the proposition of multi valued logic provides a kind of effective way for reducing chip internal line and chip area.Meanwhile, in the time processing identical information amount, use the required transmission line number of the multi-valued signal of the high information amount of carrying much smaller than the number that uses binary signal, can effectively improve the room and time utilance of circuit.Therefore, in recent years the research of multi valued logic has been caused to increasing attention.

In the method that realizes low-power consumption, dynamic circuit causes increasing concern, because dynamic circuit has lower power consumption.In dynamic circuit, dynamic energy consumption control is a very important function, and it whether in the degree that uses and use, carrys out control device by switch for circuit devcie, makes not need the device of work to close, thus consumed energy not.Dynamic circuit also has superiority than static circuit at the aspect such as speed, chip area simultaneously.

Summary of the invention

The purpose of this utility model is to overcome deficiency of the prior art, provides a kind of rational in infrastructure, the dynamic three value CMOS OR circuit of low-power consumption that low in energy consumption and operating state is controlled.

This low-power consumption dynamic three is worth CMOS OR circuit, comprises the output circuit of prewired circuit, input circuit and the control of judgement latch;

Described prewired circuit comprises nMOS pipe N4 and N10; Described input circuit comprises nMOS pipe N5, N6, N7, N8; The output circuit of described judgement latch control comprises pMOS pipe P1, P2, P3 and nMOS pipe N1, N2, N3, N9;

The source class of described pMOS pipe P1 meets operating voltage VDD; The source class ground connection of described nMOS pipe N1, N2; The source class of described nMOS pipe N4, N10 meets voltage 1/2VDD;

The grid of described prewired circuit N4 and N10 connects clock CP signal, and drain electrode connects respectively output

and Q;

The grid of described input circuit N5, N6, N7, N8 connect respectively input signal x, y,

n5 and N6 series connection, N7 and N8 series connection; The drain electrode of N5 and N7 connects respectively output and Q;

The output circuit of described judgement latch control comprises clock control circuit and difference latch control circuit two parts; Described clock control circuit, comprises pMOS pipe P1 and nMOS pipe N1, N2; Described difference latch control circuit, comprises pMOS pipe P2, P3 and nMOS pipe N3, N9;

The grid of described judgement latch circuit output P1 connects clock CP signal, and the grid of N1, N2 connects clock

signal; P2 and N3 source-drain electrode are connected in series, and connected node is output signal p3 and N9 source-drain electrode are connected in series, and connected node is output signal Q; P2 is connected with N3 grid, and is connected to output signal Q; P3 is connected with N9 grid, and is connected to output signal Q.

The beneficial effects of the utility model are: differential configuration makes circuit have advantages of that delay is little, wiring area is little, low in energy consumption, have very strong logic flexibility, and owing to having used many-valued technology, increase the amount of information of circuit, while is due to the utilization of dynamic technique, not only further reduce circuit power consumption, and made the operating state of circuit controlled.

Brief description of the drawings

Fig. 1 is the utility model circuit theory diagrams;

Embodiment

Below in conjunction with drawings and Examples, the utility model is described further.Although the utility model is described in connection with preferred embodiment, should know, do not represent that the utility model is limited in described embodiment.On the contrary, the utility model is by alternative, modified model and the equivalent contained in the scope of the present utility model that can be included in attached claims restriction.

Dynamic circuit is a class digital circuit, and it realizes its logical value by the capacitor charge and discharge on node, and the definite of output logic value inputted with clock and decided by signal.Therefore, clock in one-period, undertaking synchronously, the task of control and threshold value charging.

Research shows, although static circuit use easily, and static circuit sometimes power consumption is also very low, dynamic circuit at least has very fast speed in some circuit uses, and only needs little pipe.Static circuit is lower to the tolerance limit of noise, and the existing very little input capacitance of dynamic circuit has very high current carrying capacity.Static circuit needs some extra pipes to limit transmission delay in interconnecting between logical block simultaneously, and dynamic circuit does not just have this necessity.

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail, it is more obvious that object of the present invention and effect will become.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.

The dynamic three value CMOS OR circuit of a kind of low-power consumption of the present utility model as shown in Figure 1.

Comprise: the output circuit of prewired circuit, input circuit and the control of judgement latch.

Described prewired circuit comprises nMOS pipe N4 and N10; Described input circuit comprises nMOS pipe N5, N6, N7, N8; Described judgement latch circuit output comprises pMOS pipe P1, P2, P3 and nMOS pipe N1, N2, N3, N9.

The source class of described pMOS pipe P1 meets operating voltage VDD; The source class ground connection of described nMOS pipe N1, N2; The source class of described nMOS pipe N4, N10 meets voltage 1/2VDD.

The grid of described prewired circuit N4 and N10 connects clock CP signal, and drain electrode connects respectively output

and Q.

The grid of described input circuit N5, N6, N7, N8 connect respectively input signal x, y,

n5 and N6 series connection, N7 and N8 series connection; The drain electrode of N5 and N7 connects respectively output

and Q.

The output circuit of described judgement latch control comprises clock control circuit and difference latch control circuit two parts; Described clock control circuit, comprises pMOS pipe P1 and nMOS pipe N1, N2; Described difference latch control circuit, comprises pMOS pipe P2, P3 and nMOS pipe N3, N9.

The grid of described judgement latch circuit output P1 connects clock CP signal, and the grid of N1, N2 connects clock

signal; P2 and N3 source-drain electrode are connected in series, and connected node is output signal

p3 and N9 source-drain electrode are connected in series, and connected node is output signal Q; P2 is connected with N3 grid, and is connected to output signal Q; P3 is connected with N9 grid, and is connected to output signal Q.

When CP is logic high,

during for logic low, N2, P1 and N1 cut-off, judgement latch circuit output is closed, and does not connect the path of VDD (logic high) or GND (logic low); Simultaneously N4 and N10 conducting, prewired circuit is normally worked, output node Q and

be predisposed to 1/2VDD (logic intermediate level).

When CP is logic low,

during for logic high, prewired circuit cut-off, N2, P1, the equal conducting of N1, judgement latch is normally worked, and at this moment exports by input and determines:

(1) in the time that input x, y are high level,

be all low level, the path conducting ground connection being formed by N5 and N6, the path being made up of N7 and N8 ends,

for low level; Simultaneously

low level feed back to P3 grid by difference channel, make P3 conducting, output Q is high level.

(2) in the time that input x, y are low level, be all high level, the path being made up of N5 and N6 ends, the path conducting ground connection being formed by N7 and N8, and output Q is low level; The low level of Q feeds back to P2 grid by difference channel simultaneously, makes P2 conducting, for high level.

(3) when input x is that low level, y are high level, or x is high level, y while being low level, and path be made up of N5 and N6 ends, and the path being made up of N7 and N8 also ends, and exports Q and remains intermediate level.

Represent input and output high level VDD with H, M represents input and output intermediate level 1/2VDD, and L represents input and output low level GND.According to the course of work above, the operating state that can sum up the dynamic three value CMOS OR circuit of described a kind of low-power consumption is as shown in the table:

Claims (1)

1. the dynamic three value CMOS OR circuit of low-power consumption, is characterized in that: the output circuit that comprises prewired circuit, input circuit and the control of judgement latch;

Described prewired circuit comprises nMOS pipe N4 and N10; Described input circuit comprises nMOS pipe N5, N6, N7, N8; The output circuit of described judgement latch control comprises pMOS pipe P1, P2, P3 and nMOS pipe N1, N2, N3, N9;

The source class of described pMOS pipe P1 meets operating voltage VDD; The source class ground connection of described nMOS pipe N1, N2; The source class of described nMOS pipe N4, N10 meets voltage 1/2VDD;

The grid of described prewired circuit N4 and N10 connects clock CP signal, and drain electrode connects respectively output

and Q;

The grid of described input circuit N5, N6, N7, N8 connect respectively input signal x, y,

n5 and N6 series connection, N7 and N8 series connection; The drain electrode of N5 and N7 connects respectively output

and Q;

The output circuit of described judgement latch control comprises clock control circuit and difference latch control circuit two parts; Described clock control circuit, comprises pMOS pipe P1 and nMOS pipe N1, N2; Described difference latch control circuit, comprises pMOS pipe P2, P3 and nMOS pipe N3, N9;

The grid of described judgement latch circuit output P1 connects clock CP signal, and the grid of N1, N2 connects clock

signal; P2 and N3 source-drain electrode are connected in series, and connected node is output signal p3 and N9 source-drain electrode are connected in series, and connected node is output signal Q; P2 is connected with N3 grid, and is connected to output signal Q; P3 is connected with N9 grid, and is connected to output signal Q.

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