CN203660866U - Pulse top rush elimination circuit of pulse transformer - Google Patents
Pulse top rush elimination circuit of pulse transformer Download PDFInfo
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- CN203660866U CN203660866U CN201320889684.6U CN201320889684U CN203660866U CN 203660866 U CN203660866 U CN 203660866U CN 201320889684 U CN201320889684 U CN 201320889684U CN 203660866 U CN203660866 U CN 203660866U
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- switching tube
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- pulse transformer
- elimination
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- 230000008030 elimination Effects 0.000 title claims abstract description 15
- 238000003379 elimination reaction Methods 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 claims description 6
- 238000010923 batch production Methods 0.000 abstract description 2
- 230000001934 delay Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Abstract
The utility model discloses a pulse top rush elimination circuit of a pulse transformer. The pulse top rush elimination circuit comprises a pulse transformer and a pulse top rush elimination module connected therewith. With the above structure, the pulse top rush elimination circuit has the following advantages that firstly, time delays of a V1 and a V2 can be manually or automatically adjusted based on changes of a load to eliminate pulse top rush to minimize damage to the load; and secondly, requirements for design of a pulse transformer are reduced and thus batch production of products can be conveniently achieved.
Description
Technical field
The utility model relates to transformer technology field, and particularly a kind of elimination pulse of pulse transformer top rushes circuit.
Background technology
Because pulse transformer unavoidably will exist distributed capacitance, distributed inductance and leakage inductance in development process, these factors can determine that the output waveform of pulse transformer can be very not desirable, there is vibration in top, comprise top punching (output voltage waveform as shown in Figure 4), larger to load harm, can change Pulse Transformer Design parameter and increase more subsidiary loop for fixing load, reduce top punching and vibration, but for the load changing, to change at any time auxiliary parameter, cause and use trouble.
Utility model content
Technical problem to be solved in the utility model is, for the deficiencies in the prior art, to provide the elimination pulse top of the pulse transformer of the infringement of a kind of reduction to load to rush circuit.
For solving the problems of the technologies described above, the technical solution of the utility model is: a kind of elimination pulse top of pulse transformer rushes circuit, the pulse top die block that disappears that comprises pulse transformer and be connected with pulse transformer.
The described pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance R1, the elementary of described pulse transformer is connected with the collector electrode of switching tube V1, switching tube V2 respectively, described switching tube V2 emitting stage ground connection, the emitting stage of described switching tube V1 is by current-limiting resistance R1 ground connection.
Described switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor.
The described pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance, elementary and the collector electrode of switching tube V1 of described pulse transformer is connected, the emitter of described switching tube V1 is connected with the collector electrode of switching tube V2, and the emitter of switching tube V1 is by current-limiting resistance R1 ground connection.
Described switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor.
The utility model adopts said structure, has the following advantages: the time delay that 1, can adjust manually or automatically V1 and V2 according to the variation of load is eliminated pulse top and fallen, and reduces the infringement to load; 2, reduce the requirement of pulse transformer design, be convenient to the batch production of product.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail;
Fig. 1 is the structural representation of embodiment mono-in the utility model;
Fig. 2 is the structural representation of embodiment bis-in the utility model;
Fig. 3 is pulse transformer output voltage waveform in the utility model;
Fig. 4 is the pulse transformer output voltage waveform of background technology in the utility model;
Embodiment
The elimination pulse of pulse transformer top rushes a circuit as shown in FIG. 1 to 3, comprises pulse transformer, also comprises the pulse top die block that disappears being connected with pulse transformer.The pulse top die block that disappears that comprises pulse transformer and be connected with pulse transformer.
Embodiment mono-
The pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance R1, the elementary of pulse transformer T1 is connected with the collector electrode of switching tube V1, switching tube V2 respectively, switching tube V2 emitting stage ground connection, the emitting stage of switching tube V1 is by current-limiting resistance R1 ground connection.Switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor, or other semiconductor switch.
Drive signal first to supply with switching tube V1, after switching tube V1 conducting, power supply is supplied with pulse transformer T1 after by current-limiting resistance R1 current limliting, because the resistance of current-limiting resistance R1 is larger, can avoid the resonance of circuit, after certain hour, send and drive signal by switching tube V2 conducting, switching tube V1 and current-limiting resistance R1 are ineffective, and it is elementary that voltage is all added in pulse transformer T1, conversion efficiency is identical with original circuit, and output voltage waveforms as shown in Figure 3.The time delay that can adjust manually or automatically switching tube V1 and switching tube V2 according to the variation of load is eliminated pulse top and is fallen.
Embodiment bis-
The pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance, elementary and the collector electrode of switching tube V1 of described pulse transformer is connected, the emitter of described switching tube V1 is connected with the collector electrode of switching tube V2, and the emitter of switching tube V1 is by current-limiting resistance R1 ground connection.Switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor, or other semiconductor switch.The operation principle of embodiment bis-is identical with embodiment mono-, just less to the current requirements of switching tube V1 in circuit.
By reference to the accompanying drawings the utility model is exemplarily described above; obviously the utility model specific implementation is not subject to the restrictions described above; as long as the various improvement that adopted the technical solution of the utility model to carry out; or directly apply to other occasion without improvement, all within protection range of the present utility model.
Claims (5)
1. the elimination pulse of pulse transformer top rushes a circuit, it is characterized in that: the pulse top die block that disappears that comprises pulse transformer and be connected with pulse transformer.
2. the elimination pulse of a kind of pulse transformer according to claim 1 top rushes circuit, it is characterized in that: the described pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance R1, the elementary of described pulse transformer is connected with the collector electrode of switching tube V1, switching tube V2 respectively, described switching tube V2 emitting stage ground connection, the emitting stage of described switching tube V1 is by current-limiting resistance R1 ground connection.
3. the elimination pulse of a kind of pulse transformer according to claim 2 top rushes circuit, it is characterized in that: described switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor.
4. the elimination pulse of a kind of pulse transformer according to claim 1 top rushes circuit, it is characterized in that: the described pulse top die block that disappears comprises switching tube V1, switching tube V2, current-limiting resistance, elementary and the collector electrode of switching tube V1 of described pulse transformer is connected, the emitter of described switching tube V1 is connected with the collector electrode of switching tube V2, and the emitter of switching tube V1 is by current-limiting resistance R1 ground connection.
5. the elimination pulse of a kind of pulse transformer according to claim 4 top rushes circuit, it is characterized in that: described switching tube V1, switching tube V2 all adopt triode or insulated gate bipolar transistor or field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320889684.6U CN203660866U (en) | 2013-12-31 | 2013-12-31 | Pulse top rush elimination circuit of pulse transformer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320889684.6U CN203660866U (en) | 2013-12-31 | 2013-12-31 | Pulse top rush elimination circuit of pulse transformer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203660866U true CN203660866U (en) | 2014-06-18 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320889684.6U Expired - Fee Related CN203660866U (en) | 2013-12-31 | 2013-12-31 | Pulse top rush elimination circuit of pulse transformer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203660866U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103746542A (en) * | 2013-12-31 | 2014-04-23 | 芜湖国睿兆伏电子有限公司 | Circuit for eliminating pulse impacting of pulse transformer |
-
2013
- 2013-12-31 CN CN201320889684.6U patent/CN203660866U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103746542A (en) * | 2013-12-31 | 2014-04-23 | 芜湖国睿兆伏电子有限公司 | Circuit for eliminating pulse impacting of pulse transformer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140618 |