CN203659858U - High-voltage ESD protective device of zener-zap small hysteresis SCR structure - Google Patents
High-voltage ESD protective device of zener-zap small hysteresis SCR structure Download PDFInfo
- Publication number
- CN203659858U CN203659858U CN201320799954.4U CN201320799954U CN203659858U CN 203659858 U CN203659858 U CN 203659858U CN 201320799954 U CN201320799954 U CN 201320799954U CN 203659858 U CN203659858 U CN 203659858U
- Authority
- CN
- China
- Prior art keywords
- isolated area
- trap
- metal
- esd
- zener
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a high-voltage ESD protective device of a zener-zap small hysteresis SCR structure. The ESD protective device can be applied to an on-chip IC high-voltage ESD protective circuit and comprises a P-type substrate, an N-type buried layer, a first N trap, a P trap, sinking P doping, a second N trap, an isolation area , a first N+, a first P+, a second N+, a second P+, a third N+, a third P+, a fourth N+, a fourth P+, a fifth N+, a fifth P+, a metal anode, and a metal cathode. A zener is composed of a first metal anode, the metal cathode, the first N+, the first P+, the third N+, the third P+, the second N+ and the second P+, or is composed of a second metal anode, the metal cathode, the fifth N+, the fifth P+, the third N+, the third P+, the fourth N+ and the fourth P+ as to break down an ESD current discharge path. By breaking the ESD current discharge path through the zener, the ESD robustness of the device is enhanced, the holding voltages of the device are also improved. Therefore, the high-voltage ESD protective device provided by the utility model is suitable for high-voltage ESD protection of a narrow ESD window.
Description
Technical field
The invention belongs to the electrostatic protection field of integrated circuit, relate to a kind of high pressure esd protection device, be specifically related to a kind of high pressure esd protection device of little time stagnant SCR structure of Zener breakdown, can be used for improving the reliability of IC high pressure esd protection on sheet.
Background technology
Along with the fast development of Based Power Integrated Circuit Technology, electronic product is miniaturization day by day, makes people be easier to dailyly carry and use.But, follow portable hard drive, flash card, USB interface and smart mobile phone show that the quantity required of the electronic products such as touch-screen constantly increases, the integrity problem that integrated circuit (IC) products occurs also becomes increasingly conspicuous.As flash card suddenly data cannot read, USB interface cannot be carried out data communication, shows that the unreliability problems such as touch layer unexpected blank screen more and more cause people's attention.According to finding after causing the many factors investigation that integrated circuit (IC) products lost efficacy: ESD causes the inefficacy of circuit product, be that integrated circuit (IC) products produces the large principal element in the many factors of fault.And the high pressure esd protection of power integrated circuit interface in above-mentioned electronic product is again the large technological difficulties in whole Circuits System ESD protection Design.Present most of high pressure esd protection device; high pressure esd protection device is difficult to meet the many requirement of power integrated circuit to high pressure esd protection device: as should be had the voltage that maintains higher than operating voltage; there is again the trigger voltage lower than grid oxygen puncture voltage as far as possible, also want to pass through the ESD robust detection standard of IEC6001-4-2 simultaneously.In brief, existing high pressure esd protection lacks the ESD protective device of the strong robustness that can meet narrow ESD window.Herein for existing high pressure esd protection technical barrier; a kind of technical scheme that has high maintenance voltage, strong robustness, can meet narrow ESD window has been proposed; this scheme result after flow experiment and test proves: to return stagnant amount very little with maintaining voltage between voltage for its trigger voltage, and the while has again very strong ESD robustness.
Summary of the invention
Based on the feature of IC high pressure esd protection device and BCD high-pressure process on sheet; make full use of SCR device and have that trigger voltage is low, conducting resistance is little, secondary breakdown current is large, the advantage of fast response time etc.; after Zener breakdown, there is the physical characteristic of voltage stabilizing in conjunction with reverse-biased N+/P+ diode; to clamp down on reverse-biased PN junction both end voltage in SCR structure, thereby realize the object of high maintenance voltage.The present invention proposes a kind of high pressure esd protection device of little time stagnant SCR structure of Zener breakdown; its trigger voltage is mainly subject to the impact of reverse-biased described the 2nd N+/described P trap knot; compared with existing high pressure esd protection device; the present invention can effectively reduce device trigger voltage, improve esd protection device maintain voltage and secondary breakdown current, there is the advantages such as leakage current is little, conducting resistance is little, fast response time simultaneously.
The present invention is achieved through the following technical solutions:
A kind of high pressure esd protection device of little time stagnant SCR structure of Zener breakdown, it comprises the ESD current drain path of two SCR structures and the ESD current drain path of two Zener breakdowns, to improve the ESD robustness that maintains voltage and enhance device, it is characterized in that: comprise P type substrate, n type buried layer, the one N trap, P trap, the 2nd N trap, sinking P doping, the first isolated area, the second isolated area, the 3rd isolated area, the 4th isolated area, the 5th isolated area, the 6th isolated area, the 7th isolated area, the 8th isolated area, the 9th isolated area, the one N+, the one P+, the 2nd N+, the 2nd P+, the 3rd N+, the 3rd P+, the 4th P+, the 4th N+, the 5th P+, the 5th N+, the first metal 1, the second metal 1, the 3rd metal 1, the 4th metal 1, five metals belongs to 1, the 6th metal 1, the first metal 2, the second metal 2, the 3rd metal 2,
Described N+ buried regions is in the surface element subregion of described P type substrate, on the surface of described N+ buried regions and described P type substrate, from left to right respectively be a described N trap, described P trap and described the 2nd N trap, the right side of a described N trap is connected with the left side of described P trap, the right side of described P trap be connected with the left side of described the 2nd N trap, the left side of described N+ buried regions and a described N trap, the left side of described N+ buried regions and the horizontal overlapping lateral length of described the 2nd N trap must be greater than certain certain value;
In a described N trap surf zone, be from left to right provided with successively a described N+, described the second isolated area, a described P+, described the 3rd isolated area, between the left side edge of described P type substrate and a described N+, be provided with described the first isolated area, the left side of described the first isolated area is connected with the left side edge of described P type substrate, the right side of described the first isolated area is connected with a described N+ left side, a described N+ right side is connected with the left side of described the second isolated area, the right side of described the second isolated area is connected with the left side of a described P+, the right side of a described P+ is connected with the left side of described the 3rd isolated area,
Described the 2nd N+, across the surface element subregion at a described N trap and described P trap, is provided with described the 3rd isolated area between described the 2nd N+ and a described P+; The right side of described the 3rd isolated area is connected with the left side of described the 2nd N+;
In described P trap surf zone, be from left to right provided with successively described the 2nd P+, described sinking P doping and described the 4th P+, in described sinking P doping surfaces region, be from left to right provided with successively described the 4th isolated area, described the 3rd N+, described the 5th isolated area, described the 3rd P+ and described the 6th isolated area, the horizontal spacing between the right side of described the 2nd N+ and the left side of described the 2nd P+ can rationally regulate control according to different ESD design window demands;
Described the 2nd P+ is across the surface element subregion in described P trap and described sinking P doping, between the right side of the left side of described the 2nd N+ and described the 2nd P+, must reserve in the horizontal direction the interval of a certain fixed value, the right side of described the 2nd P+ is connected with the left side of described the 4th isolated area, the right side of described the 4th isolated area is connected with the left side of described the 3rd N+, the right side of described the 3rd N+ is connected with the left side of described the 5th isolated area, the right side of described the 5th isolated area is connected with the left side of described the 3rd P+, the right side of described the 3rd P+ is connected with the left side of described the 6th isolated area, the right side of described the 6th isolated area is connected with the left side of described the 4th P+,
Described the 4th N+ is across the surface element subregion between described P trap and described the 2nd N trap, the interval that must reserve in the horizontal direction a certain fixed value between described the 4th P+ and described the 4th N+, the horizontal spacing between the right side of described the 4th P+ and the left side of described the 4th N+ can rationally regulate control according to different ESD design window demands;
In described the 2nd N trap surf zone, be from left to right provided with successively described the 7th isolated area, described the 5th P+, described the 8th isolated area and described the 5th N+, between described the 4th N+ and described the 5th P+, be provided with described the 7th isolated area, between described the 5th N+ and described P type substrate right side edge, be provided with described the 9th isolated area, the right side of described the 4th N+ is connected with the left side of described seven isolated areas, the right side of described the 7th isolated area is connected with the left side of described the 5th P+, the right side of described the 5th P+ is connected with the left side of described the 8th isolated area, the right side of described the 8th isolated area is connected with the left side of described the 5th N+, the right side of described the 5th N+ is connected with the left side of described the 9th isolated area, the right side of described the 9th isolated area is connected with the right side edge of P type substrate,
Described the first metal 1, described the second metal 1 are connected with a described N+, a described P+ respectively, described the first metal 2 is all connected with described the second metal 1 with described the first metal 1, form the first metal anode of device, described five metals belongs to 1, described the 6th metal 1 is connected with described the 5th P+, described the 5th N+ respectively, described the 3rd metal 2 belongs to 1 with described five metals and is all connected with described the 6th metal 1, forms the second metal anode of device;
Described the 3rd metal 1, described the 4th metal 1 are connected with described the 3rd N+, described the 3rd P+ respectively, and described the second metal 2 is all connected with described the 4th metal 1 with described the 3rd metal 1, form the metallic cathode of device.
The ESD current drain path that described the first metal anode, a described N+, a described P+, a described N trap, described the 2nd N+, described the 2nd P+, described sinking P doping, described the 3rd N+, described the 3rd P+ and described metallic cathode form Article 1 Zener diode triggers SCR, maintains voltage and secondary breakdown current with what improve device.
Described the second metal anode, described the 5th N+(125), described the 5th P+(124), described the 2nd N trap (105), described the 4th N+(123), described the 4th P+(122), described sinking P adulterate (106), described the 3rd N+(120), described the 3rd P+(121) and the described metallic cathode ESD current drain path that forms Article 2 Zener diode and trigger SCR, maintain voltage and secondary breakdown current with what improve device.
Useful technique effect of the present invention is:
(1) advantages such as example device of the present invention takes full advantage of that SCR opening speed is fast, secondary breakdown current large (ESD strong robustness), conducting resistance are little, the ESD current drain path of triggering SCR by the Article 1 Zener diode that utilizes described the first metal anode, a described N+, a described P+, a described N trap, described the 2nd N+, described the 2nd P+, described sinking P doping, described the 3rd N+, described the 3rd P+ and described metallic cathode to form again, maintains voltage and secondary breakdown current with what improve device.
(2) the ESD current drain path that the second metal anode described in example devices use of the present invention, described the 5th N+, described the 5th P+, described the 2nd N trap, described the 4th N+, described the 4th P+, described sinking P doping, described the 3rd N+, described the 3rd P+ and described metallic cathode form Article 2 Zener diode and trigger SCR, maintains voltage and secondary breakdown current with what improve device.
(3) the present invention utilizes described Article 1 Zener diode to trigger the ESD current drain path of SCR and the ESD current drain path that described Article 2 Zener diode triggers SCR, does not form interdigital symmetrical structure, maintains voltage and reduces chip area to improve.
The physical characteristic that positive feedback mechanism in example devices use SCR structure of the present invention and Zener diode puncture, to reduce trigger voltage, can also, by regulating certain crucial domain characteristic parameter and stack technology, maintain voltage to improve, obtain small voltage and return the ESD characteristic curve of stagnant amount.Simultaneously; example device of the present invention, because there being many ESD current drain paths, can reduce conducting resistance, to improve secondary breakdown current; realize the high pressure esd protection of different voltage range strong robustness, can be applied to the high pressure esd protection in the power integrated circuit product of different demands.
accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is embodiment of the present invention internal structure generalized section;
Fig. 2 is the electricity connection layout of example of the present invention under esd pulse effect;
Fig. 3 is the equivalent electric circuit of example of the present invention under esd pulse effect;
Fig. 4 is the ESD current drain path of example of the present invention under esd pulse effect.
Embodiment
The present invention proposes a kind of high pressure esd protection device of little time stagnant SCR structure of Zener breakdown; because it is mainly used in high pressure esd protection field; need to be based on High voltage BCD process platform; by some characteristic parameter of appropriate design control device domain, can prepare the esd protection device of the multiple high pressure esd protection of meeting of different size demand.Such devices has two ESD current lead-through paths, the wherein circuit structure of Zener breakdown and there is the SCR structure of positive feedback mechanism, trigger voltage, the raising that can reduce device maintain voltage and secondary breakdown current, also have the advantages such as leakage current is little, conducting resistance is little, fast response time simultaneously.
As shown in Figure 1; for the section of structure of example device of the present invention; be specially a kind of high pressure esd protection device of little time stagnant SCR structure of Zener breakdown; comprise ESD current drain path and two ESD current drain paths that Zener diode punctures of two SCR structures; to improve secondary breakdown current and to maintain voltage, reduce conducting resistance.It is characterized in that: comprise P type substrate 101, n type buried layer 102, the one N trap 103, P trap 104, the 2nd N trap 105, sinking P doping 106, the first isolated area 107, the second isolated area 108, the 3rd isolated area 109, the 4th isolated area 110, the 5th isolated area 111, the 6th isolated area 112, the 7th isolated area 113, the 8th isolated area 114, the 9th isolated area 115, the one N+ 116, the one P+ 117, the 2nd N+ 118, the 2nd P+ 119, the 3rd N+ 120, the 3rd P+ 121, the 4th P+ 122, the 4th N+ 123, the 5th P+ 124, the 5th N+ 125, the first metal 1 126, the second metal 1 127, the 3rd metal 1 128, the 4th metallized metal 1 129, five metals belongs to 1 130, the 6th metal 1 131, the first metal 2 132, the second metal 2 133, the 3rd metal 2 134.
Described N+ buried regions 102 is in the surface element subregion of described P type substrate 101, on the surface of described N+ buried regions 102 and described P type substrate 101, from left to right respectively be a described N trap 103, described P trap 104 and described the 2nd N trap 105, described N+ buried regions 102 must be greater than certain certain value with a described N trap 103 and described N+ buried regions 102 with the lamination lateral length of described the 2nd N trap 105, to realize the ESD current path of SCR structure current drain, improve the ESD robustness of device.
In described N trap 103 surf zones, be from left to right provided with successively a described N+ 116, described the second isolated area 108, a described P+ 117, described the 3rd isolated area 109, between described P type substrate 101 left side edge and a described N+ 116, be provided with described the first isolated area 107.
Between a described N trap 103 and described P trap 104, surface is provided with described the 2nd N+ 118, described the 2nd N+ 118, across the surface element subregion with described P trap 104 at a described N trap 103, is provided with described the 3rd isolated area 109 between described the 2nd N+ 118 and a described P+ 117.
In described P trap 104 surf zones, be from left to right provided with successively described the 2nd P+ 119, described sinking P doping 106 and described the 4th P+ 122, described sinking P adulterates in 106 surf zones and is from left to right provided with successively described the 4th isolated area 110, described the 3rd N+ 120, described the 5th isolated area 111, described the 3rd P+ 121 and described the 6th isolated area 112, the right side of described the 3rd P+ 121 in described sinking P doping 106 is not provided with the N+ with described the 3rd N+ 120 symmetries, this design can reduce chip layout area on the one hand, on the other hand, this design also can improve and maintain voltage.
Described the 2nd P+ 119 is across the surface element subregion with described sinking P doping 106 at described P trap 104, between described the 2nd N+ 118 and described the 2nd P+ 119, must reserve in the horizontal direction the interval of a certain fixed value, form Zener breakdown state to realize described the 2nd N+ 118 with the reverse-biased PN junction that described the 2nd P+ 119 forms, and clamp down on the voltage at reverse-biased PN junction two ends, reduce the avalanche multiplication factor, maintain voltage to improve.
Described the 4th N+ 123 is across the surface element subregion between described P trap 104 and described the 2nd N trap 105, between described the 4th P+ 122 and described the 4th N+ 123, must reserve in the horizontal direction the interval of a certain fixed value, form Zener breakdown state to realize described the 4th N+ 123 with the reverse-biased PN junction that described the 4th P+ 122 forms, and clamp down on the voltage at reverse-biased PN junction two ends, reduce the avalanche multiplication factor, maintain voltage to improve.
In described the 2nd N trap 105 surf zones, be from left to right provided with successively described the 7th isolated area 113, described the 5th P+ 124, described the 8th isolated area 114 and described the 5th N+ 125, between described the 4th N+ 123 and described the 5th P+ 124, be provided with described the 7th isolated area 113, between described the 5th N+ 125 and described P type substrate 101 right side edge, be provided with described the 9th isolated area 115.
The periphery of described the first isolated area 107 and described the 9th isolated area 115 also can be provided with a P type ring; described P type articulating ground; be operated under high pressure esd protection to realize example device of the present invention, not can with protected chip on other peripheral domains produce the object of parasitic structure.
As shown in Figure 2, described the first metal 1 126, described the second metal 1 127 respectively with a described N+ 116, a described P+ 117 is connected, described the first metal 2 132 is all connected with described the second metal 1 127 with described the first metal 1 126, form the first metal anode of device, described five metals belongs to 1 130, described the 6th metal 1 131 respectively with described the 5th P+ 124, described the 5th N+ 125 is connected, described the 3rd metal 2 134 belongs to 1 130 with described five metals and is all connected with described the 6th metal 1 131, form the second metal anode of device, described the first metal anode is connected with described the second metal anode, connect the high potential of esd pulse.
Described the 3rd metal 1 128, described the 4th metal 1 129 are connected with described the 3rd N+ 120, described the 3rd P+ 121 respectively, described the second metal 2 133 is all connected with described the 4th metal 1 129 with described the 3rd metal 1 128, the metallic cathode that forms device, described metallic cathode connects the electronegative potential of esd pulse.
As shown in Figure 3, in the time that esd pulse acts on example device of the present invention, a described N+ 116, a described P+ 117, described n type buried layer 102, described P trap 104, described sinking P doping 106, described the 3rd N+ 120 and described the 3rd P+ 121 form the ESD current drain path of a common SCR, in the time that the pressure drop of resistance R 1 reaches 0.7 V, parasitic PNP pipe T1 in circuit opens, under the positive feedback role of network of described parasitic PNP pipe T1 and parasitic NPN pipe T2 formation, described parasitic PNP pipe T1 after unlatching improves constantly the pressure drop of dead resistance R2, in the time that the pressure drop in described resistance R 2 also rises to 0.7 V, described parasitic NPN pipe T2 opens, esd pulse electric current is by the SCR structure one part of current of releasing, in like manner, described the 5th N+ 125, described the 5th P+ 124, described the 2nd N trap 105, described n type buried layer 102, described P trap 104, described sinking P doping 106, described the 3rd N+ 120 and described the 3rd P+ 121 form the ESD current drain path of another common SCR, and esd pulse electric current is also by this SCR structure one part of current of releasing
[0023]meanwhile, a described N+ 116, a described N trap 103, described the 2nd N+ 118, described the 2nd P+ 119, described sinking P doping 106 and described the 3rd P+ 121 form the ESD current drain path ZD1 of a Zener diode breakdown.
Described the 5th N+ 125, described two N traps 105, described the 4th N+ 123, described the 4th P+ 122, described sinking P doping 106 and described the 3rd P+ 121 form the ESD current drain path ZD2 of a Zener diode breakdown.
As shown in Figure 4, device is under the effect of ESD high-voltage pulse, the ESD current drain path of described common SCR is respectively as shown in Path 1 and Path 3, the ESD current drain path ZD1 that described Zener diode punctures is as shown in Path 2, the ESD current drain path ZD2 that described Zener diode punctures is as shown in Path 4, described Path 1, described Path 2, described Path 3, not only can increase secondary breakdown current with described Path 4, improve the ESD robustness of device, simultaneously, described Path 2 and described Path 4 have impact to described Path 1 and described Path 3 respectively again, can promote the pressure drop in described resistance R 1 to rapidly increase to 0.7 V on the one hand, reduce trigger voltage, can clamp down on again on the other hand the voltage at reverse-biased PN junction two ends in described Path 1 and described Path 3, reduce the avalanche multiplication factor, improve and maintain voltage, thereby realize small voltage and return stagnant high maintenance voltage, low trigger voltage, the high pressure esd protection of strong ESD robustness.
Finally explanation is, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (3)
1. the high pressure esd protection device of little time stagnant SCR structure of a Zener breakdown, it comprises the ESD current drain path of two SCR structures and the ESD current drain path of two Zener breakdowns, to improve the ESD robustness that maintains voltage and enhance device, it is characterized in that: comprise P type substrate (101), n type buried layer (102), the one N trap (103), P trap (104), the 2nd N trap (105), sinking P adulterate (106), the first isolated area (107), the second isolated area (108), the 3rd isolated area (109), the 4th isolated area (110), the 5th isolated area (111), the 6th isolated area (112), the 7th isolated area (113), the 8th isolated area (114), the 9th isolated area (115), the one N+(116), the one P+(117), the 2nd N+(118), the 2nd P+(119), the 3rd N+(120), the 3rd P+(121), the 4th P+(122), the 4th N+(123), the 5th P+(124), the 5th N+(125), the first metal 1(126), the second metal 1(127), the 3rd metal 1(128), the 4th metal 1(129), five metals belongs to 1(130), the 6th metal 1(131), the first metal 2(132), the second metal 2(133), the 3rd metal 2(134),
Described N+ buried regions (102) is in the surface element subregion of described P type substrate (101), on the surface of described N+ buried regions (102) and described P type substrate (101), from left to right respectively be a described N trap (103), described P trap (104) and described the 2nd N trap (105), the right side of a described N trap (103) is connected with the left side of described P trap (104), the right side of described P trap (104) be connected with the left side of described the 2nd N trap (105), the left side of described N+ buried regions (102) and a described N trap (103), the horizontal overlapping lateral length of the left side of described N+ buried regions (102) and described the 2nd N trap (105) must be greater than certain certain value,
In described N trap (103) surf zone, be from left to right provided with successively a described N+(116), described the second isolated area (108), a described P+(117), described the 3rd isolated area (109), the left side edge of described P type substrate (101) and a described N+(116) between be provided with described the first isolated area (107), the left side of described the first isolated area (107) is connected with the left side edge of described P type substrate (101), the right side of described the first isolated area (107) and a described N+(116) left side be connected, a described N+(116) right side is connected with the left side of described the second isolated area (108), the right side of described the second isolated area (108) and a described P+(117) left side be connected, a described P+(117) right side be connected with the left side of described the 3rd isolated area (109),
Described the 2nd N+(118) across the surface element subregion at a described N trap (103) and described P trap (104), described the 2nd N+(118) and a described P+(117) between be provided with described the 3rd isolated area (109); The right side of described the 3rd isolated area (109) and described the 2nd N+(118) left side be connected;
In described P trap (104) surf zone, be from left to right provided with successively described the 2nd P+(119), described sinking P doping (106) and described the 4th P+(122), in described sinking P doping (106) surf zone, be from left to right provided with successively described the 4th isolated area (110), described the 3rd N+(120), described the 5th isolated area (111), described the 3rd P+(121) and described the 6th isolated area (112), described the 2nd N+(118) right side and described the 2nd P+(119) left side between horizontal spacing can rationally regulate control according to different ESD design window demands,
Described the 2nd P+(119) across the surface element subregion with described sinking P doping (106) at described P trap (104), described the 2nd N+(118) left side and described the 2nd P+(119) right side between in the horizontal direction must reserved a certain fixed value interval, described the 2nd P+(119) right side be connected with the left side of described the 4th isolated area (110), the right side of described the 4th isolated area (110) and described the 3rd N+(120) left side be connected, described the 3rd N+(120) right side be connected with the left side of described the 5th isolated area (111), the right side of described the 5th isolated area (111) and described the 3rd P+(121) left side be connected, described the 3rd P+(121) right side be connected with the left side of described the 6th isolated area (112), the right side of described the 6th isolated area (112) and described the 4th P+(122) left side be connected,
Described the 4th N+(123) across the surface element subregion between described P trap (104) and described the 2nd N trap (105), described the 4th P+(122) and described the 4th N+(123) between in the horizontal direction must reserved a certain fixed value interval, described the 4th P+(122) right side and described the 4th N+(123) left side between horizontal spacing can rationally regulate control according to different ESD design window demands;
In described the 2nd N trap (105) surf zone, be from left to right provided with successively described the 7th isolated area (113), described the 5th P+(124), described the 8th isolated area (114) and described the 5th N+(125), described the 4th N+(123) and described the 5th P+(124) between be provided with described the 7th isolated area (113), described the 5th N+(125) and described P type substrate (101) right side edge between be provided with described the 9th isolated area (115), described the 4th N+(123) right side be connected with the left side of described seven isolated areas (113), the right side of described the 7th isolated area (113) and described the 5th P+(124) left side be connected, described the 5th P+(124) right side be connected with the left side of described the 8th isolated area (114), the right side of described the 8th isolated area (114) and described the 5th N+(125) left side be connected, described the 5th N+(125) right side be connected with the left side of described the 9th isolated area (115), the right side of described the 9th isolated area (115) is connected with the right side edge of P type substrate (101),
Described the first metal 1(126), described the second metal 1(127) respectively with a described N+(116), a described P+(117) be connected, described the first metal 2(132) with described the first metal 1(126) all with described the second metal 1(127) be connected, form the first metal anode of device, described five metals belongs to 1(130), described the 6th metal 1(131) respectively with described the 5th P+(124), described the 5th N+(125) be connected, described the 3rd metal 2(134) belong to 1(130 with described five metals) all with described the 6th metal 1(131) be connected, form the second metal anode of device,
Described the 3rd metal 1(128), described the 4th metal 1(129) respectively with described the 3rd N+(120), described the 3rd P+(121) be connected, described the second metal 2(133) with described the 3rd metal 1(128) all with described the 4th metal 1(129) be connected, form the metallic cathode of device.
2. the high pressure esd protection device of little time stagnant SCR structure of Zener breakdown as claimed in claim 1; it is characterized in that: described the first metal anode, a described N+(116), a described P+(117), a described N trap (103), described the 2nd N+(118), described the 2nd P+(119), described sinking P adulterate (106), described the 3rd N+(120), described the 3rd P+(121) and the described metallic cathode ESD current drain path that forms Article 1 Zener diode and trigger SCR, maintain voltage and secondary breakdown current with what improve device.
3. the high pressure esd protection device of little time stagnant SCR structure of Zener breakdown as claimed in claim 1; it is characterized in that: described the second metal anode, described the 5th N+(125), described the 5th P+(124), described the 2nd N trap (105), described the 4th N+(123), described the 4th P+(122), described sinking P adulterate (106), described the 3rd N+(120), described the 3rd P+(121) and the described metallic cathode ESD current drain path that forms Article 2 Zener diode and trigger SCR, maintain voltage and secondary breakdown current with what improve device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320799954.4U CN203659858U (en) | 2013-12-09 | 2013-12-09 | High-voltage ESD protective device of zener-zap small hysteresis SCR structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320799954.4U CN203659858U (en) | 2013-12-09 | 2013-12-09 | High-voltage ESD protective device of zener-zap small hysteresis SCR structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203659858U true CN203659858U (en) | 2014-06-18 |
Family
ID=50926217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320799954.4U Expired - Fee Related CN203659858U (en) | 2013-12-09 | 2013-12-09 | High-voltage ESD protective device of zener-zap small hysteresis SCR structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203659858U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103606548A (en) * | 2013-12-09 | 2014-02-26 | 江南大学 | Zener breakdown high-voltage ESD (Electronic Static Discharge) protective device with small-hysteresis SCR (Selective Catalytic Reduction) structure |
| CN104241277B (en) * | 2014-09-28 | 2017-10-13 | 江南大学 | A kind of SCR device that GDPMOS is embedded with high maintenance voltage |
-
2013
- 2013-12-09 CN CN201320799954.4U patent/CN203659858U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103606548A (en) * | 2013-12-09 | 2014-02-26 | 江南大学 | Zener breakdown high-voltage ESD (Electronic Static Discharge) protective device with small-hysteresis SCR (Selective Catalytic Reduction) structure |
| CN104241277B (en) * | 2014-09-28 | 2017-10-13 | 江南大学 | A kind of SCR device that GDPMOS is embedded with high maintenance voltage |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103606548B (en) | A kind of high-voltage ESD protective device of little time stagnant SCR structure of Zener breakdown | |
| CN103681660B (en) | A kind of high-voltage ESD protective device of annular LDMOS-SCR structure of dual latch-up | |
| US8232601B1 (en) | Transient voltage suppressors | |
| CN102290419B (en) | Transient voltage suppressor based on Zener diode | |
| CN102306649A (en) | Bidirectional dual-channel transient voltage suppressor (TVS) | |
| CN105428354A (en) | Electronic static discharge (ESD) protection device with bidirectional silicon controlled rectifier (SCR) structure embedded with interdigital N-channel metal oxide semiconductor (NMOS) | |
| CN102290417B (en) | Transient voltage suppressor based on DTSCR (Dual Triggered Silicon Controlled Rectifier) | |
| CN203659860U (en) | Doubly anti-latch-up type high-voltage ESD protection device of annular LDMOS-SCR structure | |
| CN105390491A (en) | LDMOS-SCR device with source-end embedded finger NMOS | |
| US9337158B2 (en) | Integrated circuit device and electrostatic discharge protection device thereof | |
| CN103354236A (en) | Silicon-controlled transient voltage inhibitor with embedded Zener diode structure | |
| CN103151350A (en) | Trigger circuit structure with integrated circuit power supply rail antistatic protection | |
| CN103715233B (en) | A kind of ESD protective device of the LDMOS structure with high maintenance voltage | |
| CN104347621A (en) | Electrostatic discharge protection method of chip with multiple power systems and multiple package types | |
| CN109166850A (en) | The diode triggered of Integrated circuit electrostatic protection is silicon-controlled | |
| CN203659858U (en) | High-voltage ESD protective device of zener-zap small hysteresis SCR structure | |
| CN108878417B (en) | Transient voltage suppressor with high-maintenance MOS auxiliary trigger SCR structure | |
| CN108807374A (en) | A kind of high-voltage bidirectional Transient Voltage Suppressor | |
| CN105428353B (en) | A kind of high-voltage ESD protective device with class fin LDMOS structure | |
| CN102569374B (en) | Silicon-controlled rectifier device embedded with Zener trigger structure | |
| CN104269401A (en) | Novel ESD protection device based on SCR structure | |
| CN103187416B (en) | Integrated circuit with element charging mode electrostatic discharge protection | |
| CN204792790U (en) | LVTSCR device with low strong robustness of trigger voltage | |
| CN203659859U (en) | ESD protective device of annular VDMOS structure with high-holding currents | |
| CN103617996A (en) | ESD protective device with high-holding-current annular VDMOS structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140618 Termination date: 20161209 |