CN203659838U - Heat radiation structure used for PoP packaging - Google Patents
Heat radiation structure used for PoP packaging Download PDFInfo
- Publication number
- CN203659838U CN203659838U CN201320681795.8U CN201320681795U CN203659838U CN 203659838 U CN203659838 U CN 203659838U CN 201320681795 U CN201320681795 U CN 201320681795U CN 203659838 U CN203659838 U CN 203659838U
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- Prior art keywords
- packaging body
- upper strata
- layer packaging
- encapsulation
- package substrate
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- Withdrawn - After Issue
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The utility model discloses a heat radiation structure used for PoP packaging. The structure comprises an upper layer packaging body, a lower layer packaging body, a BGA supporting ball, a BGA ball, a heat radiation cover, and a thermal interface material. The upper layer packaging body comprises an upper layer packaging substrate and a plurality of upper layer packaging heat conducting chips or devices stick or welded a plurality of thermal vias on the upper layer packaging substrate. The lower layer packaging body comprises a lower layer packaging substrate and a plurality of lower layer packaging heat conducting chips or devices stick or welded on the surface of the lower layer packaging substrate. The BGA supporting ball is between the upper layer packaging body and the lower layer packaging body, and realizes electric interconnection of the upper layer packaging body and the lower layer packaging body. The BGA ball is formed on the back surface of the lower layer packaging substrate of the lower layer packaging body, so as to support the upper layer packaging body and the lower layer packaging body. The heat radiation cover is covered on the upper layer packaging body, so as to realize heat radiation and shielding of the upper layer packaging heat conducting chips or devices of the upper layer packaging body. The thermal interface material is formed between the upper layer packaging heat conducting chips or devices of the upper layer packaging body and the heat radiation cover, so as to reduce contact thermal resistance of the upper layer packaging body and the heat radiation cover.
Description
Technical field
The utility model relates to internal memory and processor is integrated and radio frequency (Radio Frequency, RF) integrated stacked package (the Pacakge on Package of transmitting-receiving subassembly, PoP) technical field, especially a kind of radiator structure for PoP encapsulation.
Background technology
Fig. 1 is the schematic diagram of PoP encapsulating structure in prior art, and wherein 10 is upper strata encapsulating structure; 11 is ball grid array (Ball Grid Array, BGA) soldered ball; 20 is lower floor's encapsulating structure; 21 is conductive pole; 22 is packaging EMC material; 23 is PCB substrate; 30 is articulamentum; Articulamentum 30 is made up of solder layer 31, metal level 32 and tack coat 33.This PoP encapsulating structure is interconnected and is formed by BGA soldered ball 11 and articulamentum 30 by upper strata encapsulating structure 10 and lower floor's encapsulating structure 20.BGA soldered ball 11 plays the effect of electric interconnection, has the conductive pole 21 being electrically connected with BGA soldered ball 11 in the packaging EMC material 22 of lower floor's encapsulating structure 20.The effect of articulamentum 30 is to avoid stress to focus on the corner part of the junction of soldered ball and lower floor's encapsulating structure, stress dispersion is arrived to central part, thereby prevent the warpage of soldered ball.But, the heat radiation of upper strata encapsulation is a bottleneck, most of heat that upper strata packaged chip produces is through upper strata packaging body, BGA fulcrum ball, lower floor's packaging body, then conduct to substrate, external environment finally sheds, heat is not easy to shed, and affects packaging body junction temperature and raises, restriction stacked chips power and stacking quantity.General stacking packaging body quantity is no more than two.
Utility model content
(1) technical problem that will solve
In view of this, main purpose of the present utility model is to improve a kind of radiator structure for PoP encapsulation, to solve the heat dissipation problem of upper strata packaging body.
(2) technical scheme
For achieving the above object, the utility model provides a kind of radiator structure for PoP encapsulation, comprise: upper strata packaging body, comprises layer package substrate 100 and be attached to or be welded in multiple upper stratas encapsulation heat conduction chip or the device 201 on multiple thermal holes (thermal via) 101 in the upper layer package substrate 100 of upper strata packaging body; Lower floor's packaging body, comprises lower layer package substrate 300 and the multiple lower floors encapsulation heat conduction chip or the device 202 that are attached to or are welded in lower layer package substrate 300 surfaces; BGA fulcrum ball 400, is formed between upper strata packaging body and lower floor's packaging body, and the electricity of realizing upper and lower two-layer packaging body is interconnected, and supports upper strata packaging body; BGA ball 500, is formed at the back side of the lower layer package substrate 300 of lower floor's packaging body, to support upper and lower two-layer packaging body; Heat dissipating housing 700, is covered on the packaging body of upper strata, dispels the heat and shields with upper strata encapsulation heat conduction chip or the device 201 of realizing upper strata packaging body; And thermal interfacial material 600, be formed between the upper strata encapsulation heat conduction chip or device 201 and heat dissipating housing 700 of upper strata packaging body, to reduce the contact heat resistance between upper strata packaging body and heat dissipating housing.
In such scheme, described upper layer package substrate 100 comprises: multilayer large area Copper Foil 102; Multilayer dielectricity layer 103, is formed between multilayer large area Copper Foil 102; Multiple thermal holes 101, are distributed in the lower surface of multiple upper stratas encapsulation heat conduction chip or device 201, run through multilayer large area Copper Foil 102 and multilayer dielectricity layer 103, and in thermal hole 101, fill full copper; And multiple half via holes 104, be distributed in layer package substrate surface perimeter part, run through multilayer large area Copper Foil 102 and multilayer dielectricity layer 103, and in half via hole 104, fill full copper.
In such scheme, described large area Copper Foil 102 adopts thick copper, and thickness range is 12～36 μ m, and large area Copper Foil 102 and half via hole 104 interconnected, in half via hole 104, fill full copper, half via hole 104 is connected with heat dissipating housing 700.
In such scheme, described heat dissipating housing 700, as radome, adopts frivolous material, for example aluminium, allumen etc.
In such scheme, a part of heat that described upper strata encapsulation heat conduction chip or device 201 produce conducts on arbitrary layer of large area Copper Foil 102 through thermal hole 101, is then conducted to half via hole 104 of filling full copper, sheds finally by heat dissipating housing 700; Part heat is transmitted on heat dissipating housing 700 through the thermal interfacial material 600 of high heat conductance, then is transmitted in external environment condition; Some heat, successively through upper strata packaging body, BGA fulcrum ball 400, lower floor's packaging body and conduct to the pcb board under lower floor's packaging body, finally sheds to external environment.
In such scheme, the heat that described lower floor encapsulation heat conduction chip or device 202 produce the successively pcb board under lower floor's packaging body, BGA ball and lower floor's packaging body is transmitted in external environment condition.
(3) beneficial effect
The radiator structure for PoP encapsulation that the utility model provides, upper strata packaging body adopts the radiator structure of thermal hole+large area Copper Foil+half via hole+high thermal conductivity thermal interfacial material, a part of heat that upper strata encapsulation heat conduction chip or device 201 produce conducts on arbitrary layer of large area Copper Foil 102 through thermal hole 101, then conducted to half via hole 104 of filling full copper, shed finally by heat dissipating housing 700; Part heat is transmitted on heat dissipating housing 700 through the thermal interfacial material 600 of high heat conductance, then is transmitted in external environment condition; Some heat, successively through upper strata packaging body, BGA fulcrum ball 400, lower floor's packaging body and conduct to the pcb board under lower floor's packaging body, finally sheds to external environment, has effectively solved the heat dissipation problem of upper strata packaging body.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of PoP encapsulating structure in prior art;
Fig. 2 is the schematic diagram according to the radiator structure for PoP encapsulation of the utility model embodiment;
Fig. 3 to Fig. 9 is the process chart for the radiator structure of PoP encapsulation according to the making of the utility model embodiment; Wherein:
Fig. 3 is the structural representation according to the upper layer package substrate that contains large area Copper Foil, thermal hole and half via hole of the utility model embodiment;
Fig. 4 is the vertical view according to the upper layer package substrate that contains large area Copper Foil, thermal hole and half via hole of the utility model embodiment;
Fig. 5 is the structural representation that forms upper strata packaging body after upper layer package substrate paster according to the utility model embodiment;
Fig. 6 is the structural representation that forms lower floor's packaging body after lower layer package substrate paster according to the utility model embodiment;
Fig. 7 plants the structural representation after BGA ball according to the utility model embodiment at the upper layer package substrate back side;
Fig. 8 realizes the structural representation after interconnected according to the upper strata packaging body of the utility model embodiment and lower floor's packaging body;
Fig. 9 plants the structural representation after BGA ball according to the utility model embodiment at lower floor's packaging body substrate back.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the utility model is further described.
As shown in Figure 2, Fig. 2 is that the radiator structure that this is used for PoP encapsulation, comprising according to the schematic diagram of the radiator structure for PoP encapsulation of the utility model embodiment:
Upper strata packaging body, comprises layer package substrate 100 and is attached to or is welded in multiple upper stratas encapsulation heat conduction chip or the device 201 on multiple thermal holes 101 in the upper layer package substrate 100 of upper strata packaging body;
Lower floor's packaging body, comprises lower layer package substrate 300 and the multiple lower floors encapsulation heat conduction chip or the device 202 that are attached to or are welded in lower layer package substrate 300 surfaces;
BGA fulcrum ball 400, is formed between upper strata packaging body and lower floor's packaging body, and the electricity of realizing upper and lower two-layer packaging body is interconnected, and supports upper strata packaging body;
BGA ball 500, is formed at the back side of the lower layer package substrate 300 of lower floor's packaging body, to support upper and lower two-layer packaging body;
Thermal interfacial material 600, is formed between the upper strata encapsulation heat conduction chip or device 201 and heat dissipating housing 700 of upper strata packaging body, to reduce the contact heat resistance between upper strata packaging body and heat dissipating housing.
Wherein, upper layer package substrate 100 comprises: multilayer large area Copper Foil 102; Multilayer dielectricity layer 103, is formed between multilayer large area Copper Foil 102; Multiple thermal holes 101, are distributed in the lower surface of multiple upper stratas encapsulation heat conduction chip or device 201, run through multilayer large area Copper Foil 102 and multilayer dielectricity layer 103, and in thermal hole 101, fill full copper; And multiple half via holes 104, be distributed in layer package substrate surface perimeter part, run through multilayer large area Copper Foil 102 and multilayer dielectricity layer 103, and in half via hole 104, fill full copper.
Large area Copper Foil 102 adopts thick copper, and thickness range is that 12～36 μ m and large area Copper Foil 102 and half via hole 104 are interconnected, fills full copper in half via hole 104, and half via hole 104 is connected with heat dissipating housing 700.Heat dissipating housing 700, as radome, adopts frivolous material, for example aluminium, allumen etc.
A part of heat that upper strata encapsulation heat conduction chip or device 201 produce conducts on arbitrary layer of large area Copper Foil 102 through thermal hole 101, is then conducted to half via hole 104 of filling full copper, sheds finally by heat dissipating housing 700; Part heat is transmitted on heat dissipating housing 700 through the thermal interfacial material 600 of high heat conductance, then is transmitted in external environment condition; Some heat, successively through upper strata packaging body, BGA fulcrum ball 400, lower floor's packaging body and conduct to the pcb board under lower floor's packaging body, finally sheds to external environment.
The heat that lower floor's encapsulation heat conduction chip or device 202 produce the successively pcb board under lower floor's packaging body, BGA ball and lower floor's packaging body is transmitted in external environment condition.
Based on the radiator structure for PoP encapsulation shown in Fig. 2, Fig. 3 to Fig. 9 shows the process chart of the radiator structure encapsulating for PoP according to the making of the utility model embodiment, specifically comprises the following steps:
Step 1: layer package substrate 100 in making; Its manufacture method is first large area Copper Foil 102 and dielectric layer 103 successively crossing stack to be formed to substrate, then punching and fill copper at the mid portion of this substrate surface forms multiple thermal holes 101, and makes a call to half hole and fill copper in the surrounding of this substrate surface and form multiple half via holes 104; As shown in Figure 3 and Figure 4.
Step 2: multiple upper stratas encapsulation heat conduction chip or device 201 are attached to or are welded in upper layer package substrate 100 on multiple thermal holes 101, form upper strata packaging body; As shown in Figure 5.
Step 3: make upper strata packaging body; Multiple lower floors encapsulation heat conduction chip or device 202 are attached to or are welded on lower layer package substrate 300, form lower floor's packaging body; As shown in Figure 6.
Step 4: brush tin cream on upper layer package substrate 100 back side pads, steel mesh is planted BGA ball and refluxed, and forms BGA fulcrum ball 400, it is interconnected that wherein BGA fulcrum ball 400 is realized the electricity of upper and lower two-layer packaging body on the one hand, plays on the other hand the effect of supporting upper strata packaging body; As shown in Figure 7.
Step 5: brush solder(ing) paste on lower floor's packaging body 300 upper surface of base plate pads, after lower floor's encapsulation welding tray aligns with upper strata packaging body BGA fulcrum ball 400, backflow realizes upper strata packaging body and lower floor's packaging body is interconnected, thereby reaches the object of three-dimension packaging; As shown in Figure 8.
Step 6: brush tin cream on lower floor's packaging body 300 substrate back pads, steel mesh is planted BGA ball 500, backflow realizes lower floor's packaging body and plants ball; As shown in Figure 9.
Step 7: the object of dispelling the heat and shielding in order to realize upper strata encapsulation heat conduction chip or device 201, a heat dissipating housing 700 is set on packaging body top, upper strata, in order to reduce the contact heat resistance of upper strata packaging body and heat dissipating housing 700, between upper strata encapsulation heat conduction chip or device 201 and heat dissipating housing 700, be coated with one deck high thermal conductivity thermal interfacial material 600.The final radiator structure for PoP encapsulation forming as shown in Figure 2.
Above-described specific embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiment of the utility model; be not limited to the utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. for a radiator structure for PoP encapsulation, it is characterized in that, comprising:
Upper strata packaging body, comprises layer package substrate (100) and is attached to or is welded in multiple upper stratas encapsulation heat conduction chip or the device (201) on multiple thermal holes (101) in the upper layer package substrate (100) of upper strata packaging body;
Lower floor's packaging body, comprises lower layer package substrate (300) and is attached to or is welded in lower layer package substrate (300) surperficial multiple lower floors encapsulation heat conduction chip or device (202);
BGA fulcrum ball (400), is formed between upper strata packaging body and lower floor's packaging body, and the electricity of realizing upper and lower two-layer packaging body is interconnected, and supports upper strata packaging body;
BGA ball (500), is formed at the back side of the lower layer package substrate (300) of lower floor's packaging body, to support upper and lower two-layer packaging body;
Heat dissipating housing (700), is covered on the packaging body of upper strata, to realize upper strata encapsulation heat conduction chip or device (201) heat radiation and the shielding of upper strata packaging body; And
Thermal interfacial material (600), is formed between the upper strata encapsulation heat conduction chip or device (201) and heat dissipating housing (700) of upper strata packaging body, to reduce the contact heat resistance between upper strata packaging body and heat dissipating housing.
2. the radiator structure for PoP encapsulation according to claim 1, is characterized in that, described upper layer package substrate (100) comprising:
Multilayer large area Copper Foil (102);
Multilayer dielectricity layer (103), is formed between multilayer large area Copper Foil (102);
Multiple thermal holes (101), be distributed in the lower surface of multiple upper stratas encapsulation heat conduction chip or device (201), run through multilayer large area Copper Foil (102) and multilayer dielectricity layer (103), and in thermal hole (101), fill full copper; And
Multiple half via holes (104), are distributed in layer package substrate surface perimeter part, run through multilayer large area Copper Foil (102) and multilayer dielectricity layer (103), and in half via hole (104), fill full copper.
3. the radiator structure for PoP encapsulation according to claim 2, it is characterized in that, described large area Copper Foil (102) adopts thick copper, thickness range is 12～36 μ m, and large area Copper Foil (102) is interconnected with half via hole (104), in half via hole (104), fill full copper, half via hole (104) is connected with heat dissipating housing (700).
4. the radiator structure for PoP encapsulation according to claim 1, is characterized in that, described heat dissipating housing (700) is as radome, and the material of employing is aluminium or allumen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320681795.8U CN203659838U (en) | 2013-10-31 | 2013-10-31 | Heat radiation structure used for PoP packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320681795.8U CN203659838U (en) | 2013-10-31 | 2013-10-31 | Heat radiation structure used for PoP packaging |
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| CN203659838U true CN203659838U (en) | 2014-06-18 |
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| CN201320681795.8U Withdrawn - After Issue CN203659838U (en) | 2013-10-31 | 2013-10-31 | Heat radiation structure used for PoP packaging |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560117A (en) * | 2013-10-31 | 2014-02-05 | 中国科学院微电子研究所 | Heat dissipation structure for PoP encapsulation |
| CN108630615A (en) * | 2017-03-14 | 2018-10-09 | 联发科技股份有限公司 | Semiconductor package and board structure |
| US11171113B2 (en) | 2017-03-14 | 2021-11-09 | Mediatek Inc. | Semiconductor package structure having an annular frame with truncated corners |
| US11264337B2 (en) | 2017-03-14 | 2022-03-01 | Mediatek Inc. | Semiconductor package structure |
| US11362044B2 (en) | 2017-03-14 | 2022-06-14 | Mediatek Inc. | Semiconductor package structure |
| US11387176B2 (en) | 2017-03-14 | 2022-07-12 | Mediatek Inc. | Semiconductor package structure |
-
2013
- 2013-10-31 CN CN201320681795.8U patent/CN203659838U/en not_active Withdrawn - After Issue
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560117A (en) * | 2013-10-31 | 2014-02-05 | 中国科学院微电子研究所 | Heat dissipation structure for PoP encapsulation |
| CN103560117B (en) * | 2013-10-31 | 2016-09-14 | 中国科学院微电子研究所 | A kind of radiator structure for PoP encapsulation |
| CN108630615A (en) * | 2017-03-14 | 2018-10-09 | 联发科技股份有限公司 | Semiconductor package and board structure |
| US10784211B2 (en) | 2017-03-14 | 2020-09-22 | Mediatek Inc. | Semiconductor package structure |
| US11171113B2 (en) | 2017-03-14 | 2021-11-09 | Mediatek Inc. | Semiconductor package structure having an annular frame with truncated corners |
| US11264337B2 (en) | 2017-03-14 | 2022-03-01 | Mediatek Inc. | Semiconductor package structure |
| US11362044B2 (en) | 2017-03-14 | 2022-06-14 | Mediatek Inc. | Semiconductor package structure |
| US11387176B2 (en) | 2017-03-14 | 2022-07-12 | Mediatek Inc. | Semiconductor package structure |
| US11410936B2 (en) | 2017-03-14 | 2022-08-09 | Mediatek Inc. | Semiconductor package structure |
| US11646295B2 (en) | 2017-03-14 | 2023-05-09 | Mediatek Inc. | Semiconductor package structure having an annular frame with truncated corners |
| US11862578B2 (en) | 2017-03-14 | 2024-01-02 | Mediatek Inc. | Semiconductor package structure |
| US11942439B2 (en) | 2017-03-14 | 2024-03-26 | Mediatek Inc. | Semiconductor package structure |
| US11948895B2 (en) | 2017-03-14 | 2024-04-02 | Mediatek Inc. | Semiconductor package structure |
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