CN203608106U - Five-level inverter topological unit - Google Patents
Five-level inverter topological unit Download PDFInfo
- Publication number
- CN203608106U CN203608106U CN201320599165.6U CN201320599165U CN203608106U CN 203608106 U CN203608106 U CN 203608106U CN 201320599165 U CN201320599165 U CN 201320599165U CN 203608106 U CN203608106 U CN 203608106U
- Authority
- CN
- China
- Prior art keywords
- switching tube
- node
- connects
- switching
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model provides a five-level inverter topological unit. A first end of the a first switch tube is connected with a first node, and a second end of the first switch tube is connected with a sixth node; a first end of the second switch tube is connected with the sixth node, and a second end of the second switch tube is connected with a fifth node; a first end of the third switch tube is connected with a second node, and the third switch tube is connected with the sixth node through a fifth switch tube; a first end of a fourth switch tube is connected with a fourth node, and a second end of the fourth switch tube is connected with the sixth node through a sixth switch tube; a first end of a seventh switch tube is connected with the sixth node, a second end of the seventh switch tube is connected with an anode of a first diode, and a cathode of the first diode is connected with a third node; and a first end of an eighth switch tube is connected with the third node, a second end of the eighth switch tube is connected with an anode of a second diode, and a cathode of the second diode is connected with the sixth node. On the basis of three traditional levels, two levels are added to form the five-level topological unit, and reactive passages can be provided for all the levels.
Description
Technical field
The utility model relates to electric and electronic technical field, particularly a kind of five-electrical level inverter topology unit.
Background technology
At the new energy field such as solar power generation and wind power generation, power output is large, devices switch frequency is low, system equivalent switching frequency is high, output harmonic wave is little, dynamic response is fast because having for multi-electrical level inverter, transmission frequency bandwidth, Electro Magnetic Compatibility are good etc., and characteristic more and more comes into one's own.The more multi-level circuit of research is diode clamping formula multi-level circuit at present.Wherein diode clamping formula tri-level circuit and five level circuits successfully apply to photovoltaic DC-to-AC converter and fan converter field.
Five level circuits of the prior art, some level do not have idle path.
In the inverter topology that in prior art, publication number CN102918759 provides, when high level, electric current need to pass through two electronic switching devices, exists two switching devices to move moment simultaneously, has increased like this design difficulty and the loss of inverter.In the inverter topology that publication number DE102006010694 provides, level does not have idle path, in the time of zero crossing annex and idle operating state, need to switch to high level work, and the loss that increases system has also increased the harmonic content of inverter simultaneously.Therefore, those skilled in the art need to find five level topologys, and the idle path of any level both can be provided, and can not increase again switching tube and on-state loss in circuit, and relative cost can not increase.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of five-electrical level inverter topology unit, can provide idle path for all level, and can not increase switching tube and on-state loss in circuit, also can not increase cost.
The utility model provides a kind of five-electrical level inverter topology unit, comprising: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the first diode, the second diode;
The first end of described the first switching tube connects first node, and the second end of described the first switching tube connects the 6th node;
The first end of described second switch pipe connects described the 6th node, and the second end of described second switch pipe connects the 5th node;
The first end of described the 3rd switching tube connects Section Point, and described the 3rd switching tube connects described the 6th node by the 5th switching tube;
The first end of described the 4th switching tube connects the 4th node, and the second end of described the 4th switching tube connects described the 6th node by the 6th switching tube;
The first end of described the 7th switching tube connects the 6th node, and the second end of described the 7th switching tube connects the anode of described the first diode, and the negative electrode of described the first diode connects described the 3rd node;
The first end of described the 8th switching tube connects the 3rd node, and the second end of described the 8th switching tube connects the anode of the second diode, and the negative electrode of described the second diode connects described the 6th node;
Described Section Point is divided the voltage between first node and the 3rd node equally; Described the 4th node is divided the voltage between the 3rd node and the 5th node equally; Described the 3rd node is divided the voltage between first node and the 5th node equally.
Preferably, the driving signal logic complementation of described the first switching tube and the 5th switching tube;
The driving signal logic complementation of described the 3rd switching tube and the 7th switching tube;
The driving signal logic complementation of described the 8th switching tube and the 4th switching tube;
The driving signal logic complementation of described second switch pipe and the 6th switching tube.
Preferably, described the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube and diode of the equal inverse parallel of the 8th switching tube.
Preferably, the antiparallel diode of each switching tube is together with switching tube integration packaging.
Preferably, described switching tube is metal-oxide-semiconductor, IGBT pipe, IGCT pipe or IEGT pipe.
Preferably, this five level topology unit comprises five operation modes, is respectively:
The first operation mode: the first switching tube conducting, other switching tubes all turn-off;
The second operation mode: the 3rd switching tube and the 5th switching tube conducting, other switching tubes all turn-off;
The 3rd operation mode: the 7th switching tube and the 8th switching tube conducting, other switching tubes all turn-off;
The 4th operation mode: the 4th switching tube and the 6th switching tube conducting, other switching tubes all turn-off;
The 5th operation mode: the conducting of second switch pipe, other switching tubes all turn-off.
Compared with prior art, the utlity model has following advantage:
The five-electrical level inverter topology unit that the utility model provides, on the basis of traditional three-level inverter topology unit, increases by two level and forms novel five-electrical level inverter topology unit.Therefore, the inverter topology unit that the utility model provides can increase system phase voltage output state, reduces the current harmonic content of system, reduce the filter inductance of system, the electric pressure of raising system, the operational efficiency of elevator system, the hardware cost of reduction system.In the inverter topology that in prior art, publication number CN102918759 provides, when high level, electric current need to pass through two electronic switching devices, exists two switching devices to move moment simultaneously, has increased like this design difficulty and the loss of inverter.In the inverter topology that publication number DE102006010694 provides, level does not have idle path, in the time of zero crossing annex and idle operating state, need to switch to high level work, and the loss that increases system has also increased the harmonic content of inverter simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is five-electrical level inverter topology unit embodiment mono-schematic diagram that the utility model provides;
Fig. 2 is five-electrical level inverter topology unit embodiment bis-schematic diagrames that the utility model provides;
Fig. 2 a is a kind of DC power supply schematic diagram that the utility model provides;
Fig. 2 b is the another kind of DC power supply schematic diagram that the utility model provides;
Fig. 3 is first job mode schematic diagram;
Fig. 4 is second operation mode schematic diagram;
Fig. 5 is the 3rd operation mode schematic diagram;
Fig. 6 is the 4th operation mode schematic diagram;
Fig. 7 is the 5th operation mode schematic diagram.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.
Referring to Fig. 1, this figure is five-electrical level inverter topology unit embodiment mono-schematic diagram that the utility model provides.
The utility model provides a kind of five-electrical level inverter topology unit, comprising: the first switching tube S1, second switch pipe S2, the 3rd switching tube S3, the 4th switching tube S4, the 5th switching tube S5, the 6th switching tube S6, the 7th switching tube S7, the 8th switching tube S8, the first diode D1, the second diode D2;
The first end of described the first switching tube S1 connects first node A, and the second end of described the first switching tube S1 connects the 6th node F;
The first end of described second switch pipe S2 connects described the 6th node F, and the second end of described second switch pipe S2 connects the 5th node E;
The first end of described the 3rd switching tube S3 connects Section Point B, and described the 3rd switching tube S3 connects described the 6th node F by the 5th switching tube S5;
The first end of described the 4th switching tube S4 connects the 4th node D, and the second end of described the 4th switching tube S4 connects described the 6th node F by the 6th switching tube;
The first end of described the 7th switching tube S7 connects the 6th node F, and the second end of described the 7th switching tube S7 connects the anode of described the first diode D1, and the negative electrode of described the first diode D1 connects described the 3rd node C;
The first end of described the 8th switching tube S8 connects the 3rd node C, and the second end of described the 8th switching tube S8 connects the anode of the second diode D2, and the negative electrode of described the second diode D2 connects described the 6th node F.
It should be noted that, the two ends of the first capacitor C 1 connect respectively described first node A and Section Point B;
The two ends of the second capacitor C 2 connect respectively Section Point B and the 3rd node C;
The two ends of the 3rd capacitor C 3 connect respectively the 3rd node C and the 4th node D;
The two ends of the 4th capacitor C 4 connect respectively the 4th node D and the 5th node E.
Described Section Point B divides the voltage between first node A and the 3rd node C equally; Described the 4th node D divides the voltage between the 3rd node C and the 5th node E equally; Described the 3rd node C divides the voltage between first node A and the 5th node E equally.
Be understandable that, can utilize the electric capacity that capacitance is identical to be connected to the effect that between first node to the five nodes, realization is all pressed.As shown in Figure 1, the two ends of the first capacitor C 1 connect respectively A and B, and the two ends of the second capacitor C 2 connect respectively B and C, and the two ends of the 3rd capacitor C 3 connect respectively C and D, and the two ends of the 4th capacitor C 4 connect respectively D and E.
It should be noted that, capacitor C 1-C4, except the effect of all pressing, also has the effect of voltage stabilizing.
The five-electrical level inverter topology unit that the utility model provides, on the basis of traditional three-level inverter topology unit, increases by two level and forms novel five-electrical level inverter topology unit.Therefore, the inverter topology unit that the utility model provides can increase system phase voltage output state, reduces the current harmonic content of system, reduce the filter inductance of system, the electric pressure of raising system, the operational efficiency of elevator system, the hardware cost of reduction system.In the inverter topology that in prior art, publication number CN102918759 provides, when high level, electric current need to pass through two electronic switching devices, exists two switching devices to move moment simultaneously, has increased like this design difficulty and the loss of inverter.In the inverter topology that publication number DE102006010694 provides, level does not have idle path, in the time of zero crossing annex and idle operating state, need to switch to high level work, and the loss that increases system has also increased the harmonic content of inverter simultaneously.
Embodiment bis-:
Referring to Fig. 2, this figure is five-electrical level inverter topology unit embodiment bis-schematic diagrames that the utility model provides.
The five-electrical level inverter topology unit that the present embodiment provides comprises direct-current input power supplying 2E, E, N ,-E and 2E; Be that direct-current input power supplying comprises five level, be respectively 2e, e, 0 ,-e and-2e.
In this topology unit, also comprise inductance L and AC power Vac;
Wherein, after inductance L and AC power Vac series connection, be connected between the 3rd node C and the 6th node F.
Introduce below in conjunction with accompanying drawing two kinds of direct-current input power supplyings that the utility model provides.
Referring to Fig. 2 a, this figure is a kind of direct-current input power supplying schematic diagram that the utility model provides.
Thereby produce other two-way level by two-way input DC power by two-way DC-DC circuit and form five level.
As shown in Figure 2 a, the DC power supply of PV output is by two-way DC-DC(DC-DC1 and DC-DC2) five level of generation;
In this topology unit, the voltage on C1 is e, and the voltage on C3 is 2e; In like manner, the voltage on C2 is-e that the voltage on C4 is-2e.
Referring to Fig. 2 b, this figure is a kind of direct-current input power supplying schematic diagram that the utility model provides.
The direct-current input power supplying providing in the present embodiment by four DC source (being respectively DC1, DC2, DC3 and DC4) form five level 2e, e, 0 ,-e and-2e.
It should be noted that, the voltage that DC1, DC2, DC3 and DC4 provide all equates.
It should be noted that the driving signal logic complementation of described the first switching tube S1 and the 5th switching tube S5;
The driving signal logic complementation of described the 3rd switching tube S3 and the 7th switching tube S7;
The driving signal logic complementation of described the 8th switching tube S8 and the 4th switching tube S4;
The driving signal logic complementation of described second switch pipe S2 and the 6th switching tube S6.
Described the first switching tube S1, second switch pipe S2, the 3rd switching tube S3, the 4th switching tube S4, the 5th switching tube S5, the 6th switching tube S6, the 7th switching tube S7 and diode of the equal inverse parallel of the 8th switching tube S8.
The antiparallel diode of each switching tube is together with switching tube integration packaging.
Described switching tube is metal-oxide-semiconductor, IGBT pipe, IGCT pipe or IEGT pipe.
It should be noted that, the five-electrical level inverter topology unit that the utility model embodiment provides comprises five operation modes, and this five level topology unit comprises five operation modes, is respectively:
The first operation mode: the first switching tube conducting, other switching tubes all turn-off;
The second operation mode: the 3rd switching tube and the 5th switching tube conducting, other switching tubes all turn-off;
The 3rd operation mode: the 7th switching tube and the 8th switching tube conducting, other switching tubes all turn-off;
The 4th operation mode: the 4th switching tube and the 6th switching tube conducting, other switching tubes all turn-off;
The 5th operation mode: the conducting of second switch pipe, other switching tubes all turn-off.
Below in conjunction with accompanying drawing, these five operation modes are introduced respectively.
Referring to Fig. 3, this figure is first job mode schematic diagram.
The first operation mode: the first switching tube S1 conducting, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with shallow solid line in the drawings, and the path of conducting illustrates with dark solid line.
Current path is C2 → C1 → S1 → L → Vac.
Referring to Fig. 4, this figure is second operation mode schematic diagram.
The second operation mode: the 3rd switching tube S3, the 5th switching tube S5 conducting, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with shallow solid line in the drawings, and the path of conducting illustrates with dark solid line.
Current path is C2 → S3 → S5 → L → Vac.
Referring to Fig. 5, this figure is the 3rd operation mode schematic diagram.
The 3rd operation mode: the 7th switching tube S7, the 8th switching tube S8 conducting, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with shallow solid line in the drawings, and the path of conducting illustrates with dark solid line.
Current path is S7 → D1 → Vac → L; Or S8 → D2 → L → Vac;
Referring to Fig. 6, this figure is the 4th operation mode schematic diagram.
The 4th operation mode: the 4th switching tube S4, the 6th switching tube S6 conducting, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with shallow solid line in the drawings, and the path of conducting illustrates with dark solid line.
Current path is C3 → S4 → S6 → L → Vac.
Referring to Fig. 7, this figure is the 5th operation mode schematic diagram.
The 5th operation mode: second switch pipe S2 conducting, rest switch pipe all ends;
Wherein, the path of not conducting illustrates with shallow solid line in the drawings, and the path of conducting illustrates with dark solid line.
Current path is C3 → C4 → S2 → L → Vac.
Current direction in above operation mode is all two-way.
The above, be only preferred embodiment of the present utility model, not the utility model done to any pro forma restriction.Although the utility model discloses as above with preferred embodiment, but not in order to limit the utility model.Any those of ordinary skill in the art, do not departing from technical solutions of the utility model scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solutions of the utility model, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solutions of the utility model,, all still belongs in the scope of technical solutions of the utility model protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present utility model.
Claims (6)
1. a five-electrical level inverter topology unit, it is characterized in that, comprising: the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the first diode, the second diode;
The first end of described the first switching tube connects first node, and the second end of described the first switching tube connects the 6th node;
The first end of described second switch pipe connects described the 6th node, and the second end of described second switch pipe connects the 5th node;
The first end of described the 3rd switching tube connects Section Point, and described the 3rd switching tube connects described the 6th node by the 5th switching tube;
The first end of described the 4th switching tube connects the 4th node, and the second end of described the 4th switching tube connects described the 6th node by the 6th switching tube;
The first end of described the 7th switching tube connects the 6th node, and the second end of described the 7th switching tube connects the anode of described the first diode, and the negative electrode of described the first diode connects the 3rd node;
The first end of described the 8th switching tube connects described the 3rd node, and the second end of described the 8th switching tube connects the anode of the second diode, and the negative electrode of described the second diode connects described the 6th node;
Described Section Point is divided the voltage between first node and the 3rd node equally; Described the 4th node is divided the voltage between the 3rd node and the 5th node equally; Described the 3rd node is divided the voltage between first node and the 5th node equally.
2. five-electrical level inverter topology unit according to claim 1, is characterized in that, the driving signal logic complementation of described the first switching tube and the 5th switching tube;
The driving signal logic complementation of described the 3rd switching tube and the 7th switching tube;
The driving signal logic complementation of described the 8th switching tube and the 4th switching tube;
The driving signal logic complementation of described second switch pipe and the 6th switching tube.
3. five-electrical level inverter topology unit according to claim 1, it is characterized in that described the first switching tube, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube and diode of the equal inverse parallel of the 8th switching tube.
4. five-electrical level inverter topology unit according to claim 3, is characterized in that, the antiparallel diode of each switching tube is together with switching tube integration packaging.
5. according to the five-electrical level inverter topology unit described in claim 1-4 any one, it is characterized in that, described switching tube is metal-oxide-semiconductor, IGBT pipe, IGCT pipe or IEGT pipe.
6. five-electrical level inverter topology unit according to claim 1, is characterized in that, this five level topology unit comprises five operation modes, is respectively:
The first operation mode: the first switching tube conducting, other switching tubes all turn-off;
The second operation mode: the 3rd switching tube and the 5th switching tube conducting, other switching tubes all turn-off;
The 3rd operation mode: the 7th switching tube and the 8th switching tube conducting, other switching tubes all turn-off;
The 4th operation mode: the 4th switching tube and the 6th switching tube conducting, other switching tubes all turn-off;
The 5th operation mode: the conducting of second switch pipe, other switching tubes all turn-off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320599165.6U CN203608106U (en) | 2013-09-26 | 2013-09-26 | Five-level inverter topological unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320599165.6U CN203608106U (en) | 2013-09-26 | 2013-09-26 | Five-level inverter topological unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203608106U true CN203608106U (en) | 2014-05-21 |
Family
ID=50720763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320599165.6U Expired - Lifetime CN203608106U (en) | 2013-09-26 | 2013-09-26 | Five-level inverter topological unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203608106U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108988672A (en) * | 2018-07-27 | 2018-12-11 | 东北大学 | A kind of six level circuit topological structures for power conversion system |
-
2013
- 2013-09-26 CN CN201320599165.6U patent/CN203608106U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108988672A (en) * | 2018-07-27 | 2018-12-11 | 东北大学 | A kind of six level circuit topological structures for power conversion system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101860192B (en) | Three-state three-level PFC circuit and multi-state three-level PFC circuit | |
| CN104218832A (en) | Single-phase five-level topology and inverter | |
| CN106301042B (en) | A kind of seven electrical level inverters | |
| CN103532420B (en) | Dual-three-level online-topology switchable inverter | |
| CN206272519U (en) | A kind of multi-electrical level inverter | |
| CN103051233A (en) | Non-isolated single-phase photovoltaic grid-connected inverter and on-off control timing sequence thereof | |
| CN102843056A (en) | Single-phase five-level inverter | |
| CN103490656A (en) | Four-level inverter topological structure based on H-bridge and carrier modulation method thereof | |
| CN106911260A (en) | A kind of control method of multi-electrical level inverter, device and inverter | |
| CN203327305U (en) | Bridge-free PFC plus T type three-level inversion frequency-conversion light modulator | |
| CN103236796B (en) | A kind of method of inverter and control inverter | |
| CN102710133B (en) | Seven-level circuit, a grid-connected inverter and modulation method and device of seven-level circuit | |
| CN204046460U (en) | A kind of novel Modularized multi-level converter sub-module topology | |
| CN103888010A (en) | High-frequency isolated type three-level inverter based on push-pull converter | |
| CN103051231A (en) | Three-phase five-level inverter | |
| CN102403920B (en) | Three-level half-bridge photovoltaic grid connected inverter | |
| CN102427312A (en) | Single-phase inverter | |
| CN108631639A (en) | Two-way DC-AC translation circuits for energy storage inverter | |
| CN102843054B (en) | Single-phase five-level inverter | |
| CN104682762A (en) | Low-leakage-current grid-connected inverter | |
| CN103107698A (en) | Multi-level active network boost converter | |
| CN102437761A (en) | Single-phase full bridge three-level inverter and three-phase three-level inverter | |
| CN203608106U (en) | Five-level inverter topological unit | |
| CN203119788U (en) | Three-level inversion unit and photovoltaic inverter | |
| CN202334357U (en) | Three-level half-bridge photovoltaic grid-connected inverter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140521 |
|
| CX01 | Expiry of patent term |