CN102437761A - Single-phase full bridge three-level inverter and three-phase three-level inverter - Google Patents
Single-phase full bridge three-level inverter and three-phase three-level inverter Download PDFInfo
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- CN102437761A CN102437761A CN2011103265674A CN201110326567A CN102437761A CN 102437761 A CN102437761 A CN 102437761A CN 2011103265674 A CN2011103265674 A CN 2011103265674A CN 201110326567 A CN201110326567 A CN 201110326567A CN 102437761 A CN102437761 A CN 102437761A
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Abstract
The invention discloses a single-phase full bridge three-level inverter and a three-phase three-level inverter. The three-phase three-level inverter comprises a three-phase topology unit, wherein, each phase of topology unit is a random topology unit in the following units: a first topology unit comprising four switch devices, wherein, a first switch device, a second switch device and a fourth switch device are in series connection with a direct current power supply, a second terminal of a third switch device is connected with a partial pressure middle point of the direct current power supply, and a first terminal of the third switch device is connected with a second terminal of the first switch and a first terminal of the second switch device; a second topology unit comprising four switch devices, wherein, a first switch device, a third switch device and a fourth switch device are in series connection with the direct current power supply, a first terminal of a second switch device is connected with the partial pressure middle point of the direct current power supply, a second terminal of the second switch device is connected with a second terminal of the third switch device and a first terminal of the fourth switch device. By utilizing the single-phase full bridge three-level inverter and the three-phase three-level inverter in the invention, loss can be reduced, and conversion efficiency can be raised.
Description
Technical field
The present invention relates to the voltage transitions technical field, be specifically related to a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter.
Background technology
Inverter is meant the effect that turns on and off through semiconductor power switch device, direct current energy is converted into a kind of converter of AC energy.In recent years, three-level inverter has obtained in high-power ac motor speed control by variable frequency field using widely owing to have advantages such as output capacity is big, output voltage is high, current harmonic content is little.
Owing to receive power device capacity, neutral line current, the requirement of electrical network load balance and with the restriction of the character of electric loading (like three-phase AC asynchronous motor etc.), the single-phase inverter capacity is generally lower, jumbo inverter adopts the three-phase form more.
Each phase topology unit of existing three-phase tri-level inverter topology mainly contains two types, is respectively: " 1 " font topological structure and " T " font topological structure.
As shown in Figure 1, be the sketch map of " 1 " font topological structure in the prior art.
In this " 1 " font topological structure, the electric capacity (being the capacitor C 1 and capacitor C 2 among Fig. 1) that equates through two capacitive reactances of series connection between direct current positive and negative busbar voltage obtains three level: positive bus-bar level, two capacitances in series contact level, negative busbar level.A binding post of single-phase semi-bridge inversion device interchange output is drawn from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is following:
When semiconductor switch pipe T1, T2 conducting, semiconductor switch pipe T3, T4, diode D3, D4, D5, D6 by the time, the level of output node a equals the positive bus-bar level.When the outlet side electric current flowed out to inductance L 1 from a point, diode D1, D2 ended, and current circuit is T1-T2-L1-V
G-L2-C1-T1; When the outlet side electric current flows to a point from L1, diode D1, D2 conducting, current circuit is D2-D1-C1-L2-V
G-L1-D2.
When semiconductor switch pipe T2, T3 conducting, semiconductor switch pipe T1, T4, diode D1, D2, D3, D4 by the time, the level of output node a equals two capacitances in series contact level.When the outlet side electric current flows out to L1 from a point, diode D5 conducting, diode D6 ends, and current circuit is D5-T2-L1-V
G-L2-D5; When the outlet side electric current flows to a point from L1, diode D6 conducting, diode D5 ends, and current circuit is T3-D6-L2-V
G-L1-T3.
When semiconductor switch pipe T3, T4 conducting, semiconductor switch pipe T1, T2, diode D1, D2, D5, D6 by the time, the level of output node a equals the negative busbar level.When the outlet side electric current flows out to L1 from a point, diode D3, D4 conducting, current circuit is D4-D3-L1-V
G-L2-C2-D4; When the outlet side electric current flow to a point from L1, diode D3, D4 ended, and current circuit is T3-T4-C2-L2-V
G-L1-T3.
Can know by the above-mentioned course of work; Four groups of semiconductor switch pipes (T1 and D1 of " 1 " font three-level inverter; T2 and D2, T3 and D3, T4 and D4) maximum voltage that bears is the half the of the total input voltage of direct current; Therefore, can select the less semiconductor switch pipe of rated voltage and then reduce its switching loss.But in this topology, need two clamping diode D5, D6, increased device number and its loss, also increased the on-state loss of semiconductor switch pipe T2, T3 simultaneously.
As shown in Figure 2, be the sketch map of " T " font topological structure in the prior art.
In this " T " font topological structure; The electric capacity (being the capacitor C 1 and capacitor C 2 among Fig. 2) that equates through two capacitive reactances of series connection between direct current positive and negative busbar voltage obtains three level: the positive bus-bar level; Two capacitances in series contact level; The negative busbar level, a binding post of single-phase semi-bridge inversion device interchange output is drawn from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is following:
When semiconductor switch pipe T1, T2 conducting, semiconductor switch pipe T3, T4, D2, D3, D4 by the time, the level of output node a equals the positive bus-bar level.When the outlet side electric current flowed out to inductance L 1 from a point, diode D1 ended, and current circuit is T1-L1-V
G-L2-C1-T1; When the outlet side electric current flows to a point from inductance L 1, diode D1 conducting, current circuit is D1-C1-L2-V
G-L1-D1.
When semiconductor switch pipe T2, T3 conducting, semiconductor switch pipe T1, T4, D1, D4 by the time, the level of output node a equals two capacitances in series contact level.When the outlet side electric current flows out to inductance L 1 from a point, diode D3 conducting, diode D2 ends, and current circuit is T2-D3-L1-V
G-L2-T2; When the outlet side electric current flows to a point from inductance L 1, diode D2 conducting, diode D3 ends, and current circuit is T3-D2-L2-V
G-L1-T3.
When semiconductor switch pipe T3, T4 conducting, semiconductor switch pipe T1, T2, D1, D2, D3 by the time, the level of output node a equals the negative busbar level.When the outlet side electric current flows out to inductance L 1 from a point, diode D4 conducting, current circuit is D4-L1-V
G-L2-C2-D4; When the outlet side electric current flow to a point from inductance L 1, diode D4 ended, and current circuit is T4-C2-L2-V
G-L1-T4.
Can be known that by the above-mentioned course of work maximum voltage that T1, T4 bear in four groups of semiconductor switch pipes of " T " font three-level inverter is the total input voltage of direct current, the maximum voltage that T2, T3 bear is the total input voltage of half direct current.Therefore, increase the switching loss of semiconductor switch pipe T1, T4, but need not two clamping diodes, avoided this part loss.
Summary of the invention
The embodiment of the invention provides a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter to the problem that above-mentioned prior art exists, and to reduce loss, improves energy conversion efficiency.
For this reason, the embodiment of the invention provides following technical scheme:
A kind of single-phase full bridge three-level inverter is used for converting the direct current of DC power supply output to alternating current, comprising: two brachium pontis, and said two brachium pontis are connected between the said DC power supply, and each brachium pontis comprises following any topology unit respectively:
First topology unit; Comprise: four switching devices; First switching device wherein, second switch device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; Second end of the 3rd switching device connects the dividing potential drop mid point of said DC power supply, and first end of the 3rd switching device connects second end of first switching device and first end of second switch device; Second end of second switch device links to each other with first end of the 4th switching device and as an output of said inverter;
Second topology unit; Comprise: four switching devices; First switching device wherein, the 3rd switching device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; First end of second switch device connects the dividing potential drop mid point of said DC power supply, and second end of second switch device connects second end of the 3rd switching device and first end of the 4th switching device; Second end of first switching device links to each other with first end of the 3rd switching device and as an output of said inverter.
Preferably, each switching device includes: switching tube and with the antiparallel diode of said switching tube.
Preferably, the drive signal of four switching devices in said first topology unit or second topology unit is handed over to cut by sinusoidal modulation wave and triangular carrier and is produced, and:
At the positive half period of said sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-off, and if the level of said triangular carrier less than the level of said sinusoidal modulation wave, the then first switching device conducting, the 3rd switching device turn-offs; If the level of said triangular carrier is greater than the level of said sinusoidal modulation wave, then first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at said sinusoidal modulation wave; First switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of said triangular carrier greater than said sinusoidal modulation wave the level after reverse; Second switch break-over of device then, the 4th switching device turn-offs; If the level of said triangular carrier is the level after reverse less than said sinusoidal modulation wave, then the second switch device turn-offs, the 4th switching device conducting.
Preferably, said single-phase full bridge three-level inverter also comprises:
Two dividing potential drop electric capacity are connected in series between the said DC power supply, are used for said DC power supply is carried out dividing potential drop, and the tie point of said two dividing potential drop electric capacity is the dividing potential drop mid point of said DC power supply.
Preferably, said single-phase full bridge three-level inverter also comprises:
Filter circuit is connected between the output of said two brachium pontis, is used for the high fdrequency component of the said inverter output of filtering signal.
A kind of three-phase tri-level inverter; Be used for converting the direct current of DC power supply output to alternating current; Comprise: the three-phase topology unit, each the phase topology unit in the said three-phase topology unit is connected between the said DC power supply, and is following any topology unit:
First topology unit; Comprise: four switching devices; First switching device wherein, second switch device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; Second end of the 3rd switching device connects the dividing potential drop mid point of said DC power supply, and first end of the 3rd switching device connects second end of first switching device and first end of second switch device; Second end of second switch device links to each other with first end of the 4th switching device and as an output of said inverter;
Second topology unit; Comprise: four switching devices; First switching device wherein, the 3rd switching device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; First end of second switch device connects the dividing potential drop mid point of said DC power supply, and second end of second switch device connects second end of the 3rd switching device and first end of the 4th switching device; Second end of first switching device links to each other with first end of the 3rd switching device and as an output of said inverter.
Preferably, each switching device includes: switching tube and with the antiparallel diode of said switching tube.
Preferably, the drive signal of four switching devices in said first topology unit or second topology unit is cut generation by sinusoidal wave the friendship with triangular carrier, and:
At the positive half period of said sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-off, and if the level of said triangular carrier less than the level of said sinusoidal modulation wave, the then first switching device conducting, the 3rd switching device turn-offs; If the level of said triangular carrier is greater than the level of said sinusoidal modulation wave, then first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at said sinusoidal modulation wave; First switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of said triangular carrier greater than said sinusoidal modulation wave the level after reverse; Second switch break-over of device then, the 4th switching device turn-offs; If the level of said triangular carrier is the level after reverse less than said sinusoidal modulation wave, then the second switch device turn-offs, the 4th switching device conducting.
Alternatively, said inverter is the three-phase three-wire system three-level inverter, perhaps the three-phase four-wire system three-level inverter.
Preferably, said three-phase tri-level inverter also comprises:
Two dividing potential drop electric capacity are connected in series between the said DC power supply, are used for said DC power supply is carried out dividing potential drop, and the tie point of said two dividing potential drop electric capacity is the dividing potential drop mid point of said DC power supply.
Preferably, said three-phase tri-level inverter also comprises:
Filter circuit is connected between the output of said three-phase topology unit, is used for the high fdrequency component of the said inverter output of filtering signal.
A kind of single-phase full bridge three-level inverter that the embodiment of the invention provides and a kind of three-phase tri-level inverter; Can be when the device count that keeps three-level inverter be minimum; Reduce the voltage stress of part switching tube; Thereby can select small-power semiconductor switch pipe for use, reduce loss, improve conversion efficiency.
Description of drawings
In order to be illustrated more clearly in the application embodiment or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use among the embodiment below; Obviously; The accompanying drawing that describes below only is some embodiment that put down in writing among the present invention, for those of ordinary skills, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is each phase " 1 " font topological structure sketch map of three-phase tri-level inverter topology in the prior art;
Fig. 2 is each phase " T " font topological structure sketch map of three-phase tri-level inverter topology in the prior art;
Fig. 3 is the structural representation of first topology unit in the embodiment of the invention;
Fig. 4 is the structural representation of second topology unit in the embodiment of the invention;
Fig. 5, Fig. 6, Fig. 7 are respectively a kind of structural representations of embodiment of the invention single-phase full bridge three-level inverter;
Fig. 8, Fig. 9, Figure 10, Figure 11 are respectively a kind of structural representations of embodiment of the invention three-phase three-wire system three-level inverter;
Figure 12, Figure 13, Figure 14, Figure 15 are respectively a kind of structural representations of embodiment of the invention three-phase four-wire system three-level inverter;
Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are respectively the another kind of structural representations of embodiment of the invention three-phase four-wire system three-level inverter;
Figure 21 is the drive signal sketch map of each switching device in the embodiment of the invention;
Figure 22 is the current circuit sketch map of first topology unit under first operation mode in the embodiment of the invention;
Figure 23 is the current circuit sketch map of first topology unit under second operation mode in the embodiment of the invention;
Figure 24 is the current circuit sketch map of first topology unit under the 3rd operation mode in the embodiment of the invention.
Figure 25 is the current circuit sketch map of second topology unit under first operation mode in the embodiment of the invention;
Figure 26 is the current circuit sketch map of second topology unit under second operation mode in the embodiment of the invention;
Figure 27 is the current circuit sketch map of second topology unit under the 3rd operation mode in the embodiment of the invention.
Embodiment
In order to make those skilled in the art person understand the scheme of the embodiment of the invention better, the embodiment of the invention is done further to specify below in conjunction with accompanying drawing and execution mode.
The embodiment of the invention provides a kind of single-phase full bridge three-level inverter and a kind of three-phase tri-level inverter, is used for converting the direct current of DC power supply output to alternating current, and said DC power supply can be that photo-voltaic power supply 0 also can be an energy-storage battery.
In this single-phase full bridge three-level inverter, comprise: two brachium pontis, said two brachium pontis are connected between the said DC power supply, and each brachium pontis comprises following any topology unit respectively: first topology unit, second topology unit.
Equally; In this three-phase tri-level inverter, comprise: the three-phase topology unit; Each phase topology unit in the said three-phase topology unit is connected between the said DC power supply, and is following any topology unit: first topology unit, second topology unit.
Need to prove that the three-phase tri-level inverter of the embodiment of the invention can be the three-phase three-wire system three-level inverter, also can be the three-phase four-wire system three-level inverter.
Owing in said single-phase full bridge three-level inverter and said three-phase tri-level inverter, include above-mentioned first topology unit and/or second topology unit, therefore, at first these two topology unit be elaborated below.
For convenience, abbreviate above-mentioned first topology unit as M1, second topology unit abbreviates M2 as.
As shown in Figure 3, be a kind of structural representation and the corresponding simplified block diagram thereof of first topology unit in the embodiment of the invention.
This first topology unit comprises: four switching devices; First switching device wherein, second switch device and the 4th switching device are connected in series between the said DC power supply; Wherein, First end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; Second end of the 3rd switching device connects the dividing potential drop mid point of said DC power supply, and first end of the 3rd switching device connects second end of first switching device and first end of second switch device; Second end of second switch device links to each other with first end of the 4th switching device and as an output of said inverter.
As shown in Figure 4, be a kind of structural representation and the corresponding simplified block diagram thereof of second topology unit in the embodiment of the invention.
This second topology unit comprises: four switching devices; First switching device wherein, the 3rd switching device and the 4th switching device are connected in series between the said DC power supply; Wherein, First end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; First end of second switch device connects the dividing potential drop mid point of said DC power supply, and second end of second switch device connects second end of the 3rd switching device and first end of the 4th switching device; Second end of first switching device links to each other with first end of the 3rd switching device and as an output of said inverter.
Need to prove that in practical application, the dividing potential drop mid point of above-mentioned DC power supply can be formed by two dividing potential drop electric capacity that are connected in series between the said DC power supply, the tie point of promptly said two dividing potential drop electric capacity is the dividing potential drop mid point of said DC power supply.
Each switching device among above-mentioned Fig. 3 and Fig. 4 comprises: switching tube and with the antiparallel diode of said switching tube; Said switching tube can be the semiconductor switch pipe, such as MOSFET (high voltage metal oxide silicon field effect transistor), IGBT (igbt), IGCT (integrated gate commutated thyristor), IEGT (strengthening the injection grid transistor) etc.Said diode can be the inverse parallel diode that separate diode or said switching tube inside carry.Correspondingly, the drain electrode of said switching tube or collector electrode link to each other with the negative electrode of said diode and constitute first end of said switching device, and the source electrode of said switching tube or emitter link to each other with the anode of said diode and constitute second end of said switching device.Certainly, the embodiment of the invention does not limit the type of above-mentioned switching tube, can also be the switching tube of other type.
Like Fig. 3 and shown in Figure 4; First switching device is made up of first switch transistor T 1 and the first diode D1; The second switch device is made up of the second switch pipe T2 and the second diode D2; The 3rd switching device is made up of the 3rd switch transistor T 3 and the 3rd diode D3, and the 4th switching device is made up of the 4th switch transistor T 4 and the 4th diode D4.
Based on the above-mentioned first topology unit M1 and the second topology unit M2, the single-phase full bridge three-level inverter that the embodiment of the invention provides can have the various deformation structure.
Fig. 5, Fig. 6, Fig. 7 are respectively a kind of structural representations of embodiment of the invention single-phase full bridge three-level inverter.
As shown in Figure 5, two dividing potential drop capacitor C 1, C2 are connected in series between the DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 1, C2 is identical, is used for said DC power supply is carried out dividing potential drop; Two brachium pontis are the first topology unit M1, and these two first topology unit are connected between the said DC power supply.
In this embodiment, said single-phase full bridge three-level inverter also can further comprise: be connected the filter circuit between the output of said two brachium pontis, be used for the high fdrequency component of the said inverter output of filtering signal.This filter circuit can be the L type, LC type, LCL type etc.As shown in Figure 5, in this embodiment, said filter circuit comprises: respectively with output and the AC load or the electrical network V of one of them brachium pontis
GThe inductance L 1 that links to each other is respectively with output and the AC load or the electrical network V of another brachium pontis
GThe inductance L 2 that links to each other is connected the filter capacitor C at AC load or electrical network two ends.
Fig. 6 and single-phase full bridge three-level inverter shown in Figure 7 and Fig. 5 are similar, and just two brachium pontis among Fig. 6 are respectively the first topology unit M1 and the second topology unit M2, and two brachium pontis among Fig. 7 are the second topology unit M2.
Fig. 8, Fig. 9, Figure 10, Figure 11 are respectively a kind of structural representations of embodiment of the invention three-phase three-wire system three-level inverter.
As shown in Figure 8, two dividing potential drop capacitor C 11, C12 are connected in series between the DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 11, C12 is identical, is used for DC power supply is carried out dividing potential drop; The three-phase topology unit is the first topology unit M1, is connected between the said DC power supply.
In this embodiment, said three-phase three-wire system three-level inverter also can further comprise: be connected the filter circuit between the output of said three-phase topology unit, be used for the high fdrequency component of the said inverter output of filtering signal.This filter circuit can be the L type, LC type, LCL type etc.As shown in Figure 8; In this embodiment; Said filter circuit comprises: the one group of LC mode filter that links to each other with the output of every topology unit mutually; As shown in Figure 8, with first inductance L 1 that links to each other of the output of topology unit and the capacitor C 1 that links to each other with inductance L 1 mutually, with second mutually the inductance L 2 that links to each other of the output of topology unit reach the capacitor C 2 that links to each other with inductance L 2; The inductance L that links to each other with the output of third phase topology unit 3 and capacitor C 3, three capacitor C 1, C2, C3 of linking to each other with inductance L 3 and the other end outside inductance links to each other interconnect.
Fig. 9, Figure 10, three-phase three-wire system three-level inverter shown in Figure 11 and Fig. 8 are similar, and just the three-phase topology unit among Fig. 9 is respectively the first topology unit M1, the first topology unit M1 and the second topology unit M2; Three-phase topology unit among Figure 10 is respectively the first topology unit M1, the second topology unit M2 and the second topology unit M2; Three-phase topology unit among Figure 11 is the second topology unit M2.
Need to prove that the three-phase phase-sequence of each the three-phase three-wire system three-level inverter output shown in above-mentioned Fig. 8 to Figure 11 can be arbitrarily, and this embodiment of the invention is not done qualification.
Figure 12, Figure 13, Figure 14, Figure 15 are respectively a kind of structural representations of embodiment of the invention three-phase four-wire system three-level inverter.
Shown in figure 12, two dividing potential drop capacitor C 11, C12 are connected in series between the DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 11, C12 is identical, is used for DC power supply is carried out dividing potential drop; The three-phase topology unit is the first topology unit M1, is connected between the said DC power supply.
In this embodiment, said three-phase four-wire system three-level inverter also can further comprise: be connected the filter circuit between the output of said three-phase topology unit, be used for the high fdrequency component of the said inverter output of filtering signal.This filter circuit can be the L type, LC type, LCL type etc.Shown in figure 12; In this embodiment; Said filter circuit comprises: the one group of LC mode filter that links to each other with the output of every topology unit mutually; Shown in figure 12, with first inductance L 1 that links to each other of the output of topology unit and the capacitor C 1 that links to each other with inductance L 1 mutually, with second mutually the inductance L 2 that links to each other of the output of topology unit reach the capacitor C 2 that links to each other with inductance L 2; The inductance L that links to each other with the output of third phase topology unit 3 and capacitor C 3, three capacitor C 1, C2, C3 of linking to each other with inductance L 3 and the other end outside inductance links to each other all are connected to the tie point of dividing potential drop capacitor C 11 and C22.
Figure 13, Figure 14, three-phase four-wire system three-level inverter shown in Figure 15 and Figure 12 are similar, and just the three-phase topology unit among Figure 13 is respectively the first topology unit M1, the first topology unit M1 and the second topology unit M2; Three-phase topology unit among Figure 14 is respectively the first topology unit M1, the second topology unit M2 and the second topology unit M2; Three-phase topology unit among Figure 15 is the second topology unit M2.
Need to prove that the three-phase phase-sequence of each the three-phase four-wire system three-level inverter output shown in above-mentioned Figure 12 to Figure 15 can be arbitrarily, and this embodiment of the invention is not done qualification.
In each the three-phase four-wire system three-level inverter shown in above-mentioned Figure 12 to Figure 15, draw zero line by the tie point of two dividing potential drop capacitor C 11, C12, the three-phase topology unit is drawn three live wires respectively.
Figure 16, Figure 17, Figure 18, Figure 19, Figure 20 are respectively the another kind of structural representations of embodiment of the invention three-phase four-wire system three-level inverter.
Different with each the three-phase four-wire system three-level inverter shown in above-mentioned Figure 12 to Figure 15 is; In these several embodiment; Zero line also be by one independently topology unit (the first topology unit M1 or the second topology unit M2) provide; Each three-phase four-wire system three-level inverter shown in other structure and above-mentioned Figure 12 to Figure 15 is similar, is not described in detail at this.
Need to prove, Figure 16 to each three-phase four-wire system three-level inverter shown in Figure 20, in the output of four topology unit, can select wherein any one as zero line, the output of other other three topology unit is as live wire.
Continue below to combine Fig. 3 and Fig. 4 to specify the course of work of each topology unit in the embodiment of the invention.
In the embodiment of the invention in first topology unit and second topology unit drive signal of four switching devices hand over to cut by sinusoidal modulation wave (being modulation signal) and triangular carrier (being carrier signal) and produce, shown in figure 21.
Wherein, Ug is sinusoidal wave, and such as 50Hz, Uc is a triangular carrier, like 20KHz.S1, S2, S3 and S4 represent the drive signal of first switching device, second switch device, the 3rd switching device and the 4th switching device, V respectively
AnThe output signal of representing corresponding topology unit.
At the positive half period of said sinusoidal modulation wave Ug, second switch device and the 4th switching device drive with power frequency component, and first switching device and the 3rd switching device drive with high-frequency pulse signal.Particularly, shown in figure 21, second switch break-over of device, the 4th switching device turn-off, and if the level of said triangular carrier less than the level of said sinusoidal modulation wave, i.e. Uc＜Ug, the then first switching device conducting, the 3rd switching device turn-offs; If the level of said triangular carrier is greater than the level of said sinusoidal modulation wave, i.e. Uc＞Ug, then first switching device turn-offs, the 3rd switching device conducting;
At the negative half-cycle of said sinusoidal modulation wave Ug, first switching device and the 3rd switching device drive with power frequency component, and second switch device and the 4th switching device drive with high-frequency pulse signal.Particularly, shown in figure 21, first switching device keeps off state; The 3rd switching device keeps conducting state, and if the level of said triangular carrier greater than said sinusoidal modulation wave the level after reverse, promptly Uc＞-Ug; Second switch break-over of device then, the 4th switching device turn-offs; If the level of said triangular carrier is the level after reverse less than said sinusoidal modulation wave, promptly Uc＜-Ug, then the second switch device turn-offs, the 4th switching device conducting.
Need to prove that above-mentioned high-frequency pulse signal is a pwm pulse signal, such as being the pulse signal in the KHz scope.
The first topology unit M1 in the embodiment of the invention and the second topology unit M2 all are operated in the operation mode of three level, are elaborated respectively in the face of this down.
Figure 22, Figure 23 and Figure 24 show three operation modes of the first topology unit M1 respectively, wherein:
Shown in figure 22, when first switch transistor T 1, second switch pipe T2 conducting, the 3rd switch transistor T 3, the 4th switch transistor T 4, the 3rd diode D3, the 4th diode D4 by the time, the level of output node a equals the positive bus-bar level.When the outlet side electric current flowed out to inductance L from node a, the first diode D1, the second diode D2 ended, and current circuit is T1-T2-L-V
G-C1-T1; The outlet side electric current is during from inductance L flows into node a, the first diode D1 and the second diode D2 conducting, and current circuit is D2-D1-C1-V
G-L-D2.
Shown in figure 23, when second switch pipe T2,3 conductings of the 3rd switch transistor T, first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 by the time, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
Dc/ 2, wherein, V
DcLevel for DC power supply.When the outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 ends, and current circuit is D3-T2-L-V
G-D3; The outlet side electric current is during from first inductance L, 1 flows into node a, the second diode D2 conducting, and the 3rd diode D3 ends, and current circuit is D2-T3-V
G-L-D2.
Shown in figure 24, when the 3rd switch transistor T 3,4 conductings of the 4th switch transistor T, first switch transistor T 1, second switch pipe T2, the first diode D1, the second diode D2, the 3rd diode D3 by the time, the level of output node a equals the negative busbar level.When the outlet side electric current flows out to inductance L from node a, the 4th diode D4 conducting, current circuit is D4-L-V
G-C2-D4; The outlet side electric current is during from inductance L flows into node a, and the 4th diode D4 ends, and current circuit is T4-C2-V
G-L-T4.
Can find out that by the above-mentioned course of work first topology unit in the embodiment of the invention is compared with existing " 1 " font topology, need not two clamping diodes, has reduced the on-state loss of a switching tube; Compare with existing " T " font topology, device count is identical, and wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe for use, reduces loss, improves conversion efficiency.
Figure 25, Figure 26 and Figure 27 show three operation modes of the first topology unit M1 respectively, wherein:
Shown in figure 25, when first switch transistor T 1, second switch pipe T2 conducting, the 3rd switch transistor T 3, the 4th switch transistor T 4, the second diode D2, the 3rd diode D3, the 4th diode D4 by the time, the level of output node a equals the positive bus-bar level.When the outlet side electric current flowed out to inductance L from node a, the first diode D1 ended, and current circuit is T1-L-V
G-C1-T1; When the outlet side electric current flows to a point from inductance L, the first diode D1 conducting, current circuit is D1-C1-V
G-L-D1.
Shown in figure 26, when second switch pipe T2,3 conductings of the 3rd switch transistor T, first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 by the time, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
Dc/ 2, wherein, V
DcLevel for DC power supply.When the outlet side electric current flows out to L from node a, the 3rd diode D3 conducting, the second diode D2 ends, and current circuit is T2-D3-L-V
G-T2; The outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 ends, and current circuit is T3-D2-V
G-L-T3.
Shown in figure 27, when second switch pipe T2,3 conductings of the 3rd switch transistor T, first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 by the time, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
Dc/ 2, wherein, V
DcLevel for DC power supply.When the outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 ends, and current circuit is T2-D3-L-V
G-T2; The outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 ends, and current circuit is T3-D2-V
G-L-T3.
Can find out that by the above-mentioned course of work second topology unit in the embodiment of the invention is compared with existing " 1 " font topology, need not two clamping diodes, has reduced the on-state loss of a switching tube; Compare with existing " T " font topology, device count is identical, and wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe for use, reduces loss, improves conversion efficiency.
Need to prove, in practical application, above-mentioned Fig. 5 to the single-phase full bridge three-level inverter shown in Figure 7, drive signal phase phasic difference 180 degree of corresponding each switching device in two different topology unit that brachium pontis comprised.The three-phase three-wire system three-level inverter that Fig. 8 is extremely shown in Figure 11 and Figure 12 are to three-phase four-wire system three-level inverter shown in Figure 15, and the drive signal phase place of corresponding each switching device mutual 120 is spent in the three-phase topology unit.
Figure 16 is to three-phase four-wire system three-level inverter shown in Figure 20, and the drive signal phase place mutual deviation 120 of corresponding each switching device is spent in three topology unit of three live wire correspondences.
More than the embodiment of the invention has been carried out detailed introduction, used embodiment among this paper the present invention set forth, the explanation of above embodiment just is used for help understanding equipment of the present invention; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (11)
1. single-phase full bridge three-level inverter; Be used for converting the direct current of DC power supply output to alternating current, it is characterized in that, comprising: two brachium pontis; Said two brachium pontis are connected between the said DC power supply, and each brachium pontis comprises following any topology unit respectively:
First topology unit; Comprise: four switching devices; First switching device wherein, second switch device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; Second end of the 3rd switching device connects the dividing potential drop mid point of said DC power supply, and first end of the 3rd switching device connects second end of first switching device and first end of second switch device; Second end of second switch device links to each other with first end of the 4th switching device and as an output of said inverter;
Second topology unit; Comprise: four switching devices; First switching device wherein, the 3rd switching device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; First end of second switch device connects the dividing potential drop mid point of said DC power supply, and second end of second switch device connects second end of the 3rd switching device and first end of the 4th switching device; Second end of first switching device links to each other with first end of the 3rd switching device and as an output of said inverter.
2. single-phase full bridge three-level inverter according to claim 1 is characterized in that, each switching device includes: switching tube and with the antiparallel diode of said switching tube.
3. single-phase full bridge three-level inverter according to claim 1 is characterized in that, the drive signal of four switching devices in said first topology unit or second topology unit is handed over to cut by sinusoidal modulation wave and triangular carrier and produced, and:
At the positive half period of said sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-off, and if the level of said triangular carrier less than the level of said sinusoidal modulation wave, the then first switching device conducting, the 3rd switching device turn-offs; If the level of said triangular carrier is greater than the level of said sinusoidal modulation wave, then first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at said sinusoidal modulation wave; First switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of said triangular carrier greater than said sinusoidal modulation wave the level after reverse; Second switch break-over of device then, the 4th switching device turn-offs; If the level of said triangular carrier is the level after reverse less than said sinusoidal modulation wave, then the second switch device turn-offs, the 4th switching device conducting.
4. according to each described single-phase full bridge three-level inverter of claim 1 to 3, it is characterized in that, also comprise:
Two dividing potential drop electric capacity are connected in series between the said DC power supply, are used for said DC power supply is carried out dividing potential drop, and the tie point of said two dividing potential drop electric capacity is the dividing potential drop mid point of said DC power supply.
5. according to each described single-phase full bridge three-level inverter of claim 1 to 3, it is characterized in that, also comprise:
Filter circuit is connected between the output of said two brachium pontis, is used for the high fdrequency component of the said inverter output of filtering signal.
6. three-phase tri-level inverter; Be used for converting the direct current of DC power supply output to alternating current; It is characterized in that; Comprise: the three-phase topology unit, each the phase topology unit in the said three-phase topology unit is connected between the said DC power supply, and is following any topology unit:
First topology unit; Comprise: four switching devices; First switching device wherein, second switch device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; Second end of the 3rd switching device connects the dividing potential drop mid point of said DC power supply, and first end of the 3rd switching device connects second end of first switching device and first end of second switch device; Second end of second switch device links to each other with first end of the 4th switching device and as an output of said inverter;
Second topology unit; Comprise: four switching devices; First switching device wherein, the 3rd switching device and the 4th switching device are connected in series between the said DC power supply; Wherein, first end of first switching device connects the anode of said DC power supply, and second end of the 4th switching device connects the negative terminal of said DC power supply; First end of second switch device connects the dividing potential drop mid point of said DC power supply, and second end of second switch device connects second end of the 3rd switching device and first end of the 4th switching device; Second end of first switching device links to each other with first end of the 3rd switching device and as an output of said inverter.
7. three-phase tri-level inverter according to claim 6 is characterized in that, each switching device includes: switching tube and with the antiparallel diode of said switching tube.
8. three-phase tri-level inverter according to claim 6 is characterized in that, the drive signal of four switching devices in said first topology unit or second topology unit is cut generation by sinusoidal wave the friendship with triangular carrier, and:
At the positive half period of said sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-off, and if the level of said triangular carrier less than the level of said sinusoidal modulation wave, the then first switching device conducting, the 3rd switching device turn-offs; If the level of said triangular carrier is greater than the level of said sinusoidal modulation wave, then first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at said sinusoidal modulation wave; First switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of said triangular carrier greater than said sinusoidal modulation wave the level after reverse; Second switch break-over of device then, the 4th switching device turn-offs; If the level of said triangular carrier is the level after reverse less than said sinusoidal modulation wave, then the second switch device turn-offs, the 4th switching device conducting.
9. according to each described three-phase tri-level inverter of claim 6 to 8, it is characterized in that said inverter is the three-phase three-wire system three-level inverter, perhaps the three-phase four-wire system three-level inverter.
10. according to each described three-phase tri-level inverter of claim 6 to 8, it is characterized in that, also comprise:
Two dividing potential drop electric capacity are connected in series between the said DC power supply, are used for said DC power supply is carried out dividing potential drop, and the tie point of said two dividing potential drop electric capacity is the dividing potential drop mid point of said DC power supply.
11. according to each described three-phase tri-level inverter of claim 6 to 8, it is characterized in that, also comprise:
Filter circuit is connected between the output of said three-phase topology unit, is used for the high fdrequency component of the said inverter output of filtering signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102769405A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and three-level converter |
| CN102769400A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level inverter circuit and three-level inverter |
| CN102780412A (en) * | 2012-06-29 | 2012-11-14 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and inverter |
| CN103916022A (en) * | 2014-04-13 | 2014-07-09 | 周细文 | Three-phase to single-phase electronic transformer topology structure |
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| JP4599959B2 (en) * | 2004-09-17 | 2010-12-15 | 富士電機ホールディングス株式会社 | Multi-level converter and control method thereof |
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| CN1969437A (en) * | 2004-06-18 | 2007-05-23 | Abb瑞士有限公司 | Method for error handling in a converter circuit for wiring of three voltage levels |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769405A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and three-level converter |
| CN102769400A (en) * | 2012-06-29 | 2012-11-07 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level inverter circuit and three-level inverter |
| CN102780412A (en) * | 2012-06-29 | 2012-11-14 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and inverter |
| CN102780412B (en) * | 2012-06-29 | 2015-02-18 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and inverter |
| CN102769405B (en) * | 2012-06-29 | 2015-04-15 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level circuit and three-level converter |
| CN102769400B (en) * | 2012-06-29 | 2015-04-15 | 阳光电源（上海）有限公司 | Single-phase half-bridge three-level inverter circuit and three-level inverter |
| CN103916022A (en) * | 2014-04-13 | 2014-07-09 | 周细文 | Three-phase to single-phase electronic transformer topology structure |
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