CN203563087U - A system for achieving baseband signal communication based on a NandFlash bus in a GNSS - Google Patents
A system for achieving baseband signal communication based on a NandFlash bus in a GNSS Download PDFInfo
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- CN203563087U CN203563087U CN201320521580.XU CN201320521580U CN203563087U CN 203563087 U CN203563087 U CN 203563087U CN 201320521580 U CN201320521580 U CN 201320521580U CN 203563087 U CN203563087 U CN 203563087U
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- nandflash
- baseband signal
- nandflash bus
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Abstract
The utility model relates to a system for achieving baseband signal communication based on a NandFlash bus in a GNSS. The system comprises an ARM processor, a NandFlash bus, and a baseband circuit. The ARM processor performs baseband data communication with the baseband circuit via the NandFlash bus, and comprises a CPU, a direct memory access controller, and a NandFlash bus controller. The CPU is connected with the NandFlash bus via the direct memory access controller and the NandFlash bus controller. The baseband circuit comprises a NandFlash interface controller and a baseband data processing sub circuit. The system may achieve increase in data transmission speed and saves a large amount of time for the CPU to carry out navigation calculation. Additionally, the system can be used in various navigation fields and other fields capable of applying this method, and is suitable for large-scale popularization and application.
Description
Technical field
The utility model relates to GLONASS (Global Navigation Satellite System) field, relates in particular to field of data transmission in global navigation satellite system receiver, specifically refers to the system that realizes baseband signal communication in a kind of GLONASS (Global Navigation Satellite System) based on NandFlash bus.
Background technology
At GNSS(Global Navigation Satellite System, global navigation satellite receiving system) in, multimode multi-frequency point tracking satellite due to receiver, current Beidou satellite navigation system (refering in particular to the Big Dipper two generations satellite navigation system), GPS(Global Navigation Satellite System, global positioning system), GLONASS(GLONASS, the abbreviation of GLONASS (Global Navigation Satellite System) in Russian) and Galileo(Galileo, European satellite navigation system) add up to tens frequencies, tracking channel can reach hundreds of, the data volume of communicating by letter with baseband signal has several K to 10K left and right.As shown in Fig. 2～3, for adopting the sequential chart that in prior art, VLIO bus is carried out baseband signal communication, as shown in Figures 4 and 5 for adopting SRAM(Static Random Access Memory in prior art, static RAM) bus carries out the sequential chart of baseband signal communication.Tradition RAM(Random-Access Memory, random access memory) bus or VLIO(Variable Latency I/O, variable delay I/O) bus timing is long, bus speed is slow, needs the signals such as a large amount of clock generating addresses, control, read-write, often reads and once needs to produce once identical sequential, efficiency is low, time is long, and the recurrence interval time is long, and access time will surpass the required real-time processing time of Satellite Tracking.
Utility model content
The purpose of this utility model is the shortcoming that has overcome above-mentioned prior art, provides a kind of and can realize the call duration time that solve to adopt the slow-footed problem of conventional bus read-write base band data transmission, greatly reduce baseband signal, saves the CPU processing time, had the system that realizes baseband signal communication in the GLONASS (Global Navigation Satellite System) of broader applications scope based on NandFlash bus.
To achieve these goals, the system that realizes baseband signal communication based on NandFlash bus in GLONASS (Global Navigation Satellite System) of the present utility model has following formation:
In this GLONASS (Global Navigation Satellite System), based on NandFlash bus, realize the system of baseband signal communication, its main feature is, described system comprises arm processor, NandFlash bus and baseband circuit, and described arm processor is connected with described baseband circuit by described NandFlash bus.
Preferably, described arm processor comprises CPU, direct memory access controller and NandFlash bus control unit, and described CPU is connected with described NandFlash bus by described direct memory access controller, NandFlash bus control unit.
More preferably, described system also comprises RAM bus, and described CPU is connected with described RAM bus.
More preferably, described system also comprises VLIO bus, and described CPU is connected with described VLIO bus.
Preferably, described baseband circuit comprises NandFlash interface controller and base band data processing electronic circuit, and described base band data is processed electronic circuit and is connected with described NandFlash bus by described NandFlash interface controller.
Preferably, described GLONASS (Global Navigation Satellite System) is Beidou satellite navigation system, GPS, GLONASS or Galileo navigation system.
Adopted and based on NandFlash bus, realized the system of baseband signal communication in this utility model, there is following beneficial effect:
Choose the alternative traditional bus of NandFlash bus and realize baseband signal communication, improve data reading speed.Adopt dma controller to realize NandFlash bus data to the transfer of data between internal memory simultaneously, dma controller can be realized data backstage and directly transmit, do not take the CPU processing time, for saving lower a large amount of time, CPU carries out navigation calculation, be not limited only to be applied in gps satellite navigation tracking field, also can be applied to other navigation field or other can apply the field of this system, be applicable to large-scale promotion application.
Accompanying drawing explanation
Fig. 1 realizes the structural representation of the system of baseband signal communication based on NandFlash bus in GNSS of the present utility model.
Fig. 2 is the sequential chart that available technology adopting VLIO bus is carried out baseband signal received communication.
Fig. 3 is that available technology adopting VLIO bus is carried out the sequential chart that baseband signal sends communication.
Fig. 4 is the sequential chart that available technology adopting SRAM bus is carried out baseband signal received communication.
Fig. 5 is that available technology adopting SRAM bus is carried out the sequential chart that baseband signal sends communication.
Fig. 6 adopts NandFlash bus to carry out the sequential chart of baseband signal received communication in the utility model.
Fig. 7 adopts NandFlash bus to carry out the sequential chart that baseband signal sends communication in the utility model.
Embodiment
In order more clearly to describe technology contents of the present utility model, below in conjunction with specific embodiment, conduct further description.
In order to overcome the shortcoming of above-mentioned prior art, the utility model has been studied current ARM(Advanced Risc Machellones) the conventional bus timing of processor, for complexity and communication speed, assess, (NandFlash internal memory is a kind of of Flash internal memory to choose NandFlash bus, for a kind of capacity larger, rewrite fireballing nonvolatile flash memory) substitute the communication that traditional RAM and VLIO bus realize baseband signal, and adopt DMA(Direct Memory Access, direct memory access) controller is realized NandFlash data to the transmission of internal memory, do not take the CPU core time, the feature of NandFlash bus is synchronously to read and write data, synchronous read or write speed is fast, baseband circuit simulation NandFlash bus transfer data.
Be illustrated in figure 1 the structural representation of realizing the system of baseband signal communication based on NandFlash bus of the present utility model.
Described system comprises arm processor, NandFlash bus and baseband circuit, and described arm processor carries out base band data by described NandFlash bus and described baseband circuit and communicates by letter.
Described arm processor comprises CPU, direct memory access controller and NandFlash bus control unit, and described CPU is connected with described NandFlash bus by described direct memory access controller, NandFlash bus control unit.
Described baseband circuit comprises NandFlash interface controller and base band data processing electronic circuit, and described base band data is processed electronic circuit and is connected with described NandFlash bus by described NandFlash interface controller.
System applies of the present utility model can be adopted to following technical scheme in practical base-band data communication:
(1) described arm processor receives the satellite tracking data handling interrupt signal that described baseband circuit is initiated;
(2) described arm processor is by RAM bus or VLIO bus read data status information from described baseband circuit.Arm processor first reads a small amount of state information by conventional bus.
(3) CPU of described arm processor is under the control of described NandFlash bus control unit, by described NandFlash bus, in the mode of direct memory access, from described baseband circuit, reads base band data.Start NandFlash bus and send batch data reading order, start DMA and carry out transfer of data.Exit and interrupt carrying out other processing.
(4) described direct memory access controller is initiated transfer of data interruption;
(5) described arm processor carries out Satellite Tracking and resolves according to the base band data receiving.
(6) CPU of described arm processor is under the control of described NandFlash bus control unit, by described NandFlash bus, in the mode of direct memory access, base band data is sent to described baseband circuit.Start NandFlash controller and dma controller and base band is write to data block write base band, exit and interrupt carrying out other processing.
As Fig. 6～7 are depicted as the sequential chart that adopts NandFlash bus to carry out baseband signal communication.
Adopt the sequential scheme of NandFlash bus timing only in generation address, beginning and control signal, data acquisition synchronous transmission subsequently, one group of data of every read-write clock transfer, can greatly improve data signaling rate.Shortcoming is exactly must read a blocks of data at every turn, and common NandFlash block size is 512 bytes and 2048 bytes at present.For GNSS satellite baseband signal, process and all will read in a large amount of continuous data situations at every turn, these shortcomings can not exert an influence to system.Coordinate with NandFlash bus and adopt DMA transfer of data, DMA transfer of data does not take the CPU core time simultaneously.
In GNSS of the present utility model, based on NandFlash bus, realize in the technical scheme of system of baseband signal communication, wherein each included function device and device all can be corresponding to actual particular hardware circuit structures, therefore these building blocks only utilize hardware circuit just can realize, and do not need to assist can automatically realize corresponding function specifically to control software.
Wherein arm processor can adopt the risc microcontroller of Acorn computer Co., Ltd design, CPU in arm processor can adopt the CPU of GNSS receiver general on market, NandFlash interface controller in dma controller wherein of arm processor and NandFlash bus control unit, baseband circuit all can be selected universal hardware product common on market, and the base band signal process electronic circuit in baseband circuit can adopt the base band signal process circuit being combined by frequency mixer, filter circuit, analog to digital conversion circuit.
Adopted and based on NandFlash bus, realized the system of baseband signal communication in this utility model, there is following beneficial effect:
Choose the alternative traditional bus of NandFlash bus and realize baseband signal communication, improve data reading speed.Adopt dma controller to realize NandFlash bus data to the transfer of data between internal memory simultaneously, dma controller can be realized data backstage and directly transmit, do not take the CPU processing time, for saving lower a large amount of time, CPU carries out navigation calculation, be not limited only to be applied in gps satellite navigation tracking field, also can be applied to other navigation field or other can apply the field of this system, be applicable to large-scale promotion application.
In this specification, the utility model is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from spirit and scope of the present utility model.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (6)
1. a GNSS is based on NandFlash bus baseband signal communication system, it is characterized in that, described system comprises arm processor, NandFlash bus and baseband circuit, and described arm processor is connected with described baseband circuit by described NandFlash bus.
2. GNSS according to claim 1 is based on NandFlash bus baseband signal communication system, it is characterized in that, described arm processor comprises CPU, direct memory access controller and NandFlash bus control unit, and described CPU is connected with described NandFlash bus by described direct memory access controller, NandFlash bus control unit.
3. GNSS according to claim 2, based on NandFlash bus baseband signal communication system, is characterized in that, described system also comprises RAM bus, and described CPU is connected with described RAM bus.
4. GNSS according to claim 2, based on NandFlash bus baseband signal communication system, is characterized in that, described system also comprises VLIO bus, and described CPU is connected with described VLIO bus.
5. GNSS according to claim 1 is based on NandFlash bus baseband signal communication system, it is characterized in that, described baseband circuit comprises NandFlash interface controller and base band data processing electronic circuit, and described base band data is processed electronic circuit and is connected with described NandFlash bus by described NandFlash interface controller.
According to the GNSS described in any one in claim 1 to 5 based on NandFlash bus baseband signal communication system, it is characterized in that, described GNSS is Beidou satellite navigation system, GPS, GLONASS or Galileo navigation system.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320521580.XU CN203563087U (en) | 2013-08-23 | 2013-08-23 | A system for achieving baseband signal communication based on a NandFlash bus in a GNSS |
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| CN201320521580.XU CN203563087U (en) | 2013-08-23 | 2013-08-23 | A system for achieving baseband signal communication based on a NandFlash bus in a GNSS |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103414623A (en) * | 2013-08-23 | 2013-11-27 | 上海司南卫星导航技术有限公司 | System and method for achieving baseband signal communication based on NandFlash bus in GNSS |
| CN113568565A (en) * | 2020-04-29 | 2021-10-29 | 爱思开海力士有限公司 | Memory controller and operating method thereof |
-
2013
- 2013-08-23 CN CN201320521580.XU patent/CN203563087U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103414623A (en) * | 2013-08-23 | 2013-11-27 | 上海司南卫星导航技术有限公司 | System and method for achieving baseband signal communication based on NandFlash bus in GNSS |
| CN103414623B (en) * | 2013-08-23 | 2016-08-10 | 上海司南卫星导航技术股份有限公司 | GNSS realizes the system and method for baseband signal communication based on NandFlash bus |
| CN113568565A (en) * | 2020-04-29 | 2021-10-29 | 爱思开海力士有限公司 | Memory controller and operating method thereof |
| CN113568565B (en) * | 2020-04-29 | 2024-01-26 | 爱思开海力士有限公司 | Memory controller and method of operating the same |
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Address after: 201801 Shanghai city Jiading District Chengliu Road No. 618 Building No. 2 Patentee after: COMNAV TECHNOLOGY Ltd. Address before: 201103 Minhang District Lotus Road, Lane No. 2080, building E, floor 50, Shanghai, China Patentee before: ComNav Technology Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20140423 |
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| CX01 | Expiry of patent term |