CN203502448U - Simple signal wave generator - Google Patents
Simple signal wave generator Download PDFInfo
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- CN203502448U CN203502448U CN201320657219.XU CN201320657219U CN203502448U CN 203502448 U CN203502448 U CN 203502448U CN 201320657219 U CN201320657219 U CN 201320657219U CN 203502448 U CN203502448 U CN 203502448U
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Abstract
Disclosed in the utility model is a simple signal wave generator comprising a direct-current power supply, a diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a potentiometer and a time-based chip. Compared with the prior art, the provided simple signal wave generator has the advantages of simple structure, low cost, and convenient adjustment; a square wave, a triangular wave, and a sinusoidal wave are outputted simultaneously through a first signal output terminal, a second signal output terminal and a third signal output terminal. And the simple signal wave generator is especially suitable for an experiment of signal waveform observation during oscilloscope teaching or other testing instrument application.
Description
Technical field
The utility model relates to a kind of signal wave generator, relates in particular to a kind of easy signal wave generator.
Background technology
Along with China's economy and scientific and technological development, corresponding testing tool and means of testing are also had higher requirement, oneself becomes a vital class in testing tool signal wave generator, therefore developing signal generator is significant, signal wave emitter structures is now too complicated, cost of manufacture is higher, uses cumbersomely, to us, has brought unnecessary loss.
Summary of the invention
The purpose of this utility model is that a kind of easy signal wave generator will be provided.
For achieving the above object, the utility model is implemented according to following technical scheme:
The utility model comprises direct supply, diode, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, potentiometer and Shi Ji chip, the anodal while of described direct supply and the positive pole of described diode, the positive pole of described the first electric capacity, the first end of described the second resistance, when described, the power voltage terminal of the reset terminal of base chip base chip when described is connected, and the negative pole of described direct supply simultaneously and the first end of described the first resistance, the negative pole of described the first electric capacity, the first end of described the second electric capacity, the earth terminal of base chip when described, the first end of described the 3rd electric capacity, the first end of described the 5th electric capacity, the first end of the first end of described the 6th electric capacity and described the 7th electric capacity is connected and ground connection, and the second end of described the first resistance is connected with the negative pole of described diode, the second end while of described the second electric capacity and the first end of described potentiometer, when described, the low level trigger end of the thresholding end of base chip base chip when described is connected, the second end of described potentiometer is connected with the first end of described the 3rd resistance, the second end of described the 3rd resistance is connected with the discharge end of the second end of described the second resistance base chip when described simultaneously, when described, the voltage controling end of base chip is connected with the second end of described the 3rd electric capacity, when described, the output terminal of base chip is connected with the positive pole of described the 4th electric capacity, the negative pole of described the 4th electric capacity is connected with first signal output terminal with the first end of described the 4th resistance simultaneously, the second end while of described the 4th resistance and the second end of described the 5th electric capacity, the first end of described the 5th resistance is connected with secondary signal output terminal, the second end of described the 5th resistance is connected with the first end of described the 6th resistance with the second end of described the 6th electric capacity simultaneously, and the second end of described the 6th resistance is connected with the 3rd signal output part with the second end of described the 7th electric capacity simultaneously.
Particularly, described diode is light emitting diode, and described the first electric capacity and described the 4th electric capacity are polar capacitor.
Compared with prior art, the utility model circuit structure is simple, with low cost, easy to adjust, can export square wave, triangular wave and sine wave by first signal output terminal, secondary signal output terminal and the 3rd signal output part simultaneously, be particularly suitable for the experiment of observation signal waveform or the application of other testing tool in oscillograph teaching.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the utility model is further described, in illustrative examples and the explanation of this utility model, is used for explaining the utility model, but not as to restriction of the present utility model.
As shown in Figure 1: the utility model comprises direct supply DC, diode D, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the first capacitor C 1, the second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, the 6th capacitor C 6, the 7th capacitor C 7, potentiometer RP and Shi Ji chip IC, diode D is light emitting diode, the first capacitor C 1 and the 4th capacitor C 4 are polar capacitor, the anodal while of direct supply DC and the positive pole of diode D, the positive pole of the first capacitor C 1, the first end of the second resistance R 2, time base chip IC reset terminal be connected with the power voltage terminal of Shi Ji chip IC, the negative pole of direct supply DC is simultaneously and the first end of the first resistance R 1, the negative pole of the first capacitor C 1, the first end of the second capacitor C 2, time base chip IC earth terminal, the first end of the 3rd capacitor C 3, the first end of the 5th capacitor C 5, the first end of the first end of the 6th capacitor C 6 and the 7th capacitor C 7 is connected and ground connection, and the second end of the first resistance R 1 is connected with the negative pole of diode D, the second end while of the second capacitor C 2 and the first end of potentiometer RP, time base chip IC thresholding end with time base chip IC low level trigger end be connected, the second end of potentiometer RP is connected with the first end of the 3rd resistance R 3, the second end of the 3rd resistance R 3 simultaneously with the second end of the second resistance R 2 with time base chip IC discharge end be connected, time base chip IC voltage controling end be connected with the second end of the 3rd capacitor C 3, time base chip IC output terminal be connected with the positive pole of the 4th capacitor C 4, the negative pole of the 4th capacitor C 4 is connected with first signal output terminal VO1 with the first end of the 4th resistance R 4 simultaneously, the second end while of the 4th resistance R 4 and the second end of the 5th capacitor C 5, the first end of the 5th resistance R 5 is connected with secondary signal output terminal VO2, the second end of the 5th resistance R 5 is connected with the first end of the 6th resistance R 6 with the second end of the 6th capacitor C 6 simultaneously, and the second end of the 6th resistance R 6 is connected with the 3rd signal output part VO3 with the second end of the 7th capacitor C 7 simultaneously.
The utility model can pass through first signal output terminal VO1, secondary signal output terminal VO2 and the 3rd signal output part VO3 export square wave simultaneously, triangular wave and sine wave, be particularly suitable for the experiment of observation signal waveform or the application of other testing tool in oscillograph teaching, this signal wave generator circuit is simple, with low cost, easy to adjust, in the time of wherein, base chip IC is selected 555 family chips, the second capacitor C 2 is timing capacitor, its charging rate and discharge time constant approximately equal, by time base chip IC output terminal output be near symmetrical square wave, by regulator potentiometer RP, can change the frequency of the oscillator that time base variable chip IC forms, square-wave signal is after the 4th resistance R 4 and the 5th capacitor C 5, output triangular wave, triangular wave is again through the 5th resistance R 5, the 6th capacitor C 6, the 6th resistance R 6 and the approximate sine wave of the 7th capacitor C 7 output, diode D is as power supply indication.
The technical solution of the utility model is not limited to the restriction of above-mentioned specific embodiment, and every technology distortion of making according to the technical solution of the utility model, within all falling into protection domain of the present utility model.
Claims (2)
1. an easy signal wave generator, is characterized in that: comprise direct supply, diode, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the first electric capacity, the second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, the 7th electric capacity, potentiometer and Shi Ji chip, the anodal while of described direct supply and the positive pole of described diode, the positive pole of described the first electric capacity, the first end of described the second resistance, when described, the power voltage terminal of the reset terminal of base chip base chip when described is connected, and the negative pole of described direct supply simultaneously and the first end of described the first resistance, the negative pole of described the first electric capacity, the first end of described the second electric capacity, the earth terminal of base chip when described, the first end of described the 3rd electric capacity, the first end of described the 5th electric capacity, the first end of the first end of described the 6th electric capacity and described the 7th electric capacity is connected and ground connection, and the second end of described the first resistance is connected with the negative pole of described diode, the second end while of described the second electric capacity and the first end of described potentiometer, when described, the low level trigger end of the thresholding end of base chip base chip when described is connected, the second end of described potentiometer is connected with the first end of described the 3rd resistance, the second end of described the 3rd resistance is connected with the discharge end of the second end of described the second resistance base chip when described simultaneously, when described, the voltage controling end of base chip is connected with the second end of described the 3rd electric capacity, when described, the output terminal of base chip is connected with the positive pole of described the 4th electric capacity, the negative pole of described the 4th electric capacity is connected with first signal output terminal with the first end of described the 4th resistance simultaneously, the second end while of described the 4th resistance and the second end of described the 5th electric capacity, the first end of described the 5th resistance is connected with secondary signal output terminal, the second end of described the 5th resistance is connected with the first end of described the 6th resistance with the second end of described the 6th electric capacity simultaneously, and the second end of described the 6th resistance is connected with the 3rd signal output part with the second end of described the 7th electric capacity simultaneously.
2. easy signal wave generator according to claim 1, is characterized in that: described diode is light emitting diode, and described the first electric capacity and described the 4th electric capacity are polar capacitor.
Priority Applications (1)
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CN201320657219.XU CN203502448U (en) | 2013-10-22 | 2013-10-22 | Simple signal wave generator |
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CN201320657219.XU CN203502448U (en) | 2013-10-22 | 2013-10-22 | Simple signal wave generator |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104407185A (en) * | 2014-12-08 | 2015-03-11 | 赵伊苓 | Electric oscillating wave generator |
CN105244883A (en) * | 2015-11-20 | 2016-01-13 | 国家电网公司 | High-frequency filter |
CN105281351A (en) * | 2015-11-20 | 2016-01-27 | 国家电网公司 | A low-voltage transformer area electric energy quality control device |
CN109044573A (en) * | 2018-08-31 | 2018-12-21 | 东北电力大学 | wearable bone stress real-time monitoring system |
-
2013
- 2013-10-22 CN CN201320657219.XU patent/CN203502448U/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104407185A (en) * | 2014-12-08 | 2015-03-11 | 赵伊苓 | Electric oscillating wave generator |
CN105244883A (en) * | 2015-11-20 | 2016-01-13 | 国家电网公司 | High-frequency filter |
CN105281351A (en) * | 2015-11-20 | 2016-01-27 | 国家电网公司 | A low-voltage transformer area electric energy quality control device |
CN109044573A (en) * | 2018-08-31 | 2018-12-21 | 东北电力大学 | wearable bone stress real-time monitoring system |
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140326 Termination date: 20141022 |
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EXPY | Termination of patent right or utility model |