CN203482089U - Current limiting circuit - Google Patents
Current limiting circuit Download PDFInfo
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- CN203482089U CN203482089U CN201320594163.8U CN201320594163U CN203482089U CN 203482089 U CN203482089 U CN 203482089U CN 201320594163 U CN201320594163 U CN 201320594163U CN 203482089 U CN203482089 U CN 203482089U
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Abstract
The utility model relates to a current limiting circuit, which comprises a comparison unit, a trigger unit, a first counter and a second counter, wherein the comparison unit compares reference current and sampling current to obtain an overcurrent judgment signal and controls current of an external circuit never to exceed the reference current when overcurrent happens to the sampling current, and the reference current is transient reference current or steady-state reference current; the trigger unit is used for determining the reference current inputted to the comparison unit to be transient reference current or steady-state reference current; the first counter operates when the sampling current is higher than the transient reference current, and the full counting time of the first counter is the overcurrent time when the sampling current is allowed to exceed the transient reference current; and the second counter operates when the sampling current is higher than the steady-state reference current, and the full counting time of the second counter is the overcurrent time when the sampling current is allowed to exceed the steady-state reference current.
Description
Technical field
The utility model relates to electronic circuit technology field, relates in particular to a kind of current limit circuit.
Background technology
Current limit circuit in traditional power management chip is generally a fixing current threshold.For example, in voltage regulator, the peak value that generally can control its output current is a certain current threshold, and by negative feedback, realizing its maximum output current is a certain fixed value.Current limit circuit is used for limiting power supply chip can not damaged when occurring that load current is excessive.And the main damage mode of semiconductor circuit when there is overcurrent is cause thermal damage, when chip overheating and damage.Prior art is to realize the control to maximum average current by setting a constant current peak value.
But in real system, occur that sometimes the electric current of moment is excessive, but the duration is not long, for example, when radio circuit is launched, needs higher immediate current.Can there is overcurrent protection in existing current limit circuit, cause output voltage to decline, and when output voltage declines when violent, causes some circuit to work.And long overcurrent condition to a certain degree of duration can't cause voltage management chip temperature to raise too much, thereby can not cause chip to damage.Moment provides being designed with of large electric current to help improve the load response characteristic of power management chip when load jumps to heavy duty from underloading in addition.When occurring being downloaded on the lenient side heavily loaded rapid jumping, can provide the power management chip of instantaneous large-current can come with larger output current, to output node charging, to reduce the amplitude that output voltage declines.
Utility model content
The purpose of this utility model is to provide a kind of current limit circuit; when can realize the lower current-limiting protection of circuit normal operation; can also realize the current-limiting protection under circuit transient response; can support moment to need the more system applies of High-current output, avoid system not normal due to the restriction of instantaneous large-current.
The utility model provides a kind of current limit circuit, comprising:
Comparing unit, by reference current and sample rate current are compared, obtains overcurrent judgement signal, in order to control the electric current of external circuit when the described sample rate current generation overcurrent, is no more than all the time reference current; Described reference current is transient state reference current or stable state reference current;
The first counter, the reset terminal of described the first counter is connected with the output of described comparing unit, by described overcurrent judgement signal, provides the first reset signal for described the first counter; When described sample rate current is during higher than transient state reference current, described the first counter works, the time that described the first counter is write all over is for allowing sample rate current to surpass the overcurrent time of transient state reference current;
Flip-flop element, the input end of clock of described flip-flop element is connected with the output of the first counter, the data terminal of described flip-flop element is connected with supply voltage, the forward output of described flip-flop element and the output signal of inverse output terminal are respectively used to the input of described reference current to control selection, determine that the reference current of described comparing unit access is transient state reference current or stable state reference current;
The second counter, the reset terminal of described the second counter is connected with the inverse output terminal of described flip-flop element, and the reversed-phase output of described flip-flop element provides the second reset signal for described the second counter; The input end of clock of described the second counter is connected with the input end of clock of described the first counter; Meanwhile, the output of described the second counter provides the 3rd reset signal for described flip-flop element; When described sample rate current is during higher than stable state reference current, described the second counter works, the time that described the second counter is write all over is for allowing sample rate current to surpass the overcurrent time of stable state reference current.
Preferably, the forward output of described flip-flop element is used for controlling the described stable state reference current of access; The inverse output terminal of described flip-flop element is used for controlling the described transient state reference current of access.
Preferably, described flip-flop element comprise one or and a d type flip flop, the output signal of described the second counter and the power-on reset signal of current limit circuit become the reset signal of d type flip flop by access or pupil;
When described supply voltage is during lower than threshold voltage, described d type flip flop is in reset mode; When described supply voltage is higher than threshold voltage and described the second counter during in reset mode, described d type flip flop is in running order.
Further preferably, described flip-flop element also comprises an inverter, is connected with the forward output of described d type flip flop, makes the output of described inverter form the inverse output terminal of described flip-flop element.
Preferably, after circuit electrification reset, the reference current signal of the access of described comparator is transient state reference current signal; When sample rate current is during higher than transient current, described comparing unit generated flow control signals, and the output of controlling external circuit is restricted to transient current; And, described the first counter is started working, after described the first counter is write all over, the input end of clock of described flip-flop element receives the rising edge clock signal of described the first timer output, the forward output output digit signals high level of described flip-flop element, the reference current signal of the access of comparator is stable state reference current signal described in FEEDBACK CONTROL; The inverse output terminal output digit signals low level of described flip-flop element, the second counter enters operating state described in FEEDBACK CONTROL.
Further preferably, after the reference current signal of the access of described comparator is stable state reference current signal, when sample rate current is during higher than steady-state current, described comparing unit generated flow control signals, and the output current of controlling external circuit is restricted to steady-state current; After described the second counter is write all over, the reset terminal of described flip-flop element receives the rising edge clock signal of described the second timer output and resets, the forward output output digit signals low level of described flip-flop element, the inverse output terminal output digit signals high level of described flip-flop element, the reference current signal of the access of comparator described in FEEDBACK CONTROL is transient state reference current signal, and described in FEEDBACK CONTROL, the second counter resets.
A kind of current limit circuit providing at the utility model; when can realize the lower current-limiting protection of circuit normal operation; can also realize the current-limiting protection under circuit transient response; can support moment to need the more system applies of High-current output, avoid system not normal due to the restriction of instantaneous large-current.
Accompanying drawing explanation
The circuit diagram of a kind of current limit circuit that Fig. 1 provides for the utility model embodiment;
The specific implementation of the first counter in a kind of current limit circuit that Fig. 2 provides for the utility model embodiment;
There is the Current Control schematic diagram of over-current state in the current limit circuit that Fig. 3 provides for the utility model embodiment.
Below in conjunction with drawings and Examples, the utility model is elaborated.
Embodiment
The utility model embodiment provides a kind of current limit circuit; be applicable to the current-limiting protection circuit of various power management chips; as low difference voltage regulator or DC-to-DC converter etc.; can realize the current-limiting protection to steady-state current under circuit normal operating conditions; can also realize the current-limiting protection to the more high threshold under circuit transient response simultaneously; can support moment to need the more system applies of High-current output, avoid system not normal due to the restriction of instantaneous large-current.
The circuit diagram of a kind of current limit circuit that Fig. 1 provides for the utility model embodiment.As shown in Figure 1, current limit circuit comprises: comparing unit 1, the first counter Timer1, flip-flop element 2 and the second counter Timer2.
The comparison signal of comparing unit 1 input is respectively reference current signal and sample rate current signal.By reference current signal and sample rate current signal are compared, the signal C exporting at the output of comparing unit 1 is overcurrent judgement signal, in order to when there is overcurrent according to the turning on and off of overcurrent judgement signal controlling external circuit, thereby make within the current signal of external circuit is limited to reference current range of signal.Concrete, when sample rate current signal is during higher than reference current signal, comparing unit 1 output digit signals high level; When sample rate current signal is not during higher than reference current signal, comparing unit 1 output digit signals low level.Wherein, reference current signal is transient state reference current signal I
hor stable state reference current signal I
l, both selections will be discussed hereinafter.By the output FEEDBACK CONTROL of current limit circuit, select the reference current signal of comparing unit 1 input to be specially transient state reference current signal I
hor stable state reference current signal I
l..Comparing unit 1 specifically can be realized by a current comparator com.
The reset terminal of the first counter Timer1 is connected with the overcurrent judgement signal C of the output of comparing unit 1, and by overcurrent judgement signal controlling, the first counter Timer1 resets or work.In the present embodiment, the first counter Timer1 is that low level resets.
In a concrete example, the first counter Timer1 can be the circuit shown in Fig. 2, adopts the circuit of multistage trigger series connection to realize tally function.The d type flip flop being triggered by a plurality of trailing edge clock signals forms, and each d type flip flop connects into 2 frequency division modes.Qb is the anti-phase output of output signal q, and R is reset terminal, for high level resets.In order to produce the low level of Timer1, reset, for the RESET input has increased inverter INV3.The progression of d type flip flop can be according to the frequency decision of required timing time and input clock, and d type flip flop progression is more, and the timing time of generation is longer; The frequency of the clock input signal CLK adopting is lower, and the timing time of generation is longer.
The input end of clock of flip-flop element 2 is connected with the output signal B of the output of the first counter Timer1.The data terminal of flip-flop element 2 is connected with supply voltage VDD, the forward output signal AN of flip-flop element 2 and oppositely output signal A control selection to the reference current signal input of comparing unit 1 respectively, when forward output signal AN is high level, oppositely output signal A is low level, the input of comparing unit 1 and stable state reference current signal I
laccess switch S 2 closures, by stable state reference current signal I
las reference current signal access comparing unit 1, and the input of comparing unit 1 and transient state reference current signal I
haccess switch S 1 disconnect, by stable state reference current signal I
las reference current signal access comparing unit 1; When forward output signal AN is low level, oppositely output signal A is high level, the input of comparing unit 1 and transient state reference current signal I
haccess switch S 1 closure, and the input of comparing unit 1 and stable state reference current signal I
laccess switch S 2 disconnect, by stable state reference current signal I
has reference current signal access comparing unit 1.
The reset terminal of the second counter Timer2 is connected with the inverse output terminal of flip-flop element 2, and the reversed-phase output signal A of flip-flop element 2 provides reset signal for the second counter Timer2; The input end of clock of the second counter Time2 is connected with the input end of clock of the first counter Timer1, receives external timing signal; Meanwhile, the output signal D of the second counter Timer2 is the reset signal RST of flip-flop element 2.In the present embodiment, the second counter Timer2 is that high level resets.
The physical circuit of the second counter Timer2 is realized similar to the first counter Timer1, and difference is only that the second counter Timer2 is that high level resets, and removes inverter INV3 and can realize in Fig. 2.And the progression of the flip-flops in series of the two can be different.
Preferably, flip-flop element 2 comprises one or an OR2 and a d type flip flop ffdr, and the power-on reset signal UV of the output signal of the second counter Timer2 and current limit circuit accesses in the lump or door OR2 generates the reset signal RST of d type flip flop ffdr; The power-on reset signal UV of current limit circuit is for the supply voltage state after indication circuit electrification reset, when supply voltage VDD works desired threshold voltage lower than circuit, UV is high level, when supply voltage meets the requiring of threshold voltage of circuit normal operation, UV is low level.Therefore, when supply voltage is during lower than threshold voltage, UV is high level, and d type flip flop is in reset mode.
Preferably, flip-flop element 2 also comprises an inverter INV1, is connected with the forward output terminals A N of d type flip flop ffdr, makes the output of inverter INV1 be the inverse output terminal A of flip-flop element 2.
Below the operation principle of the protective circuit of current limit shown in Fig. 1 is elaborated.
Under initial condition, supply voltage is lower than operating voltage requirement, and power-on reset signal UV is high level, and the reset signal RST that exports to d type flip flop ffdr of process or door OR2 is also high level, therefore the output signal AN of d type flip flop ffdr is reset to low level; The second counter Timer2 is resetted by the reverse output signal A of the high level of d type flip flop ffdr, and the second counter Timer2 output signal D is low level.
After circuit powers on, power-on reset signal UV becomes low level, and the reset terminal of d type flip flop ffdr is low level, and resetting, it is inoperative to control.D type flip flop ffdr waits for the triggering of rising edge clock signal, so output signal AN is still maintained low level.When initial thus, switch S 2 is turn-offed, switch S 1 conducting, and the negative input end of comparator is connected to transient state reference current signal I
h, now the overcurrent threshold value of system is higher.Is is the sample rate current signal of system, when Is is less than I
htime, transient current is not in the situation of overcurrent, and the overcurrent judgement signal C of comparator com output is low level.Now the current signal of external circuit is Is.Counter Time1 is low level reset mode, and now Timer1 is always in reset mode, and output signal B is low level always, and the output signal AN of d type flip flop ffdr continues to remain low level.
When occurring in the situation of transient state overcurrent, Is surpasses I
h, the overcurrent judgement signal C of comparator com output becomes high level, and the current signal of controlling external circuit is restricted to I
h, the reset locking of counter is removed simultaneously.Counter Timer1 will start the timing with clock input signal CLK.After meter is full, the output signal B of Time1 becomes high level, now to d type flip flop ffdr, provide a rising edge clock signal, d type flip flop ffdr exports the high level signal of the supply voltage VDD of its data terminal d to forward output signal AN, be that AN becomes high level, oppositely output signal A becomes low level.Now switch S 2 conductings, and switch S 1 shutoff, stable state reference current signal I
lbe connected to the negative input end of comparator com.When Is surpasses I
l, the overcurrent judgement signal C of comparator com output is high level, the current signal of controlling external circuit is restricted to I
l; When Is is less than I
ltime, the overcurrent judgement signal C of comparator com output is low level, the current signal of external circuit is Is.
And counter Timer2 be take signal A as reset signal, therefore when signal A is low level, Timer2 starts to count with clock signal clk, when meter is full, output signal D becomes high level, process or door OR2, the reset signal RST output high level of d type flip flop ffdr, is reset to low level by the output AN of d type flip flop ffdr.Then continue the timing of cycle counter Timer1.
Hence one can see that, and the time that described the first counter is write all over is for allowing the time of transient current overcurrent; The time that described the second counter is write all over is for allowing the time of steady-state current overcurrent.As shown in Figure 3, counter Timer1 counts the full time corresponding to the Ta time in Fig. 3; Counter Timer2 counts the full time corresponding to the Tb time in Fig. 3.After Timer1 writes all over, sample rate current current limliting is by I
hbecome I
l, after Timer2 writes all over, sample rate current current limliting is again by I
lbecome I
h, this is because cause the Causing Factors of Transient Currents a lot, except system powers on, for example also have in cell phone system, during radio transmitter work, cause the required immediate current of system to increase, and radio transmitter is not when work, the required electric current of system is less.In current system, having a lot of circuit is service intermittent (the general work time is shorter, and the length of one's sleep is longer), is in order to economize power consumption like this.Therefore need to change and also circuit be carried out to current-limiting protection for the transient current in these courses of work.The longest operating time when Tb can be according to the most of circuit service intermittent of routine is determined.
From foregoing description, the current limit circuit shown in Fig. 1 has been realized the current limit function that Fig. 3 describes.The overcurrent judgement signal C of output specifically can be for controlling switch-off power pipe.For example, for take the DC-to-DC converter that PMOS is power device, can judge that signal C controls its shutoff by overcurrent, play current limit function, specific implementation can for overcurrent judgement signal C and pulse-width signal from feedback control loop through or logic after control the grid of PMOS power device.
In addition, the relatively input of the utility model circuit can also be: the current signal Is of sampling is only the 1/N of actual current, wherein N>0, simultaneously reference current signal I
hand I
lalso be set to the 1/N of actual current limits value.The function of its realization is still identical with the function that Fig. 1 circuit is realized like this.
The utility model provides a kind of current limit circuit; when can realize the lower current-limiting protection of circuit normal operation; can also realize the current-limiting protection under circuit transient response; can support moment to need the more system applies of High-current output, avoid system not normal due to the restriction of instantaneous large-current.Current limit circuit of the present utility model has also improved the load response characteristic of power management chip.Allow moment to provide being designed with of large electric current to help improve the load response characteristic of power management chip when load jumps to heavy duty from underloading.When occurring being downloaded on the lenient side heavily loaded rapid jumping, can provide the power management chip of instantaneous large-current can come with larger output current, to output node charging, to reduce the amplitude that output voltage declines.
Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only embodiment of the present utility model; and be not used in and limit protection range of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.
Claims (6)
1. a current limit circuit, is characterized in that, described circuit comprises:
Comparing unit, by reference current and sample rate current are compared, obtains overcurrent judgement signal, in order to control the electric current of external circuit when the described sample rate current generation overcurrent, is no more than all the time reference current; Described reference current is transient state reference current or stable state reference current;
The first counter, the reset terminal of described the first counter is connected with the output of described comparing unit, by described overcurrent judgement signal, provides the first reset signal for described the first counter; When described sample rate current is during higher than transient state reference current, described the first counter works, the time that described the first counter is write all over is for allowing sample rate current to surpass the overcurrent time of transient state reference current;
Flip-flop element, the input end of clock of described flip-flop element is connected with the output of the first counter, the data terminal of described flip-flop element is connected with supply voltage, the forward output of described flip-flop element and the output signal of inverse output terminal are respectively used to the input of described reference current to control selection, determine that the reference current of described comparing unit access is transient state reference current or stable state reference current;
The second counter, the reset terminal of described the second counter is connected with the inverse output terminal of described flip-flop element, and the reversed-phase output of described flip-flop element provides the second reset signal for described the second counter; The input end of clock of described the second counter is connected with the input end of clock of described the first counter; Meanwhile, the output of described the second counter provides the 3rd reset signal for described flip-flop element; When described sample rate current is during higher than stable state reference current, described the second counter works, the time that described the second counter is write all over is for allowing sample rate current to surpass the overcurrent time of stable state reference current.
2. circuit according to claim 1, is characterized in that, the forward output of described flip-flop element is used for controlling the described stable state reference current of access; The inverse output terminal of described flip-flop element is used for controlling the described transient state reference current of access.
3. circuit according to claim 1, it is characterized in that, described flip-flop element comprise one or and a d type flip flop, the output signal of described the second counter and the power-on reset signal of current limit circuit become the reset signal of d type flip flop by access or pupil;
When described supply voltage is during lower than threshold voltage, described d type flip flop is in reset mode; When described supply voltage is higher than threshold voltage and described the second counter during in reset mode, described d type flip flop is in running order.
4. circuit according to claim 3, is characterized in that, described flip-flop element also comprises an inverter, is connected with the forward output of described d type flip flop, makes the output of described inverter form the inverse output terminal of described flip-flop element.
5. circuit according to claim 1, is characterized in that, after circuit electrification reset, the reference current signal of the access of described comparator is transient state reference current signal; When sample rate current is during higher than transient current, described comparing unit generated flow control signals, and the output of controlling external circuit is restricted to transient current; And, described the first counter is started working, after described the first counter is write all over, the input end of clock of described flip-flop element receives the rising edge clock signal of described the first timer output, the forward output output digit signals high level of described flip-flop element, the reference current signal of the access of comparator is stable state reference current signal described in FEEDBACK CONTROL; The inverse output terminal output digit signals low level of described flip-flop element, the second counter enters operating state described in FEEDBACK CONTROL.
6. circuit according to claim 5, it is characterized in that, after the reference current signal of the access of described comparator is stable state reference current signal, when sample rate current is during higher than steady-state current, described comparing unit generated flow control signals, and the output current of controlling external circuit is restricted to steady-state current; After described the second counter is write all over, the reset terminal of described flip-flop element receives the rising edge clock signal of described the second timer output and resets, the forward output output digit signals low level of described flip-flop element, the inverse output terminal output digit signals high level of described flip-flop element, the reference current signal of the access of comparator described in FEEDBACK CONTROL is transient state reference current signal, and described in FEEDBACK CONTROL, the second counter resets.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320594163.8U CN203482089U (en) | 2013-09-25 | 2013-09-25 | Current limiting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320594163.8U CN203482089U (en) | 2013-09-25 | 2013-09-25 | Current limiting circuit |
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|---|---|
| CN203482089U true CN203482089U (en) | 2014-03-12 |
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| CN201320594163.8U Withdrawn - After Issue CN203482089U (en) | 2013-09-25 | 2013-09-25 | Current limiting circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490396A (en) * | 2013-09-25 | 2014-01-01 | 无锡中星微电子有限公司 | Current limiting circuit |
| CN104466890A (en) * | 2014-12-05 | 2015-03-25 | 青岛鼎信通讯股份有限公司 | Over-current protection control circuit |
| CN104967389A (en) * | 2015-06-30 | 2015-10-07 | 广东美的制冷设备有限公司 | Overcurrent protection method and overcurrent protection device for motor driver |
| CN105634260A (en) * | 2016-01-30 | 2016-06-01 | 深圳南云微电子有限公司 | Output short-circuit protection method and circuit |
| CN110311351A (en) * | 2019-07-17 | 2019-10-08 | 易视智瞳科技（深圳）有限公司 | Current foldback circuit and load circuit |
| CN111262228A (en) * | 2018-12-03 | 2020-06-09 | 华大半导体有限公司 | Current-limiting protection device and motor driving chip |
-
2013
- 2013-09-25 CN CN201320594163.8U patent/CN203482089U/en not_active Withdrawn - After Issue
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103490396A (en) * | 2013-09-25 | 2014-01-01 | 无锡中星微电子有限公司 | Current limiting circuit |
| CN103490396B (en) * | 2013-09-25 | 2016-08-24 | 无锡中感微电子股份有限公司 | A kind of current limit circuit |
| CN104466890A (en) * | 2014-12-05 | 2015-03-25 | 青岛鼎信通讯股份有限公司 | Over-current protection control circuit |
| CN104466890B (en) * | 2014-12-05 | 2017-08-11 | 青岛鼎信通讯股份有限公司 | A kind of overcurrent protection controls circuit |
| CN104967389A (en) * | 2015-06-30 | 2015-10-07 | 广东美的制冷设备有限公司 | Overcurrent protection method and overcurrent protection device for motor driver |
| CN104967389B (en) * | 2015-06-30 | 2017-11-14 | 广东美的制冷设备有限公司 | The over-current protection method and device of motor driver |
| CN105634260A (en) * | 2016-01-30 | 2016-06-01 | 深圳南云微电子有限公司 | Output short-circuit protection method and circuit |
| CN105634260B (en) * | 2016-01-30 | 2019-02-05 | 深圳南云微电子有限公司 | Output short circuit protection circuit |
| CN111262228A (en) * | 2018-12-03 | 2020-06-09 | 华大半导体有限公司 | Current-limiting protection device and motor driving chip |
| CN111262228B (en) * | 2018-12-03 | 2022-06-28 | 华大半导体有限公司 | Current-limiting protection device and motor driving chip |
| CN110311351A (en) * | 2019-07-17 | 2019-10-08 | 易视智瞳科技（深圳）有限公司 | Current foldback circuit and load circuit |
| CN110311351B (en) * | 2019-07-17 | 2022-05-03 | 易视智瞳科技（深圳）有限公司 | Overcurrent protection circuit and load circuit |
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Address after: A 530 Taihu international science and Technology Park building 214135 Qingyuan Road in Jiangsu province Wuxi City District 10 layer Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: A 530 Taihu international science and Technology Park building 214135 Qingyuan Road in Jiangsu province Wuxi City District 10 layer Patentee before: Wuxi Vimicro Co., Ltd. |
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