CN211377868U - Dormancy detection circuitry - Google Patents
Dormancy detection circuitry Download PDFInfo
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- CN211377868U CN211377868U CN201921823473.6U CN201921823473U CN211377868U CN 211377868 U CN211377868 U CN 211377868U CN 201921823473 U CN201921823473 U CN 201921823473U CN 211377868 U CN211377868 U CN 211377868U
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Abstract
The utility model relates to a detection circuitry especially relates to a dormancy detection circuitry, include: the working circuit is connected between the voltage input end and the voltage output end; the input end of the drive control unit is connected to the voltage input end; the switching device group is connected between the output end of the driving control unit and the input end of the working circuit, the input end of the zero current detection unit is connected with the input end of the energy storage element, and the output end of the zero current detection unit is connected to the first input end of the driving control unit; the input end of the average current detection unit is connected to the two ends of the detection resistor, and the output end of the average current detection unit is connected to the second input end of the drive control unit. Has the advantages that: the zero current detection unit is added, so that under-voltage detection is completed when the power supply voltage is higher, the problem of reference voltage error is avoided, the occurrence of misjudgment is reduced, the problem of reverse current is avoided by adding the average current detection unit, and the dormant state can be correctly identified.
Description
Technical Field
The utility model relates to a detection circuitry especially relates to a dormancy detection circuitry.
Background
In some application scenarios of the inductive energy storage type DCDC switching converter, when the power supply voltage is low, the system needs to be closed timely to prevent unexpected uncertain conditions, and then the system enters a sleep state to indicate that the power supply is withdrawn; for example, for a charging chip, when the charger is pulled out, a system indication, a power source pull-out or a power source undervoltage need to be given in time.
In the process of power supply voltage drop, an under-voltage indication signal is not monotonous possibly due to the nonlinearity of some circuits, that is, an error condition exists in a certain voltage interval, in the application scene of some inductance energy storage type DCDC switching converters, the condition that the current is reversely poured from an output power supply to an input power supply occurs due to the existence of inductance and the existence of reverse current when the power supply is removed, the current supplement of the input power supply is caused, and the condition of under-voltage cannot be detected all the time.
Disclosure of Invention
To solve the above problems in the prior art, a sleep detection circuit is provided, which has the following specific technical scheme:
a sleep detection circuit, comprising:
a voltage input terminal;
a voltage output terminal;
the working circuit is connected between the voltage input end and the voltage output end;
the input end of the driving control unit is connected to the voltage input end;
the switching device group is connected between the output end of the driving control unit and the input end of the working circuit, the output end of the working circuit is connected to the voltage output end, and an energy storage element and a detection resistor are arranged in the working circuit;
the input end of the zero current detection unit is connected with the input end of the energy storage element, and the output end of the zero current detection unit is connected to the first input end of the drive control unit;
and the input end of the average current detection unit is connected to the two ends of the detection resistor, and the output end of the average current detection unit is connected to the second input end of the drive control unit so as to detect the average current of the detection resistor.
Preferably, the drive control unit includes:
the input end of the low-voltage locking unit is connected with the voltage input end;
the input end of the circuit control unit is connected with the output end of the low-voltage locking unit;
the input end of the pulse driving unit is connected with the output end of the circuit control unit; the output end of the pulse driving unit is connected with the switch device group so as to drive the switch device group to trigger.
Preferably, the switching device group includes:
the drain electrode of the first switching tube is connected with the voltage input end, the grid electrode of the first switching tube is connected with the output end of the pulse driving unit, and the source electrode of the first switching tube is connected with the input end of the working circuit;
and the drain electrode of the second switch tube is connected with the input end of the working circuit, the grid electrode of the second switch tube is connected with the output end of the pulse driving unit, and the source electrode of the first switch tube is connected with the grounding end.
Preferably, the output terminal of the drive control unit includes:
the first output end is connected with the grid electrode of the first switching tube so as to output a high-frequency pulse signal;
and the second output end is connected with the grid electrode of the second switching tube so as to output a low-frequency pulse signal.
Preferably, the sleep detection circuit further includes: a first power supply connected between the voltage input terminal and the ground terminal.
Preferably, the sleep detection circuit further comprises a load power supply, and the load power supply is connected between the voltage output end and the ground end.
Preferably, the sleep detection circuit further includes:
the first regulating circuit is connected between the voltage input end and the grounding end;
and the second regulating circuit is connected between the voltage output end and the grounding end.
Preferably, the first adjusting circuit includes: and the first resistor is connected between the voltage input end and the grounding end through a first capacitor.
Preferably, the second adjusting circuit includes: and the second resistor is connected between the voltage output end and the grounding end through a second capacitor.
Has the advantages that: the zero current detection unit is added, so that under-voltage detection is completed at a higher point of the power voltage, the problem of reference voltage error is avoided, the occurrence of misjudgment can be reduced, the problem of reverse current is effectively avoided by adding the average current detection unit, and the dormant state can be correctly identified.
Drawings
Fig. 1 is a prior art circuit diagram of a sleep detection circuit according to the present invention;
fig. 2 is a circuit diagram of a sleep detection circuit according to the present invention;
a voltage input terminal 1; a voltage output terminal 2; an operating circuit 3; a drive control unit 4; a low-voltage locking unit 41; the circuit control unit 42; a pulse drive unit 43; a first output terminal 431; a second output terminal 432; a switch device group 5; a first switching tube 51; a second switching tube 52; an energy storage element 31; a sense resistor 32; a zero current detection unit 6; an average current detection unit 7; a first power supply 8; a load power supply 9; a first regulating circuit 10; a second regulating circuit 11.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention will be further described with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.
A sleep detection circuit, comprising:
a voltage input terminal 1;
a voltage output terminal 2;
the working circuit 3 is connected between the voltage input end 1 and the voltage output end 2;
a driving control unit 4, wherein the input end of the driving control unit 4 is connected to the voltage input end 1;
a switch device group 5 connected between the output end of the driving control unit 4 and the input end of the working circuit 3, the output end of the working circuit 3 is connected to the voltage output end 2, and an energy storage element 31 and a detection resistor 32 are arranged in the working circuit 3;
the input end of the zero current detection unit 6 is connected with the input end of the energy storage element 31, and the output end of the zero current detection unit 6 is connected to the first input end of the driving control unit 4;
an average current detection unit 7, an input end of the average current detection unit 7 is connected to two ends of the detection resistor 32, and an output end of the average current detection unit 7 is connected to a second input end of the driving control unit 4 to detect the average current of the detection resistor 32.
Specifically, as shown in fig. 2, this is a step-down topology, the voltage input terminal 1 is a power source of the charger, when the charger is unplugged, the charging current to the voltage output terminal 2 is reduced, when the current approaches 0, because the zero current detection unit 6 prevents the current from being turned over, but because of the detection accuracy problem of the zero current detection unit 6, a certain reverse current also flows from the voltage output terminal 2 to the voltage input terminal 1, because the voltage input terminal 1 has the first capacitor C1, the voltage of the voltage input terminal 1 is not reduced, and the system does not enter the sleep state.
In the technical scheme, the zero current detection unit 6 and the average current detection unit 7 are additionally arranged to detect the under-voltage dormancy when the power supply voltage is higher, so that the influence of the power supply voltage on the reference voltage is avoided, and the problem of misjudgment can be effectively avoided because the operation is carried out after the average current is detected.
In a preferred embodiment, the drive control unit 4 comprises:
the input end of the low-voltage locking unit 41 is connected with the voltage input end 1;
a circuit control unit 42, wherein the input end of the circuit control unit 42 is connected with the output end of the low-voltage locking unit 42;
a pulse driving unit 43, wherein the input end of the pulse driving unit 43 is connected with the output end of the circuit control unit 42; the output terminal of the pulse driving unit 43 is connected to the switching device group 5 to drive the triggering of the switching device group.
In a preferred embodiment, the switch device group 5 includes:
a first switch tube 51, the drain of the first switch tube 51 is connected to the voltage input terminal 1, the gate of the first switch tube 51 is connected to the output terminal of the pulse driving unit 43, and the source of the first switch tube 51 is connected to the input terminal of the working circuit 3;
a second switch tube 52, the drain of the second switch tube 52 is connected to the input terminal of the working circuit 3, the gate of the second switch tube 52 is connected to the output terminal of the pulse driving unit 43, and the source of the first switch tube 51 is connected to the ground terminal.
Specifically, the switching device group 5 is formed by alternately opening the first switching tube 51 and the second switching tube 52 to realize energy transfer, and the detection current of the average current detection unit 7 is full, and is detected no matter when the first switching tube 51 or the second switching tube 52 is turned on.
In a preferred embodiment, the output of the drive control unit 43 comprises:
a first output end 431, wherein the first output end 431 is connected to the gate of the first switch tube 51 for outputting a high frequency pulse signal;
a second output terminal 432, the second output terminal 432 is connected to the gate of the second switch tube 52 for outputting a low frequency pulse signal.
In a preferred embodiment, the sleep detection circuit further comprises: a first power supply 8, the first power supply 8 is connected between the voltage input terminal 1 and the ground terminal.
In a preferred embodiment, the sleep detection circuit further comprises a load power supply 9, and the load power supply 9 is connected between the voltage output terminal 2 and the ground terminal.
In a preferred embodiment, the sleep detection circuit further comprises:
a first adjusting circuit 10, the first adjusting circuit 10 is connected between the voltage input terminal 1 and the ground terminal;
and the second regulating circuit 11, the second regulating circuit 11 is connected between the voltage output end 2 and the ground end.
In a preferred embodiment, the first regulating circuit 10 comprises: a first resistor R1, the first resistor R1 is connected between the voltage input terminal 1 and the ground terminal through a first capacitor C1.
In a preferred embodiment, the second regulating circuit 11 comprises: a second resistor R2, the second resistor R2 is connected between the voltage output terminal 2 and the ground terminal through a second capacitor C2.
Has the advantages that: the zero current detection unit is added, so that under-voltage detection is completed at a higher point of the power voltage, the problem of reference voltage error is avoided, the occurrence of misjudgment can be reduced, the problem of reverse current is effectively avoided by adding the average current detection unit, and the dormant state can be correctly identified.
The above description is only an example of the preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and those skilled in the art should be able to realize the equivalent alternatives and obvious variations of the present invention.
Claims (9)
1. A sleep detection circuit, comprising:
a voltage input terminal;
a voltage output terminal;
the working circuit is connected between the voltage input end and the voltage output end;
the input end of the driving control unit is connected to the voltage input end;
the switching device group is connected between the output end of the driving control unit and the input end of the working circuit, the output end of the working circuit is connected to the voltage output end, and an energy storage element and a detection resistor are arranged in the working circuit;
the input end of the zero current detection unit is connected with the input end of the energy storage element, and the output end of the zero current detection unit is connected to the first input end of the drive control unit;
and the input end of the average current detection unit is connected to the two ends of the detection resistor, and the output end of the average current detection unit is connected to the second input end of the drive control unit so as to detect the average current of the detection resistor.
2. The sleep detection circuit according to claim 1, wherein the drive control unit comprises:
the input end of the low-voltage locking unit is connected with the voltage input end;
the input end of the circuit control unit is connected with the output end of the low-voltage locking unit;
the input end of the pulse driving unit is connected with the output end of the circuit control unit; the output end of the pulse driving unit is connected with the switch device group so as to drive the switch device group to trigger.
3. The sleep detection circuit as claimed in claim 2, wherein the switch device group comprises:
the drain electrode of the first switching tube is connected with the voltage input end, the grid electrode of the first switching tube is connected with the output end of the pulse driving unit, and the source electrode of the first switching tube is connected with the input end of the working circuit;
and the drain electrode of the second switch tube is connected with the input end of the working circuit, the grid electrode of the second switch tube is connected with the output end of the pulse driving unit, and the source electrode of the first switch tube is connected with the grounding end.
4. The sleep detection circuit as claimed in claim 3, wherein the output terminal of the driving control unit comprises:
the first output end is connected with the grid electrode of the first switching tube so as to output a high-frequency pulse signal;
and the second output end is connected with the grid electrode of the second switching tube so as to output a low-frequency pulse signal.
5. The sleep detection circuit as claimed in claim 3, further comprising: a first power supply connected between the voltage input terminal and the ground terminal.
6. The sleep detection circuit as claimed in claim 5, further comprising a load power supply connected between the voltage output terminal and the ground terminal.
7. The sleep detection circuit as claimed in claim 6, further comprising:
the first regulating circuit is connected between the voltage input end and the grounding end;
and the second regulating circuit is connected between the voltage output end and the grounding end.
8. The sleep detection circuit as claimed in claim 7, wherein the first adjusting circuit comprises: and the first resistor is connected between the voltage input end and the grounding end through a first capacitor.
9. The sleep detection circuit as claimed in claim 7, wherein the second regulation circuit comprises: and the second resistor is connected between the voltage output end and the grounding end through a second capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921823473.6U CN211377868U (en) | 2019-10-28 | 2019-10-28 | Dormancy detection circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921823473.6U CN211377868U (en) | 2019-10-28 | 2019-10-28 | Dormancy detection circuitry |
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| Publication Number | Publication Date |
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| CN211377868U true CN211377868U (en) | 2020-08-28 |
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| CN201921823473.6U Active CN211377868U (en) | 2019-10-28 | 2019-10-28 | Dormancy detection circuitry |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116736076A (en) * | 2023-05-12 | 2023-09-12 | 珠海妙存科技有限公司 | Chip dormancy state detection method and system, electronic equipment and storage medium |
-
2019
- 2019-10-28 CN CN201921823473.6U patent/CN211377868U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116736076A (en) * | 2023-05-12 | 2023-09-12 | 珠海妙存科技有限公司 | Chip dormancy state detection method and system, electronic equipment and storage medium |
| CN116736076B (en) * | 2023-05-12 | 2024-04-09 | 珠海妙存科技有限公司 | Chip dormancy state detection method and system, electronic equipment and storage medium |
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