CN203445120U - Array substrate and display apparatus - Google Patents
Array substrate and display apparatus Download PDFInfo
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- CN203445120U CN203445120U CN201320526664.2U CN201320526664U CN203445120U CN 203445120 U CN203445120 U CN 203445120U CN 201320526664 U CN201320526664 U CN 201320526664U CN 203445120 U CN203445120 U CN 203445120U
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Abstract
The embodiments of the utility model disclose an array substrate and a display apparatus and relate to the technical field of displaying. The array substrate comprises a base substrate, a gate line, a data line, and a film transistor y, a pixel electrode and a passivation layer which are arranged on the base substrate in an array. The film transistor comprises a gate, an active layer, a source electrode and a drain electrode. The pixel electrode, the source electrode and the drain electrode are arranged at the same layer and are integrally molded. The array substrate and the display apparatus are applied to a liquid crystal display and have the advantages of simplified array substrate structure, reduced composition frequency of an array substrate manufacturing process, and improved array substrate yield.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of array base palte and display unit.
Background technology
Liquid crystal display is a kind of display device of planar ultra-thin, it has, and volume is little, thin thickness, lightweight, power consumption less, the advantage such as radiation is low, be widely used in various electronic display units.The display effect of liquid crystal display mainly determines by display panels, and display panels mainly comprises array base palte, color membrane substrates and the layer of liquid crystal molecule between two substrates.Wherein, array base palte has determined response time and the display effect of display panels to a great extent.
On array base palte, generally include the structures such as thin-film transistor, pixel electrode, wherein thin-film transistor specifically comprises the structures such as grid, active layer, source electrode, drain electrode.In bottom gate thin film transistor array base palte manufacturing process, conventionally need 5 composition techniques to form respectively grid, active layer, source electrode and drain electrode, drain via and pixel electrode.The making of top gate type thin film transistor array base palte needs through more complicated composition technique to form each layer of structure.
Utility model people finds, traditional array base-plate structure is complicated, need to could make formation through composition technique repeatedly, and cost is higher, and repeatedly in composition technique, has bit errors problem, has reduced the yields of array base palte.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of array base palte and display unit, can simplify the structure of array base palte, reduces the composition number of times in array base palte manufacturing process, has improved the yields of array base palte.
For solving the problems of the technologies described above, a kind of array base palte that the utility model embodiment provides adopts following technical scheme:
A kind of array base palte, comprise underlay substrate, grid line, data wire, array arrangement thin-film transistor, pixel electrode and the passivation layer on described underlay substrate, described thin-film transistor comprises grid, active layer, source electrode and drain electrode, and described pixel electrode and described active layer, described drain electrode arrange with layer and be one-body molded.
Described thin-film transistor is bottom gate thin film transistor, described array base palte comprises described grid line and the described grid being positioned on described underlay substrate, be positioned at the first insulating barrier on described grid line and described grid, be positioned at the described active layer on described the first insulating barrier, described drain electrode and described pixel electrode, be positioned at described data wire and described source electrode on described active layer, described drain electrode and described pixel electrode, and be positioned at the described passivation layer on described data wire and described source electrode, wherein, the source electrode of described thin-film transistor connects described active layer.
Described thin-film transistor is top gate type thin film transistor, described array base palte comprises the described active layer being positioned on described underlay substrate, described drain electrode and described pixel electrode, be positioned at described active layer, the first insulating barrier on described drain electrode and described pixel electrode, be positioned at described grid line and grid on described the first insulating barrier, be positioned at the second insulating barrier on described grid line and described grid, be positioned at described data wire and described source electrode on described the second insulating barrier, and be positioned at the described passivation layer on described data wire and described source electrode, wherein, described the first insulating barrier and described the second insulating barrier are provided with the via hole of corresponding described active layer, the source electrode of described thin-film transistor connects described active layer by described via hole.
Described thin-film transistor is bottom gate thin film transistor, and described passivation layer also comprises the opening of corresponding described pixel electrode.
Described thin-film transistor is top gate type thin film transistor, and described the first insulating barrier, described the second insulating barrier and described passivation layer also comprise the opening of corresponding described pixel electrode.
Described array base palte also comprises: be positioned at the public electrode on described passivation layer.
On described public electrode, there is slit.
The material of described active layer, described drain electrode and described pixel electrode is oxide semiconductor material; The thickness of described active layer, described drain electrode and described pixel electrode is
Above-described embodiment provides a kind of array base palte, and this array base palte comprises having structure as above.On this array base palte, pixel electrode, active layer and drain electrode, with layer setting and one-body molded, have been simplified the structure of array base palte, in the manufacturing process of array base palte, can effectively reduce composition technique number of times, have saved cost.Meanwhile, also avoided the repeatedly bit errors problem of composition technique problem, improved the yields of array base palte, the display floater of applying this array base palte has better display effect.
The utility model embodiment also provides a kind of display unit, comprises array base palte as above.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is a kind of bottom gate thin film transistor array base palte plane graph in the utility model embodiment;
Fig. 2 is that the bottom gate thin film transistor array base palte shown in the Fig. 1 in the utility model embodiment is along the profile of I-I ' direction;
Fig. 3 is the manufacture method flow chart of array base palte in the utility model embodiment;
Fig. 4 is the another kind of bottom gate thin film transistor array base palte schematic diagram in the utility model embodiment;
Fig. 5 is the manufacture method flow chart of the bottom gate thin film transistor array base palte in the utility model embodiment;
Fig. 6 is a kind of top gate type thin film transistor array base palte plane graph in the utility model embodiment;
Fig. 7 is that a kind of top gate type thin film transistor array base palte shown in the Fig. 6 in the utility model embodiment is along the profile of I-I ' direction;
Fig. 8 is the another kind of top gate type thin film transistor array base palte schematic diagram in the utility model embodiment;
Fig. 9 is the manufacture method flow chart of the top gate type thin film transistor array base palte in the utility model embodiment;
Figure 10 is the senior super dimension of a kind of bottom gate thin film transistor in a utility model embodiment switch technology type array base palte plane graph;
Figure 11 is that the senior super dimension of the bottom gate thin film transistor shown in the Figure 10 in a utility model embodiment switch technology type array base palte is along the profile of I-I ' direction;
Figure 12 is the manufacture method flow chart of the senior super dimension of the bottom gate thin film transistor in a utility model embodiment switch technology type array base palte;
Figure 13 is the senior super dimension of the top gate type thin film transistor in a utility model embodiment switch technology type array base palte plane graph;
Figure 14 is that the senior super dimension of the top gate type thin film transistor shown in the Figure 13 in a utility model embodiment switch technology type array base palte is along the profile of I-I ' direction;
Figure 15 is the manufacture method flow chart of the senior super dimension of the top gate type thin film transistor in a utility model embodiment switch technology type array base palte.
Description of reference numerals:
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment mono-
The utility model embodiment provides a kind of array base palte, as depicted in figs. 1 and 2, this array base palte comprises underlay substrate 10, grid line 20, data wire 60, array arrangement thin-film transistor 1, pixel electrode 33 and the passivation layer 71 on described underlay substrate, described thin-film transistor 1 comprises grid 21, active layer 31, source electrode 61 and drains 32, described pixel electrode 33 and described active layer 31, the same layer setting of described drain electrode 32 and one-body molded.
Above-described embodiment provides a kind of array base palte, and this array base palte comprises having structure as above.On this array base palte, pixel electrode, active layer and drain electrode, with layer setting and one-body molded, have been simplified the structure of array base palte, in the manufacturing process of array base palte, can effectively reduce composition technique number of times, have saved cost.Meanwhile, also avoided the repeatedly bit errors problem of composition technique problem, improved the yields of array base palte, the display floater of applying this array base palte has better display effect.
Wherein, the active layer 31 arranging with layer, drain 32 and pixel electrode 33 be same metal-oxide semiconductor (MOS).In prior art, active layer 31 is selected the semi-conducting materials such as polysilicon, amorphous silicon conventionally, drains 32 conventionally to select the metals such as chromium, molybdenum, copper, and pixel electrode 33 is selected the electrically conducting transparent things such as tin indium oxide, indium zinc oxide conventionally.In the utility model embodiment, active layer 31, drain 32 and pixel electrode 33 select same metal-oxide semiconductor (MOS), metal-oxide semiconductor (MOS) can have good conductivity in the operating voltage range of display panels, there is good light transmission simultaneously, thereby can meet active layer 31, drain 32 and the performance requirement of 33 pairs of selected materials of pixel electrode simultaneously.The metal-oxide semiconductor (MOS) of selecting in the utility model embodiment can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.
Further, as shown in Figure 1, select metal-oxide semiconductor (MOS) as the film crystal pipe unit 1 of active layer 31 and drain electrode 32, to be positioned at the infall of grid line 20 and data wire 60.Wherein, the grid line 20 of array base palte and grid 21 arrange with layer and are one-body molded, and the data wire 60 of array base palte and source electrode 61 arrange with layer and be one-body molded.The region contacting with active layer 31 in data wire 60 is the source electrode 61 of film crystal pipe unit 1.
It should be noted that, active layer 31, drain 32 and the relative position of pixel electrode 33 be not limited to the position that in Fig. 1 and Fig. 2, dotted line separates, three's concrete relative position can regulate according to actual conditions, the utility model embodiment does not do concrete restriction to this.
Similarly, active layer 31, drain 32 and the shape of pixel electrode 33 be also not limited to the shape shown in Fig. 1 and Fig. 2, also can be according to actual conditions adjustment.For example, on pixel electrode 33, can there is the edge of slit, pixel electrode 33 can have on zigzag fashion or pixel electrode 33 and can there are other fine patterns.
Further, the active layer 31 arranging with layer, drain 32 and the thickness of pixel electrode 33 be preferably
active layer 31, drain 32 and the thickness of pixel electrode 33 can regulate according to actual conditions, the utility model embodiment does not limit this.
In addition, the utility model embodiment also provides a kind of display unit, and this display unit comprises array base palte as above.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, organic LED panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Embodiment bis-
The utility model embodiment also provides a kind of manufacture method of array base palte, this array base palte comprises underlay substrate, grid line, data wire, array arrangement thin-film transistor, pixel electrode and the passivation layer on underlay substrate, and thin-film transistor comprises grid, active layer, source electrode and drain electrode.
As shown in Figure 3, this manufacture method comprises:
Step S301, formation comprise the figure of active layer and drain electrode and pixel electrode, and pixel electrode and active layer, drain electrode arrange with layer and be one-body molded.
Particularly, first, can on array base palte, form a layer thickness by methods such as sputters and be preferably
metal oxide semiconductor layer.Wherein metal-oxide semiconductor (MOS) can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.
Secondly, on metal oxide semiconductor layer, apply one deck photoresist, use comprises active layer 31, drain 32 and the mask plate of pixel electrode 33 figures hide, through a composition technique, on array base palte, form the active layer 31 that arranges with layer, drain 32 and pixel electrode 33.The active layer 31 forming, drain 32 and pixel electrode 33 with layer, arrange and one-body molded.
Similarly, the grid line 20 of array base palte and grid 21 arrange with layer and are one-body molded, and the data wire 60 of array base palte and source electrode 61 arrange with layer and be one-body molded.
Above-described embodiment provides a kind of manufacture method of array base palte, and this manufacture method comprises that formation comprises the figure of active layer and drain electrode and pixel electrode; Pixel electrode and active layer, drain electrode arrange with layer and are one-body molded.This manufacture method can be made array base palte through less composition technique number of times, and technique is simple, and cost is lower, has reduced the bit errors problem of array base palte in manufacturing process, and the array base palte yields of making is higher.
Embodiment tri-
The thin-film transistor arranging on array base palte can be bottom gate thin film transistor, can be also top gate type thin film transistor, and when the thin-film transistor type that arranges on array base palte is different, structure of array base palte and preparation method thereof is also different.
The utility model embodiment provides a kind of bottom gate thin film transistor array base palte, as depicted in figs. 1 and 2.
This array base palte comprises: be positioned at grid line 20 and grid 21 on underlay substrate 10, be positioned at the first insulating barrier 22 on grid line 20 and grid 21, be positioned at active layer 31 on the first insulating barrier 22, drain 32 and pixel electrode 33, be positioned at active layer 31, drain 32 and pixel electrode 33 on data wire 60 and source electrode 61, the source electrode 61 of thin-film transistor 1 connects active layer 31, and is positioned at the passivation layer on data wire 60 and source electrode 61.
Particularly, the structure of this array base palte is as follows:
Be positioned at grid line 20 and grid 21 on underlay substrate 10, grid line 20 and grid 21 can be also sandwich construction for single layer structure.When grid line 20 and grid 21 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When grid line 20 and grid 21 are sandwich construction, can be copper titanium, copper molybdenum, molybdenum aluminium molybdenum etc.The thickness of grid line 20 and grid 21 is preferably
grid line 20 and grid 21 can be located immediately on underlay substrate 10, also can between grid line 20 and grid 21 and underlay substrate 10, resilient coating be set, and resilient coating can be silicon nitride or silica.
The first insulating barrier 22, the first insulating barriers 22 that are positioned on grid line 20 and grid 21 can be the materials such as silicon nitride, silica or silicon oxynitride, and it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the first insulating barrier 22 is preferably
Be positioned on the first insulating barrier 22 active layer 31 that arranges with layer, drain 32 and pixel electrode 33, active layer 31, drain 32 and pixel electrode 33 be same metal-oxide semiconductor (MOS), can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.In addition the active layer 31 arranging with layer,, drain 32 and the thickness of pixel electrode 33 be preferably
Be positioned at active layer 31, drain 32 and pixel electrode 33 on data wire 60 and source electrode 61, data wire 60 and source electrode 61 can be also sandwich construction for single layer structure.When data wire 60 and source electrode 61 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When data wire 60 and source electrode 61 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.Further, the thickness of data wire 60 and source electrode 61 is preferably
Be positioned at the passivation layer 71 on data wire 60 and source electrode 61, passivation layer 71 can be the single layer structure of silicon nitride, silica or silicon oxynitride, can be also the double-decker of silicon nitride or silica formation.In addition, can also select organic resin as passivation layer 71 material used, such as acrylic resin, polyimides and polyamide etc.The thickness of passivation layer 71 is preferably
Further, as shown in Figure 4, in order to reduce the thickness between pixel electrode 33 and layer of liquid crystal molecule, further reduce the operating voltage that drives liquid crystal molecule, the opening 72 of respective pixel electrode 33 can be set on passivation layer 71.
The utility model embodiment also provides the manufacture method of the bottom gate thin film transistor array base palte shown in a kind of Fig. 1 and Fig. 2, and as shown in Figure 5, this manufacture method comprises:
Step S501, on underlay substrate, form the figure comprise grid line and grid.
First, can on underlay substrate 10, form by methods such as sputter, thermal evaporations one deck grid metal film.Before forming grid metal film, can on underlay substrate 10, first form one deck resilient coating.
Secondly, apply one deck photoresist on grid metal film, use to have to comprise that the mask plate of grid line 20 and grid 21 figures hides, then expose, development, etching, last stripping photoresist, forms the figure that comprises grid line 20 and grid 21.
Step S502, on the figure of grid line and grid, form the first insulating barrier.
Can on the figure of grid line 20 and grid 21, form by methods such as plasma enhanced chemical vapor depositions the first insulating barrier 22.
Step S503, on the first insulating barrier, form the figure of active layer and drain electrode and pixel electrode.
First, can on the first insulating barrier 22, form layer of metal oxide semiconductor by methods such as sputters.
Secondly, on metal-oxide semiconductor (MOS), apply one deck photoresist, then use have comprise active layer 31, drain 32 and the mask plate of the figure of pixel electrode 33 hide, expose, development and etching, last stripping photoresist, forms comprising active layer 31, draining 32 and the figure of pixel electrode 33 of arranging with layer.
Step S504, on the figure of active layer and drain electrode and pixel electrode, form the figure comprise data wire and source electrode, source electrode connects active layer.
First, can be by methods such as sputter or thermal evaporations, active layer 31, drain 32 and pixel electrode 33 on form one deck data wire metal film.
Secondly, on data wire metal film, apply one deck photoresist, then use the mask plate with the figure that comprises data wire 60 and source electrode 61 to hide, expose, development and etching, last stripping photoresist, forms data wire 60 and source electrode 61, and wherein source electrode 61 is directly connected with active layer 31.
Step S505, on the figure of data wire and source electrode, form passivation layer.
When passivation layer 71 materials are the materials such as silicon nitride, silica, can on the figure of data wire 60 and source electrode 61, form by methods such as plasma enhanced chemical vapor depositions one deck passivation layer 71; When passivation layer 71 materials are organic resin, directly organic resin is coated on data wire 60 and source electrode 61, form passivation layer 71.
Further, can also on passivation layer 71, apply one deck photoresist, use the mask plate of the figure with the opening 72 that comprises respective pixel electrode 33 to hide, through a composition technique, the opening 72 that forms respective pixel electrode 33 on passivation layer 71, comes out pixel electrode 33.
Embodiment tetra-
The utility model embodiment provides a kind of top gate type thin film transistor array base palte, as shown in Figure 6 and Figure 7.
Top gate type thin film transistor array base palte comprises: be positioned at the active layer 31 on underlay substrate 10, drain electrode 32 and pixel electrode 33, be positioned at active layer 31, the first insulating barrier 22 on drain electrode 32 and pixel electrode 33, be positioned at grid line 20 and grid 21 on the first insulating barrier 22, be positioned at the second insulating barrier 41 on grid line 20 and grid 21, be positioned at data wire 60 and source electrode 61 on the second insulating barrier 41, and be positioned at the passivation layer 71 on data wire 60 and source electrode 61, wherein, the first insulating barrier 22 and the second insulating barrier 41 are provided with the via hole 51 of corresponding active layer 31, the source electrode 61 of thin-film transistor connects active layer 31 by via hole 51.
Particularly, the structure of this array base palte is as follows:
Be positioned at active layer 31 that the same layer on underlay substrate 10 arranges, drain 32 and pixel electrode 33, active layer 31, drain 32 and pixel electrode 33 be same metal-oxide semiconductor (MOS), can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.In addition the active layer 31 arranging with layer,, drain 32 and the thickness of pixel electrode 33 be preferably
the active layer 31 arranging with layer, drain 32 and pixel electrode 33 can be located immediately on underlay substrate 10, also can the active layer 31 arranging with layer, drain 32 and pixel electrode 33 and underlay substrate 10 between resilient coating is set, resilient coating can be silicon nitride or silica.
Be positioned at active layer 31, drain 32 and pixel electrode 33 on the first insulating barrier 22, the first insulating barriers 22 can be the materials such as silicon nitride, silica or silicon oxynitride, it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the first insulating barrier 22 is preferably
Be positioned at grid line 20 and grid 21 on the first insulating barrier 22, grid line 20 and grid 21 can be also sandwich construction for single layer structure.When grid line 20 and grid 21 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When grid line 20 and grid 21 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.The thickness of grid line 20 and grid 21 is preferably
The second insulating barrier 41, the second insulating barriers 41 that are positioned on grid line 20 and grid 21 can be the materials such as silicon nitride, silica or silicon oxynitride, and it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the second insulating barrier 41 is preferably
The via hole 51 of the corresponding active layer 31 arranging on the first insulating barrier 22 and the second insulating barrier 41.
Be positioned at data wire 60 and source electrode 61 on the first insulating barrier 22 and the second insulating barrier 41, wherein source electrode 61 is connected with active layer 31 by via hole 51.Data wire 60 and source electrode 61 can be also sandwich construction for single layer structure.When data wire 60 and source electrode 61 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When data wire 60 and source electrode 61 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.Further, the thickness of data wire 60 and source electrode 61 is preferably
Be positioned at the passivation layer 71 on data wire 60 and source electrode 61, passivation layer 71 can be the single layer structure of silicon nitride, silica or silicon oxynitride, can be also the double-decker of silicon nitride or silica formation.In addition, can also select organic resin as passivation layer 71 material used, such as acrylic resin, polyimides and polyamide etc.The thickness of passivation layer 71 is preferably
Further, as shown in Figure 8, in order to reduce the thickness between pixel electrode 33 and layer of liquid crystal molecule, further reduce the operating voltage that drives liquid crystal molecule, the opening 72 of respective pixel electrode 33 can be set on passivation layer 71.
The utility model embodiment also provides a kind of manufacture method of top gate type thin film transistor array base palte.As shown in Figure 9, this manufacture method comprises:
Step S901, on underlay substrate, form the figure of active layer and drain electrode and pixel electrode.
First, can by methods such as sputters, on underlay substrate 10, directly form layer of metal oxide semiconductor, also can before forming metal-oxide semiconductor (MOS), first form one deck resilient coating.
Secondly, on metal-oxide semiconductor (MOS), apply one deck photoresist, then use have comprise active layer 31, drain 32 and the mask plate of the figure of pixel electrode 33 hide, expose, development and etching, last stripping photoresist, forms comprising active layer 31, draining 32 and the figure of pixel electrode 33 of arranging with layer.
Step S902, on the figure of active layer and drain electrode and pixel electrode, form the first insulating barrier.
Can by the methods such as plasma enhanced chemical vapor deposition active layer 31, drain 32 and the figure of pixel electrode 33 on form the first insulating barrier 22.
Step S903, on the first insulating barrier, form the figure comprise grid line and grid.
First, can on the first insulating barrier 22, form by methods such as sputter, thermal evaporations one deck grid metal film.
Secondly, apply one deck photoresist on grid metal film, use to have to comprise that the mask plate of grid line 20 and grid 21 figures hides, then expose, development, etching, last stripping photoresist, forms the figure that comprises grid line 20 and grid 21.
Step S904, on the figure of grid line and grid, form the second insulating barrier, the first insulating barrier and the second insulating barrier are provided with the via hole of corresponding active layer.
By methods such as plasma enhanced chemical vapor depositions, on grid line 20 and grid 21, form the second insulating barrier 41.
On the second insulating barrier 41, apply one deck photoresist, use the mask plate with via pattern to hide, then expose, development, etching, last stripping photoresist, forms the figure of the via hole 51 that comprises corresponding active layer 31.
Step S905, on the second insulating barrier, form the figure comprise data wire and source electrode, source electrode connects active layer by via hole.
First, can, by methods such as sputter or thermal evaporations, on the second insulating barrier 41, form one deck data wire metal film.
Secondly, on data wire metal film, apply one deck photoresist, then use the mask plate with the figure that comprises data wire 60 and source electrode 61 to hide, expose, development and etching, last stripping photoresist, form data wire 60 and source electrode 61, wherein source electrode 61 is connected with active layer 31 by via hole 51.
Step S906, on the figure of data wire and source electrode, form passivation layer.
When passivation layer 71 materials are the materials such as silicon nitride, silica, can on data wire 60 and source electrode 61, form by methods such as plasma enhanced chemical vapor depositions one deck passivation layer 71; When passivation layer 71 materials are organic resin, directly organic resin is coated on data wire 60 and source electrode 61, form passivation layer 71.
Further, can also on passivation layer 71, apply one deck photoresist, use the mask plate of the figure with the opening 72 that comprises respective pixel electrode 33 to hide, through a composition technique, the opening 72 that forms respective pixel electrode 33, comes out pixel electrode 33.
Embodiment five
Further, array base palte can also be a senior super dimension switch technology type array base palte, wherein, a senior super dimension switch technology type array base palte also can be divided into the senior super dimension switch technology type array base palte of bottom gate thin film transistor and the senior super dimension of a top gate type thin film transistor switch technology type array base palte.
The utility model embodiment provides the senior super dimension of an a kind of bottom gate thin film transistor switch technology type array base palte, as shown in Figure 10 and Figure 11.
Particularly, this array base palte comprises:
Be positioned at grid line 20 and grid 21 on underlay substrate 10, grid line 20 and grid 21 can be also sandwich construction for single layer structure.When grid line 20 and grid 21 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When grid line 20 and grid 21 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.The thickness of grid line 20 and grid 21 is preferably
grid line 20 and grid 21 can be located immediately on underlay substrate 10, also can between grid line 20 and grid 21 and underlay substrate 10, resilient coating be set, and resilient coating can be silicon nitride or silica.
The first insulating barrier 22, the first insulating barriers 22 that are positioned on grid line 20 and grid 21 can be the materials such as silicon nitride, silica or silicon oxynitride, and it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the first insulating barrier 22 is preferably
Be positioned on the first insulating barrier 22 active layer 31 that arranges with layer, drain 32 and pixel electrode 33, active layer 31, drain 32 and pixel electrode 33 be same metal-oxide semiconductor (MOS), can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.In addition the active layer 31 arranging with layer,, drain 32 and the thickness of pixel electrode 33 be preferably
Be positioned at active layer 31, drain 32 and pixel electrode 33 on data wire 60 and source electrode 61, data wire 60 and source electrode 61 can be also sandwich construction for single layer structure.When data wire 60 and source electrode 61 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When data wire 60 and source electrode 61 are sandwich construction, can be copper titanium, copper molybdenum, molybdenum aluminium molybdenum etc.Further, the thickness of data wire 60 and source electrode 61 is preferably
Be positioned at the passivation layer 71 on data wire 60 and source electrode 61, passivation layer 71 can be the single layer structure of silicon nitride, silica or silicon oxynitride, can be also the double-decker of silicon nitride or silica formation.In addition, can also select organic resin as passivation layer 71 material used, such as acrylic resin, polyimides and polyamide etc.The thickness of passivation layer 71 is preferably
Be positioned at the public electrode 81 on passivation layer 71, public electrode 81 is overall structures, covers all pixels on array base palte.Public electrode 81 is transparent conductive material, can be the materials such as tin indium oxide, indium zinc oxide.The thickness of public electrode 81 is preferably
further, public electrode 81 can be set according to actual conditions with the relative position of pixel electrode 33, and the utility model embodiment does not do concrete restriction to this.For example, public electrode 81 can be positioned at the top of pixel electrode 33 on array base palte, also can be positioned at the below of pixel electrode 33.When public electrode 81 is positioned at the top of pixel electrode 33, on public electrode 81, there is slit; When public electrode 81 is positioned at the below of pixel electrode 33, on pixel electrode 33, there is slit.
The utility model embodiment also provides the manufacture method of the senior super dimension of an a kind of bottom gate thin film transistor switch technology type array base palte, and as shown in figure 12, this manufacture method comprises:
Step S1201, on underlay substrate, form the figure comprise grid line and grid.
First, can on underlay substrate 10, form by methods such as sputter, thermal evaporations one deck grid metal film.Before forming grid metal film, can on underlay substrate 10, first form one deck resilient coating.
Secondly, apply one deck photoresist on grid metal film, use to have to comprise that the mask plate of grid line 20 and grid 21 figures hides, then expose, development, etching, last stripping photoresist, forms the figure that comprises grid line 20 and grid 21.
Step S1202, on the figure of grid line and grid, form the first insulating barrier.
Can on the figure of grid line 20 and grid 21, form by methods such as plasma enhanced chemical vapor depositions the first insulating barrier 22.
Step S1203, on the first insulating barrier, form the figure of active layer and drain electrode and pixel electrode.
First, can on the first insulating barrier 22, form layer of metal oxide semiconductor by methods such as sputters.
Secondly, on metal-oxide semiconductor (MOS), apply one deck photoresist, then use have comprise active layer 31, drain 32 and the mask plate of the figure of pixel electrode 33 hide, expose, development and etching, last stripping photoresist, forms comprising active layer 31, draining 32 and the figure of pixel electrode 33 of arranging with layer.
Step S1204, on active layer and drain electrode and pixel electrode, form the figure comprise data wire and source electrode, source electrode connects active layer.
First, can be by methods such as sputter or thermal evaporations, active layer 31, drain 32 and pixel electrode 33 on form one deck data wire metal film.
Secondly, on data wire metal film, apply one deck photoresist, then use the mask plate with the figure that comprises data wire 60 and source electrode 61 to hide, expose, development and etching, last stripping photoresist, forms data wire 60 and source electrode 61, and source electrode 61 is directly connected with active layer 31.
Step S1205, on the figure of data wire and source electrode, form passivation layer.
When passivation layer 71 materials are the materials such as silicon nitride, silica, can on the figure of data wire 60 and source electrode 61, form by methods such as plasma enhanced chemical vapor depositions one deck passivation layer 71; When passivation layer 71 materials are organic resin, directly organic resin is coated on data wire 60 and source electrode 61, form passivation layer 71.
Step S1206, on passivation layer, form the figure of public electrode.
First, can, by methods such as sputter or thermal evaporations, on passivation layer 71, form one deck common electrode layer.
Secondly, apply one deck photoresist in common electrode layer, then use the mask plate of the figure with public electrode 81 to hide, expose, development and etching, last stripping photoresist, forms public electrode 81.
Step S1207, on public electrode, form slit.
On public electrode 81, apply one deck photoresist, use the mask plate with slot pattern to hide, expose, development and etching, last stripping photoresist forms slit on public electrode 81.
The manufacture method of the senior super dimension of the above a bottom gate thin film transistor switch technology type array base palte is the manufacture method that public electrode 81 is positioned at pixel electrode 33 tops, because the relative position of public electrode 81 and pixel electrode 33 can be determined according to actual conditions, so the manufacture method of the senior super dimension of a bottom gate thin film transistor switch technology type array base palte also can be determined according to actual conditions.
Embodiment six
The utility model embodiment also provides the senior super dimension of an a kind of top gate type thin film transistor switch technology type array base palte, as shown in Figure 13 and Figure 14.
Particularly, the senior super dimension of a top gate type thin film transistor switch technology type array base palte comprises:
Be positioned at active layer 31 that the same layer on underlay substrate 10 arranges, drain 32 and pixel electrode 33, active layer 31, drain 32 and pixel electrode 33 be same metal-oxide semiconductor (MOS), can be the transparent metal oxide semiconductor materials such as amorphous indium gallium zinc oxide, indium zinc oxide, zinc oxide, titanium dioxide, tin oxide, stannic acid cadmium or other metal oxides.In addition the active layer 31 arranging with layer,, drain 32 and the thickness of pixel electrode 33 be preferably
the active layer 31 arranging with layer, drain 32 and pixel electrode 33 can be located immediately on underlay substrate 10, also can the active layer 31 arranging with layer, drain 32 and pixel electrode 33 and underlay substrate 10 between resilient coating is set, resilient coating can be silicon nitride or silica.
Be positioned at active layer 31, drain 32 and pixel electrode 33 on the first insulating barrier 22, the first insulating barriers 22 can be the materials such as silicon nitride, silica or silicon oxynitride, it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the first insulating barrier 22 is
Be positioned at grid line 20 and grid 21 on the first insulating barrier 22, grid line 20 and grid 21 can be also sandwich construction for single layer structure.When grid line 20 and grid 21 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When grid line 20 and grid 21 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.The thickness of grid line 20 and grid 21 is preferably
The second insulating barrier 41, the second insulating barriers 41 that are positioned on grid line 20 and grid 21 can be the materials such as silicon nitride, silica or silicon oxynitride, and it can be single layer structure, can be also the double-decker consisting of silicon nitride or silica.In the utility model embodiment, the thickness of the second insulating barrier 41 is preferably
The via hole 51 of the corresponding active layer 31 arranging on the first insulating barrier 22 and the second insulating barrier 41.
Be positioned at data wire 60 and source electrode 61 on the first insulating barrier 22 and the second insulating barrier 41, wherein source electrode 61 is connected with active layer 31 by via hole 51.Data wire 60 and source electrode 61 can be also sandwich construction for single layer structure.When data wire 60 and source electrode 61 are single layer structure, it can be the alloy of the materials such as copper, aluminium, silver, molybdenum, chromium, neodymium, nickel, manganese, titanium, tantalum, tungsten or above various element compositions; When data wire 60 and source electrode 61 are sandwich construction, can be copper titanium sandwich construction, copper molybdenum sandwich construction, molybdenum aluminium molybdenum sandwich construction etc.Further, the thickness of data wire 60 and source electrode 61 is preferably
Be positioned at the passivation layer 71 on data wire 60 and source electrode 61, passivation layer 71 can be the single layer structure of silicon nitride, silica or silicon oxynitride, can be also the double-decker of silicon nitride or silica formation.In addition, can also select organic resin as passivation layer 71 material used, such as acrylic resin, polyimides and polyamide etc.The thickness of passivation layer 71 is preferably
Be positioned at the public electrode 81 on passivation layer 71, public electrode 81 is overall structures, covers all pixels on array base palte.Public electrode 81 is transparent conductive material, can be the materials such as tin indium oxide, indium zinc oxide.The thickness of public electrode 81 is preferably
further, public electrode 81 can be set according to actual conditions with the relative position of pixel electrode 33, and the utility model embodiment does not do concrete restriction to this.For example, public electrode 81 can be positioned at the top of pixel electrode 33 on array base palte, also can be positioned at the below of pixel electrode 33.When public electrode 81 is positioned at the top of pixel electrode 33, on public electrode 81, there is slit; When public electrode 81 is positioned at the below of pixel electrode 33, on pixel electrode 33, there is slit.
The utility model embodiment also provides the manufacture method of the senior super dimension of an a kind of top gate type thin film transistor switch technology type array base palte.
As shown in figure 15, this manufacture method comprises:
Step S1501, on underlay substrate, form the figure of active layer and drain electrode and pixel electrode.
First, can by methods such as sputters, on underlay substrate 10, directly form layer of metal oxide semiconductor, also can before forming metal-oxide semiconductor (MOS), first form one deck resilient coating.
Secondly, on metal-oxide semiconductor (MOS), apply one deck photoresist, then use have comprise active layer 31, drain 32 and the mask plate of the figure of pixel electrode 33 hide, expose, development and etching, last stripping photoresist, forms comprising active layer 31, draining 32 and the figure of pixel electrode 33 of arranging with layer.
Step S1502, forming on the figure of active layer and drain electrode and pixel electrode, form the first insulating barrier.
Can by the methods such as plasma enhanced chemical vapor deposition active layer 31, drain 32 and pixel electrode 33 on form the first insulating barrier 22.
Step S1503, on the first insulating barrier, form the figure comprise grid line and grid.
First, can on the first insulating barrier 22, form by methods such as sputter, thermal evaporations one deck grid metal film.
Secondly, apply one deck photoresist on grid metal film, use to have to comprise that the mask plate of grid line 20 and grid 21 figures hides, then expose, development, etching, last stripping photoresist, forms the figure that comprises grid line 20 and grid 21.
Step S1504, on the figure of grid line and grid, form the second insulating barrier, the first insulating barrier and the second insulating barrier are provided with the via hole of corresponding active layer.
By methods such as plasma enhanced chemical vapor depositions, on grid line 20 and grid 21, form the second insulating barrier 41.
On the second insulating barrier 41, apply one deck photoresist, use the mask plate with via pattern to hide, then expose, development, etching, last stripping photoresist, forms the figure that comprises via hole 51.
Step S1505, on the second insulating barrier, form the figure comprise data wire and source electrode, source electrode connects active layer by via hole.
First, can, by methods such as sputter or thermal evaporations, on the second insulating barrier 41, form one deck data wire metal film.
Secondly, on data wire metal film, apply one deck photoresist, then use the mask plate with the figure that comprises data wire 60 and source electrode 61 to hide, expose, development and etching, last stripping photoresist, form data wire 60 and source electrode 61, wherein source electrode 61 is connected with active layer 31 by via hole 51.
Step S1506, on the figure of data wire and source electrode, form passivation layer.
When passivation layer 71 materials are the materials such as silicon nitride, silica, can on the figure of data wire 60 and source electrode 61, form by methods such as plasma enhanced chemical vapor depositions one deck passivation layer 71; When passivation layer 71 materials are organic resin, directly organic resin is coated on data wire 60 and source electrode 61, form passivation layer 71.
Step S1507, on passivation layer, form the figure of public electrode.
First, can, by methods such as sputter or thermal evaporations, on passivation layer 71, form one deck common electrode layer.
Secondly, apply one deck photoresist in common electrode layer, then use the mask plate of the figure with public electrode 81 to hide, expose, development and etching, last stripping photoresist, forms public electrode 81.
Step S1508, on public electrode, form slit.
On public electrode 81, apply one deck photoresist, use the mask plate with slot pattern to hide, expose, development and etching, last stripping photoresist forms slit on public electrode 81.
The manufacture method of the senior super dimension of an above-described top gate type thin film transistor switch technology type array base palte is the manufacture method that public electrode 81 is positioned at pixel electrode 33 tops, because the relative position of public electrode 81 and pixel electrode 33 can be determined according to actual conditions, so the manufacture method of the senior super dimension of a top gate type thin film transistor switch technology type array base palte also can be determined according to actual conditions.
The above; it is only embodiment of the present utility model; but protection range of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.
Claims (9)
1. an array base palte, comprises underlay substrate, grid line, data wire, array arrangement thin-film transistor, pixel electrode and the passivation layer on described underlay substrate, and described thin-film transistor comprises grid, active layer, source electrode and drain electrode, it is characterized in that,
Described pixel electrode and described active layer, described drain electrode arrange with layer and are one-body molded.
2. array base palte according to claim 1, is characterized in that,
Described thin-film transistor is bottom gate thin film transistor, described array base palte comprises described grid line and the described grid being positioned on described underlay substrate, be positioned at the first insulating barrier on described grid line and described grid, be positioned at the described active layer on described the first insulating barrier, described drain electrode and described pixel electrode, be positioned at described data wire and described source electrode on described active layer, described drain electrode and described pixel electrode, and be positioned at the described passivation layer on described data wire and described source electrode, wherein, the source electrode of described thin-film transistor connects described active layer.
3. array base palte according to claim 1, is characterized in that,
Described thin-film transistor is top gate type thin film transistor, described array base palte comprises the described active layer being positioned on described underlay substrate, described drain electrode and described pixel electrode, be positioned at described active layer, the first insulating barrier on described drain electrode and described pixel electrode, be positioned at described grid line and grid on described the first insulating barrier, be positioned at the second insulating barrier on described grid line and described grid, be positioned at described data wire and described source electrode on described the second insulating barrier, and be positioned at the described passivation layer on described data wire and described source electrode, wherein, described the first insulating barrier and described the second insulating barrier are provided with the via hole of corresponding described active layer, the source electrode of described thin-film transistor connects described active layer by described via hole.
4. array base palte according to claim 2, is characterized in that,
Described passivation layer also comprises the opening of corresponding described pixel electrode.
5. array base palte according to claim 3, is characterized in that,
Described the first insulating barrier, described the second insulating barrier and described passivation layer also comprise the opening of corresponding described pixel electrode.
6. according to the array base palte described in claim 2 or 3, it is characterized in that, also comprise:
Be positioned at the public electrode on described passivation layer.
7. array base palte according to claim 6, is characterized in that,
On described public electrode, there is slit.
8. according to the array base palte described in claim 1-3 any one, it is characterized in that,
The material of described active layer, described drain electrode and described pixel electrode is metal oxide semiconductor material; The thickness of described active layer, described drain electrode and described pixel electrode is
9. a display unit, is characterized in that, comprises the array base palte as described in claim 1-8 any one.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456742A (en) * | 2013-08-27 | 2013-12-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105786287A (en) * | 2016-05-18 | 2016-07-20 | 上海天马微电子有限公司 | Touch display device and driving method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456742A (en) * | 2013-08-27 | 2013-12-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| US9502447B2 (en) | 2013-08-27 | 2016-11-22 | Boe Technology Co., Ltd. | Array substrate and manufacturing method thereof, display device |
| CN103456742B (en) * | 2013-08-27 | 2017-02-15 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
| CN105786287A (en) * | 2016-05-18 | 2016-07-20 | 上海天马微电子有限公司 | Touch display device and driving method thereof |
| CN105786287B (en) * | 2016-05-18 | 2019-01-22 | 上海天马微电子有限公司 | Touch display device and driving method thereof |
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