CN203422916U - Control signal generation circuit and circuit system - Google Patents
Control signal generation circuit and circuit system Download PDFInfo
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- CN203422916U CN203422916U CN201320577487.0U CN201320577487U CN203422916U CN 203422916 U CN203422916 U CN 203422916U CN 201320577487 U CN201320577487 U CN 201320577487U CN 203422916 U CN203422916 U CN 203422916U
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Abstract
The utility model provides a control signal generation circuit. The control signal generation circuit comprises signal output modules, each of which comprises an output terminal, a first control signal input terminal, and a second control signal input terminal, and each of which is capable of selectively outputting a first control signal inputted by the first control signal input terminal or a second control signal inputted by the second control signal input terminal to a control signal reception circuit through the output terminal. The utility model also provides a circuit system comprising the control signal generation circuit. When supplying a high level signal or a low level signal to the control signal reception circuit, the control signal generation circuit provided by the utility model only needs to switch between a first control signal mode and a second control signal mode without requiring complex transformation. In addition, the control signal generation circuit provided by the utility model also can test various control signal reception circuits needing rapid motions.
Description
Technical field
The utility model relates to control and the field tests of circuit, particularly, relates to a kind of control signal circuit for generating and a kind of Circuits System that comprises this control signal circuit for generating.
Background technology
In the array base palte of display device, having used in a large number gate driver circuit (GOA, Gate-driver On Array, is integrated in the gate driver circuit on array base palte), during test panel, is important step to the test of gate driver circuit.The control signal of gate driver circuit is comprised to high level signal VGH(grid cut-in voltage) and low level signal VGL(gate off voltage).In the prior art, the control signal circuit for generating of gate driver circuit utilizes operational amplifier to realize the conversion between high level signal VGH and low level signal VGL more, but when gate driver circuit needs to change control signal fast, utilize operational amplifier to provide the method for control signal not satisfy the demands.
Therefore, provide a kind of control signal circuit for generating that can realize the gate driver circuit of changing fast between high level signal and low level signal to become essential.
Utility model content
The purpose of this utility model is to provide a kind of can realize control signal circuit for generating and a kind of Circuits System that comprises this control signal circuit for generating of changing fast between high level signal and low level signal.
To achieve these goals, as an aspect of the present utility model, a kind of control signal circuit for generating is provided, wherein, described control signal circuit for generating comprises signal output module, described signal output module comprises output terminal, the first control signal input end and the second control signal input end, and described signal output module can optionally export the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to control signal receiving circuit from output terminal.
Preferably, described signal output module also comprises clock signal input end, and described signal output module optionally exports the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to control signal receiving circuit from output terminal according to the clock signal of described clock signal input end input.
Preferably, described signal output module comprises at least one analog switch, described in each, analog switch comprises described output terminal, described the first control signal input end, described the second control signal input end and described clock signal input end, and described output terminal is optionally connected with described the first control signal input end or described the second control signal input end according to described clock signal.
Preferably, described control signal circuit for generating also comprises the programmable logic device (PLD) for generation of described clock signal, and the clock signal output terminal of described programmable logic device (PLD) is connected with described clock signal input end.
Preferably, described signal output module comprise a plurality of described clock signal input ends and with a plurality of described clock signal input ends a plurality of described output terminals one to one, described programmable logic device (PLD) comprises a plurality of clock signal output terminals, a plurality of clock signal output terminals are connected with a plurality of described clock signal input ends respectively, and a plurality of described clock signal output terminals can be exported multiple clock signal.
Preferably, described signal output module comprises three described clock signal input ends, a plurality of described clock signal output terminal of described programmable logic device (PLD) comprises the first clock signal output terminal that can export the first clock signal, can export the second clock signal output terminal and the 3rd clock signal output terminal that can export the 3rd clock signal of the second clock signal, described the first clock signal is used for controlling described signal output module output initialize signal, described the second clock signal is used for controlling described signal output module and exports the first clock signal, described the 3rd clock signal is used for controlling described signal output module output second clock signal.
Preferably, described programmable logic device (PLD) comprises programmable gate array device, and the output pin of described programmable gate array device forms described clock signal output terminal.
Preferably, described control signal circuit for generating also comprises DC voltage modular converter, this DC voltage modular converter comprises the first control signal output module that produces described the first control signal and the second control signal output module that produces described the second control signal, described the first control signal output module is connected with described the first control signal input end, and described the second control signal output module is connected with described the second control signal input end.
Preferably, described control signal circuit for generating comprises a plurality of described DC voltage modular converters, described signal output module comprises many groups the first control signal input end and the second control signal input end, and a plurality of described DC voltage modular converters are corresponding one by one with many groups the first control signal input end and the second control signal input end.
Preferably, the first control signal of described the first control signal output module output can regulate in the first preset range; And/or the second control signal of described the second control signal output module output can regulate in the second preset range.
Preferably, described the first preset range is 5V to 20V, and described the second preset range is-and 20V is to-5V.
As another aspect of the present utility model, a kind of Circuits System is provided, comprise control signal circuit for generating and control signal receiving circuit, wherein, described control signal circuit for generating is above-mentioned control signal circuit for generating provided by the utility model, and the output terminal of the described signal output module of described control signal circuit for generating is electrically connected to described control signal receiving circuit.
Preferably, the gate driver circuit that described control signal receiving circuit is display device, this gate driver circuit comprises initialize signal input end, the first clock signal input terminal and second clock signal input part, the signal output module of described control signal generating means can provide initialize signal for described initialize signal input end, for described the first clock signal input terminal provides the first clock signal, and provide second clock signal for described second clock signal input part.
When utilizing control signal generating means provided by the utility model to provide the first required control signal of control and the second control signal for described control signal receiving circuit, only need between the first control signal pattern and the second control signal pattern, switch, for example, without the conversion (, producing the first control signal or the second control signal without operational amplifier) through complicated.Hence one can see that, control signal generating means provided by the utility model can and be exported between two kinds of patterns of the second control signal pattern rapidly in output the first control signal pattern and switch, the service requirement of the control signal receiving circuit that switches fast between the first control signal and the second control signal of can satisfying the demand.
Accompanying drawing explanation
Accompanying drawing is to be used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Fig. 1 is the schematic diagram of showing control signal circuit for generating provided by the utility model;
Fig. 2 is the circuit diagram of the first control signal output module in DC voltage modular converter;
Fig. 3 is the circuit diagram of the second control signal output module in DC voltage modular converter;
Fig. 4 is the circuit diagram of analog switch;
Fig. 5 is the sequential chart of the clock signal of programmable logic device (PLD) generation.
Description of reference numerals
100: control signal circuit for generating 110: DC voltage modular converter
112: the second control signal output modules of 111: the first control signal output modules
120: signal output module 121: analog switch
130: programmable logic device (PLD) 200: display device
210: display panel 220: source electrode drive circuit
230: gate driver circuit 121a: output terminal
121b: the first control signal input end 121c: the second control signal input end
121d: clock signal input end 111a: the first DC voltage input end
111b: the first control signal output terminal 111c: the first DC voltage conversion chip
112a: the second DC voltage input end 112b: the second control signal output terminal
112c: the second DC voltage conversion chip
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the utility model, is not limited to the utility model.
As shown in Figure 1, as an aspect of the present utility model, a kind of control signal circuit for generating 100 is provided, wherein, this control signal circuit for generating 100 comprises signal output module 120, this signal output module 120 comprises output terminal, the first control signal input end and the second control signal input end, and signal output module can optionally export the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to control signal receiving circuit from output terminal.
Control signal receiving circuit need to switch when normal operation between the first control signal and the second control signal.Control signal generating means provided by the utility model has the first control signal pattern and two kinds of patterns of the second control signal pattern.In the first control signal pattern, signal output module 120 exports the first control signal by the first control signal input end input to described control signal receiving circuit; In the second control signal pattern, signal output module 120 exports the second control signal by the second control signal input end input to described control signal receiving circuit.
The first control signal and the second control signal can be mutually different level signal.For example, the first control signal can be low level signal VGL, and the second control signal can be high level signal VGH.
When utilizing control signal generating means provided by the utility model to provide the first required control signal of control and the second control signal for described control signal receiving circuit, only need between the first control signal pattern and the second control signal pattern, switch, for example, without the conversion (, producing the first control signal or the second control signal without operational amplifier) through complicated.Hence one can see that, control signal generating means provided by the utility model can and be exported between two kinds of patterns of the second control signal pattern rapidly in output the first control signal pattern and switch, the service requirement of the control signal receiving circuit that switches fast between the first control signal and the second control signal of can satisfying the demand.
In addition, control signal circuit for generating 100 provided by the utility model can also be for testing the described control signal receiving circuit that need to switch fast between the first control signal and the second control signal.; analog control signal receiving circuit is (for example more truly for control signal circuit for generating 100 provided by the utility model; gate driver circuit in display device) working environment; control signal receiving circuit is tested, be take, judge that whether this control signal receiving circuit is as non-defective unit.
In the utility model, can be controlled in several ways between described the first control signal pattern and described the second control signal pattern and switch.For example, can control signal circuit for generating 100 be switched between the first control signal pattern and the second control signal pattern by mechanical means.Particularly, can in control signal circuit for generating 100, timing unit be set, this timing unit can periodically move, and control signal circuit for generating 100 is periodically switched between the first control signal pattern and the second control signal pattern.
In order to improve the switch speed of control signal circuit for generating 100 between the first control signal pattern and the second control signal pattern, preferably, can utilize electronically that control signal circuit for generating is switched between the first control signal pattern and the second control signal pattern.Particularly, signal output module 120 can also comprise clock signal input end, and signal output module 120 optionally exports the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to described control signal receiving circuit from output terminal according to the clock signal from described clock signal input end input.Should be understood that, the sequential of required control signal while normally moving from the clock signal of the clock signal input end input of signal output module 120 and described control signal receiving circuit (, the first control signal and the second control signal) is synchronous.
In order to respond rapidly described timing control signal, preferably, signal output module 120 can also comprise at least one analog switch 121, as shown in Figure 4, each analog switch 121 comprises output terminal 121a, the first control signal input end 121b, the second control signal input end 121c and clock signal input end 121d.Output terminal 121a is optionally connected with the first control signal input end 121b or the second control signal input end 121c according to described clock signal, thereby exports the first control signal or the second control signal to described control signal receiving circuit.
Particularly, when clock signal is high level, the output terminal 121a of analog switch 121 is connected with the first control signal input end 121b, thereby exports the first control signal by the first control signal input end 121b input to described control signal receiving circuit; When clock signal is low level, the output terminal 121a of analog switch 121 is connected with the second control signal input end 121c, thereby exports the second control signal by the second control signal input end 121c input to described control signal receiving circuit.
Or when clock signal is low level, the output terminal 121a of analog switch 121 is connected with the first control signal input end 121b, thereby export the first control signal by the first control signal input end 121b input to described control signal receiving circuit; When clock signal is high level, the output terminal 121a of analog switch 121 is connected with the second control signal input end 121c, thereby exports the second control signal by the second control signal input end 121c input to described control signal receiving circuit.
When signal output module 120 has an output terminal, this signal output module 120 can have an analog switch.In the embodiment shown in Fig. 4, signal output module 120 has four analog switches.Hereinafter, by introducing in detail the signal output module 120 with a plurality of analog switches, first do not repeat here.
In the utility model, can utilize external clock signal generating means to provide clock signal for control signal circuit for generating 100, in order to improve the integrated degree of control signal circuit for generating 100, reduce to utilize the overall dimension of the Circuits System of control signal circuit for generating 100, preferably, can be in the interior integrated programmable logic device (PLD) 130 for generation of described clock signal of control signal circuit for generating 100, the clock signal output terminal of this programmable logic device (PLD) 130 is connected with described clock signal input end.
When described control signal receiving circuit normally moves, need many group control signals when (every group of control signal all comprises described the first control signal and described the second control signal), control signal circuit for generating 100 can comprise a plurality of signal output module 120.In order to improve the integrated degree of control signal circuit for generating 100, preferably, signal output module 120 can comprise a plurality of described output terminals.
While normally moving due to described control signal receiving circuit, every group of required control signal all comprises the first control signal and the second control signal, therefore, signal output module 120 can also comprise a plurality of described clock signal input ends, and the plurality of described clock signal input end is corresponding one by one with a plurality of described clock signal input ends.Correspondingly, programmable logic device (PLD) 130 comprises a plurality of described clock signal output terminals, and a plurality of described clock signal output terminals are connected with a plurality of described clock signal input ends respectively, and a plurality of described clock signal output terminals can be exported multiple clock signal.
Those skilled in the art should be understood that, in each group control signal, the sequential of the first control signal and the second control signal can be the same or different, therefore, the multiple clock signal of a plurality of described clock signal output terminals outputs can be identical also can be different, as long as guarantee the timing synchronization of respectively organizing control signal required with described control signal receiving circuit operation.
Dissimilar control signal receiving circuit needs different control signals.For example, when gate driver circuit that described control signal receiving circuit is display panel, this control signal receiving circuit moves required control signal has initialize signal STV(to comprise low level signal and high level signal), the first clock signal clk 1(comprises low level signal and high level signal) and second clock signal CLK2(comprise low level signal and high level signal).
Correspondingly, signal output module 120 comprises three described clock signal input ends, a plurality of described clock signal output terminal of programmable logic device (PLD) 130 comprises the first clock signal output terminal that can export the first clock signal, can export the second clock signal output terminal and the 3rd clock signal output terminal that can export the 3rd clock signal of the second clock signal, described the first clock signal is for control signal output module 120 output initialize signal STV, described the second clock signal is for control signal output module 120 output the first clock signal clks 1, described the 3rd clock signal is for control signal output module 120 output second clock signal CLK2.
In signal output module 120, comprise in the embodiment of three described clock signal input ends, signal output module 120 can comprise three analog switches 121.
In control signal circuit for generating provided by the utility model, the concrete form of programmable logic device (PLD) 130 is not had to special restriction yet, for example, programmable logic device (PLD) 130 can be single-chip microcomputer.Preferably, programmable logic device (PLD) 130 can comprise programmable gate array device (FPGA, Field-Programmable Gate Array), and the output pin of this programmable gate array device forms described clock signal output terminal.Because programmable gate array device comprises a plurality of output pins, therefore, in this case, programmable logic device (PLD) 130 can easily realize the output of a plurality of clock signals.
For the ease of the first control signal and the second control signal are provided, preferably, as shown in Figure 1, control signal circuit for generating 100 can also comprise DC voltage modular converter 110, this DC voltage modular converter 110 can comprise produce described the first control signal the first control signal output module 111(as shown in Figure 2) and the second control signal output module 112(of producing described the second control signal as shown in Figure 3), the first control signal output module 111 is connected with described the first control signal input end, the second control signal output module 112 is connected with described the second control signal input end.
As shown in Figure 2, the first control signal output module 111 can comprise the first DC voltage input end 111a, the first DC voltage conversion chip 111c and the first control signal output terminal 111b.The first DC voltage input end 111a is connected with direct supply, after the first DC voltage conversion chip 111c and the various electronic components conversion that is connected with this first DC voltage conversion chip 111c, convert the DC voltage by the first DC voltage input end 111a input to first control signal.
As shown in Figure 2, the first control signal output module 111 can comprise the first DC voltage input end 111a, the first DC voltage conversion chip 111c and the first control signal output terminal 111b.The first DC voltage input end 111a is connected with direct supply, after the first DC voltage conversion chip 111c and the various electronic components conversion that is connected with this first DC voltage conversion chip 111c, convert the DC voltage by the first DC voltage input end 111a input to first control signal.
As shown in Figure 3, the second control signal output module 112 can comprise the second DC voltage input end 112a, the second DC voltage conversion chip 112c and the second control signal output terminal 112b.The second DC voltage input end 112a is connected with direct supply, after the second DC voltage conversion chip 112c and the various electronic components conversion that is connected with this second DC voltage conversion chip 112c, convert the DC voltage by the second DC voltage input end 112a input to second control signal.
In the utility model, DC conversion modules 110 can comprise the second control signal output module 112 that DC voltage is converted to the first control signal output module 111 of the first control signal (can be low level signal VGL) and DC voltage is converted to the second control signal (can be high level signal VGH), therefore, when utilizing the first control signal and the second control signal to test signal receiving circuit, only need between the first control signal output module 111 and the second control signal output module 112, switch, without complicated conversion (for example, without operational amplifier, produce the first control signal or the second control signal), can be to the QA signal receiving circuit of needs (for example, the gate driver circuit of display device) provide work required clock signal, or it is tested.
In comprising the embodiment of analog switch 121, the first control signal output terminal 111b of the first control signal output module 111 can be connected with the first control signal input end 121b of analog switch 121, and the second control signal output terminal 112b of the second control signal output module 112 can be connected with the second control signal input end 121c of analog switch 121.
In addition, the first control signal output module 111 can stable output the first control signal, that is, and after setting, the first control signal of the first control signal output module 111 outputs is changeless, and this first control signal can be the required control signal of signal receiving circuit work.And the second control signal output module 112 can stable output the second control signal,, after setting, the second control signal of the second control signal output module 112 outputs is changeless, and this second control signal can be the required control signal of signal receiving circuit work.Hence one can see that, and the test environment that described control signal circuit for generating provides is almost identical with the working environment of described signal receiving circuit, can obtain and test more accurately effect.
In the embodiment shown in Fig. 2 and Fig. 3, the first control signal of the first control signal output module 111 outputs is low level VGL, and the second control signal of the second control signal output module 112 outputs is high level VGH.
As noted before, described control signal receiving circuit may need many group control signals (every group of control signal all comprises the first control signal and the second control signal) while normally moving.Mutually the same when each group first control signal in control signal, when the second control signal is also mutually the same, a plurality of output terminals of signal output module 120 all can be connected with same DC voltage modular converter 110.For the ease of connecting, control signal circuit for generating 100 can comprise a plurality of DC voltage modular converters 110, and many groups of the first control signal input ends and the second control signal input end of signal output module 120 are corresponding one by one with a plurality of DC voltage modular converters 110.That is, each DC voltage modular converter 110 all with corresponding corresponding connection of one group of control signal (comprising the first control signal and the second control signal).
Control signal circuit for generating provided by the utility model can be for controlling or test multi-signal receiving circuit, and therefore, preferably, the first control signal of the first control signal output module 111 outputs can regulate in the first preset range; And/or the second control signal of the second control signal output module 112 outputs can regulate in the second preset range.As shown in Figures 2 and 3, in order to realize this purpose, in the first control signal output module 111 and the second control signal output module 112, be provided with respectively adjustable resistance.
When utilizing control signal circuit for generating provided by the utility model to test the gate driver circuit of display device, the first control signal is high level signal VGH, described the first preset range can be 5V to 20V, the second control signal is low level signal VGL, and described the second preset range can be for-20V be to-5V.
Control signal circuit for generating provided by the utility model can comprise a signal output module 120, also can comprise a plurality of signal output module 120.For example, when signal receiving circuit is the gate driver circuit of LCD display panel, because the side at LCD display panel is only provided with gate driver circuit, therefore, described control signal circuit for generating can comprise a signal output module 120, for the gate driver circuit of LCD display panel provides the required control signal of work or it is tested.When signal receiving circuit is the gate driver circuit of AMOLED display panel (as shown in Figure 1), need two signal output module 120, this is that both sides due to AMOLED are all provided with gate driver circuit, the effect of the gate driver circuit of one side is to provide sweep signal, the effect of the gate driver circuit of opposite side is that control OLED is luminous, needing two signal output module 120 to be respectively both sides gate driver circuit provides work required clock signal, or respectively the gate driver circuit of both sides is tested.
As another aspect of the present utility model, as shown in Figure 1, a kind of Circuits System is provided, this Circuits System comprises control signal circuit for generating 100 and control signal receiving circuit, wherein, described control signal circuit for generating 100 is above-mentioned control signal circuit for generating provided by the utility model, and described control signal receiving circuit is electrically connected to the output terminal of signal output module 120.
Particularly, described control signal receiving circuit can be the gate driver circuit 230 of display device 200, and this gate driver circuit 230 comprises initialize signal input end, the first clock signal input terminal and second clock signal input part.In this case, the signal output module 120 of control signal circuit for generating can provide initialize signal STV for described initialize signal input end, for described the first input end of clock provides the first clock signal clk 1, and provide second clock signal CLK2 for described second clock signal input part.
As shown in Figure 2, display device 200 also comprises display panel 210 and display panel source electrode drive circuit 220.
In the utility model, DC conversion modules 110 can comprise the second control signal output module 112 that DC voltage is converted to the first control signal output module 111 of the first control signal (can be low level signal VGL) and DC voltage is converted to the second control signal (can be high level signal VGH), therefore, when utilizing the first control signal and the second control signal to test signal receiving circuit, only need between the first control signal output module 111 and the second control signal output module 112, switch, without complicated conversion (for example, without operational amplifier, produce the first control signal or the second control signal), can be to the QA signal receiving circuit of needs (for example, the gate driver circuit of display device) provide work required clock signal, or it is tested.
In addition, the first control signal output module 111 can stable output the first control signal, that is, and after setting, the first control signal of the first control signal output module 111 outputs is changeless, and this first control signal can be the required control signal of signal receiving circuit work.And the second control signal output module 112 can stable output the second control signal,, after setting, the second control signal of the second control signal output module 112 outputs is changeless, and this second control signal can be the required control signal of signal receiving circuit work.Hence one can see that, and the test environment that described control signal circuit for generating provides is almost identical with the working environment of described signal receiving circuit, can obtain and test more accurately effect.
Those skilled in the art should be understood that, although the gate driver circuit of usining in the utility model has been described control signal circuit for generating provided by the utility model and Circuits System as described signal receiving circuit, but control signal circuit for generating provided by the utility model can also be used to other control signal receiving circuits outside gate driver circuit the required clock signal of work is provided or tests.
Below describe by reference to the accompanying drawings preferred implementation of the present utility model in detail; but; the utility model is not limited to the detail in above-mentioned embodiment; within the scope of technical conceive of the present utility model; can carry out multiple simple variant to the technical solution of the utility model, these simple variant all belong to protection domain of the present utility model.
It should be noted that in addition each the concrete technical characterictic described in above-mentioned embodiment, in reconcilable situation, can combine by any suitable mode.For fear of unnecessary repetition, the utility model is to the explanation no longer separately of various possible array modes.
In addition, between various embodiment of the present utility model, also can carry out combination in any, as long as it is without prejudice to thought of the present utility model, it should be considered as content disclosed in the utility model equally.
Claims (13)
1. a control signal circuit for generating, it is characterized in that, described control signal circuit for generating comprises signal output module, described signal output module comprises output terminal, the first control signal input end and the second control signal input end, and described signal output module can optionally export the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to control signal receiving circuit from output terminal.
2. control signal circuit for generating according to claim 1, it is characterized in that, described signal output module also comprises clock signal input end, and described signal output module optionally exports the second control signal of the first control signal of described the first control signal input end input or described the second control signal input end input to control signal receiving circuit from output terminal according to the clock signal of described clock signal input end input.
3. control signal circuit for generating according to claim 2, it is characterized in that, described signal output module comprises at least one analog switch, described in each, analog switch comprises described output terminal, described the first control signal input end, described the second control signal input end and described clock signal input end, and described output terminal is optionally connected with described the first control signal input end or described the second control signal input end according to described clock signal.
4. according to the control signal circuit for generating described in claim 2 or 3, it is characterized in that, described control signal circuit for generating also comprises the programmable logic device (PLD) for generation of described clock signal, and the clock signal output terminal of described programmable logic device (PLD) is connected with described clock signal input end.
5. control signal circuit for generating according to claim 4, it is characterized in that, described signal output module comprise a plurality of described clock signal input ends and with a plurality of described clock signal input ends a plurality of described output terminals one to one, described programmable logic device (PLD) comprises a plurality of clock signal output terminals, a plurality of clock signal output terminals are connected with a plurality of described clock signal input ends respectively, and a plurality of described clock signal output terminals can be exported multiple clock signal.
6. control signal circuit for generating according to claim 5, it is characterized in that, described signal output module comprises three described clock signal input ends, a plurality of described clock signal output terminal of described programmable logic device (PLD) comprises the first clock signal output terminal that can export the first clock signal, can export the second clock signal output terminal and the 3rd clock signal output terminal that can export the 3rd clock signal of the second clock signal, described the first clock signal is used for controlling described signal output module output initialize signal, described the second clock signal is used for controlling described signal output module and exports the first clock signal, described the 3rd clock signal is used for controlling described signal output module output second clock signal.
7. control signal circuit for generating according to claim 4, is characterized in that, described programmable logic device (PLD) comprises programmable gate array device, and the output pin of described programmable gate array device forms described clock signal output terminal.
8. according to the control signal circuit for generating described in any one in claims 1 to 3, it is characterized in that, described control signal circuit for generating also comprises DC voltage modular converter, this DC voltage modular converter comprises the first control signal output module that produces described the first control signal and the second control signal output module that produces described the second control signal, described the first control signal output module is connected with described the first control signal input end, and described the second control signal output module is connected with described the second control signal input end.
9. control signal circuit for generating according to claim 8, it is characterized in that, described control signal circuit for generating comprises a plurality of described DC voltage modular converters, described signal output module comprises many groups the first control signal input end and the second control signal input end, and a plurality of described DC voltage modular converters are corresponding one by one with many groups the first control signal input end and the second control signal input end.
10. control signal circuit for generating according to claim 8, is characterized in that, the first control signal of described the first control signal output module output can regulate in the first preset range; And/or the second control signal of described the second control signal output module output can regulate in the second preset range.
11. control signal circuit for generatings according to claim 10, is characterized in that, described the first preset range is 5V to 20V, and described the second preset range is-and 20V is to-5V.
12. 1 kinds of Circuits System, comprise control signal circuit for generating and control signal receiving circuit, it is characterized in that, described control signal circuit for generating is the control signal circuit for generating described in any one in claim 1 to 11, and the output terminal of the described signal output module of described control signal circuit for generating is electrically connected to described control signal receiving circuit.
13. Circuits System according to claim 12, it is characterized in that, the gate driver circuit that described control signal receiving circuit is display device, this gate driver circuit comprises initialize signal input end, the first clock signal input terminal and second clock signal input part, the signal output module of described control signal generating means can provide initialize signal for described initialize signal input end, for described the first clock signal input terminal provides the first clock signal, and provide second clock signal for described second clock signal input part.
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| CN201320577487.0U CN203422916U (en) | 2013-09-17 | 2013-09-17 | Control signal generation circuit and circuit system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103472753A (en) * | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | Control signal generation circuit and circuit system |
| CN105929210A (en) * | 2016-05-06 | 2016-09-07 | 中南大学 | Detection signal generation circuit and self-check system |
| CN110598310A (en) * | 2019-09-09 | 2019-12-20 | 珠海格力电器股份有限公司 | Signal conditioning method, circuit system, conditioning apparatus and storage medium |
| CN112859658A (en) * | 2019-11-27 | 2021-05-28 | 株洲中车时代电气股份有限公司 | Dry node output control device |
-
2013
- 2013-09-17 CN CN201320577487.0U patent/CN203422916U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103472753A (en) * | 2013-09-17 | 2013-12-25 | 京东方科技集团股份有限公司 | Control signal generation circuit and circuit system |
| WO2015039463A1 (en) * | 2013-09-17 | 2015-03-26 | 京东方科技集团股份有限公司 | Control signal generating circuit and circuit system |
| US9728113B2 (en) | 2013-09-17 | 2017-08-08 | Boe Technology Group Co., Ltd. | Control signal generating circuit and circuit system |
| CN105929210A (en) * | 2016-05-06 | 2016-09-07 | 中南大学 | Detection signal generation circuit and self-check system |
| CN105929210B (en) * | 2016-05-06 | 2018-09-04 | 中南大学 | A kind of detection signal generating circuit and self-checking system |
| CN110598310A (en) * | 2019-09-09 | 2019-12-20 | 珠海格力电器股份有限公司 | Signal conditioning method, circuit system, conditioning apparatus and storage medium |
| CN112859658A (en) * | 2019-11-27 | 2021-05-28 | 株洲中车时代电气股份有限公司 | Dry node output control device |
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