CN203422915U - Shift register unit, shift register and display device - Google Patents
Shift register unit, shift register and display device Download PDFInfo
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- CN203422915U CN203422915U CN201320487520.0U CN201320487520U CN203422915U CN 203422915 U CN203422915 U CN 203422915U CN 201320487520 U CN201320487520 U CN 201320487520U CN 203422915 U CN203422915 U CN 203422915U
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Abstract
The utility model provides a shift register unit. The shift register comprises a first driving signal input terminal, a first driving signal output terminal, a first clock signal input terminal, a first pull-up transistor, a first output pull-down transistor, a switch transistor, a reset transistor and a bootstrap capacitor. The shift register unit further comprises a pull-down unit. A first terminal of the pull-down unit is connected with the gate of the switch transistor. A second terminal of the pull-down unit is connected with the gate of the reset transistor. A third terminal of the pull-down unit is connected with the gate of the first output pull-down transistor. The source of the reset transistor is connected with a second low-level input terminal. The source of the first output pull-down transistor is connected with a third low-level input terminal. The utility model further provides a shift register having the shift register unit, a gate driver having the shift register, and a display device having the gate driver. The shift register unit can adopt a depleted transistor.
Description
Technical field
The utility model relates to demonstration field, particularly, relates to a kind of shifting deposit unit, a kind of shift register and a kind of display device that comprises this shift register that comprises this shifting deposit unit.
Background technology
Along with the development of flat pannel display, high resolving power, narrow frame become the trend of development, and on display panel integrated gate drive circuitry be realize high resolving power, narrow frame shows most important solution.
Shown in Fig. 1 is the circuit diagram of existing basic shifting deposit unit, as shown in Figure 1, this basic shifting deposit unit comprise the T100 that pulls up transistor, output pull-down transistor T200, bootstrap capacitor C1, on draw control transistor T 300, drop-down control transistor T 400, the first clock signal input terminal CLK, drop-down unit 13, driving signal input OUT(n-1) and driving signal output part OUT(n).
In Fig. 1, above draw the node of node PU point for being connected with the grid of the T100 that pulls up transistor, pull-down node PD is the node being connected with the grid of output pull-down transistor T200.From driving signal input OUT(n-1) input start signal STV, VGL represents low level.Shown in Fig. 2 is the sequential chart of shifting deposit unit each signal when work in Fig. 1, and VGH represents high level.
A-si(amorphous silicon) and p-si(polysilicon) thin film transistor (TFT) made is reinforced membranes transistor, when using this basic shifting deposit unit circuit of enhancement mode TFT fabrication techniques, the shifting deposit unit shown in Fig. 1 can work (as shown in the solid line part of Fig. 2).
In recent years, oxide thin film transistor is as a kind of very potential semiconductor technology, simpler than p-si technique, cost is lower, higher than a-si mobility, thereby more and more come into one's own, be likely various display panels, especially OLED(Organic Light Emitting Diode future) and the flexible main flow backboard Driving technique showing.Yet oxide thin film transistor has the feature of depletion type, as shown in dotted portion in Fig. 2, when the oxide thin film transistor as depletion type thin film transistor (TFT) directly applies to the circuit shown in Fig. 1, can not work.
Reason is explained as follows: the transistorized difference of depletion type thin film transistor (TFT) and reinforced membranes is shown in Fig. 3 and Fig. 4, Fig. 3 is the transistorized performance diagram of reinforced membranes, the longitudinal axis is the electric current of thin film transistor (TFT) drain electrode, transverse axis is the voltage of grid source electrode, from the transistorized performance diagram of the reinforced membranes shown in Fig. 3, can find out, when Vgs(gate source voltage) voltage is while being zero, id (drain current) is zero, illustrate that when Vgs is zero, reinforced membranes transistor is closed completely.Fig. 4 is the performance diagram of depletion type thin film transistor (TFT), and the same longitudinal axis is drain current, and transverse axis is gate source voltage, but this figure shows, is Vgs while being zero, and id is much larger than zero, and only when gate source voltage is certain negative voltage, id is just zero.
Utility model content
The purpose of this utility model is to provide a kind of shifting deposit unit, a kind of shift register of this shifting deposit unit, a kind of gate drivers and a kind of display device that comprises this gate drivers that comprises this shift register of comprising, in described shifting deposit unit, can use depletion type thin film transistor (TFT).
To achieve these goals, as an aspect of the present utility model, a kind of shifting deposit unit is provided, this shifting deposit unit comprises the first driving signal input, first drives signal output part, the first clock signal input terminal, first pulls up transistor, the first output pull-down transistor, switching transistor, reset transistor and bootstrap capacitor, the drain electrode of described switching transistor is connected with described the first driving signal input, the drain electrode of described the first output pull-down transistor and described first drives signal output part to be connected, one end of described bootstrap capacitor is connected with described the first grid pulling up transistor, the other end and described first drives signal output part to be connected, described the first grid pulling up transistor is connected with the source electrode of described switching transistor, described the first drain electrode pulling up transistor is connected with described the first clock signal input terminal, described the first drain electrode pulling up transistor and described first drives signal output part to be connected, the drain electrode of described reset transistor is connected with the source electrode of described switching transistor, wherein, described shifting deposit unit also comprises drop-down unit, the first end of this drop-down unit is connected with the grid of described switching transistor, the second end of described drop-down unit is connected with the grid of described reset transistor, the 3rd end of described drop-down unit is connected with the grid of described the first output pull-down transistor, the source electrode of described reset transistor with can export second low level the second low level input end and be connected, the source electrode of described the first output pull-down transistor with can export the 3rd low level the 3rd low level input end and be connected, in evaluate phase, described drop-down unit can be to the grid of described the first output pull-down transistor, the grid of described switching transistor and the grid of described reset transistor are exported the first low level, described the first low level and described the second low level difference are less than the threshold voltage of described reset transistor, described the first low level and described the 3rd low level difference are less than the threshold voltage of described the first output pull-down transistor.
Preferably, described shifting deposit unit comprises the first drop-down module and the second drop-down module, described the first drop-down module is for exporting the second low level in pre-charging stage to described the second end and described the 3rd end, this second low level and described the 3rd low level difference are less than the threshold voltage of described the first output pull-down transistor, and described the second drop-down module is for exporting described the first low level in described evaluate phase to described the second end and described the 3rd end.
Preferably, described shifting deposit unit comprises the second driving signal output part, this second driving signal output part and described first drives signal output part to synchronize, and can export described high level and described the first low level, described the second drop-down module comprises the first drop-down control transistor and the second driving signal input, the transistorized grid of this first drop-down control and described second drives signal output part to be connected, the transistorized source electrode of described the first drop-down control is connected with described the first low level input end, the transistorized drain electrode of described the first drop-down control is connected with described the 3rd end with described the second end, described the second driving signal input is synchronizeed with described the first driving signal input, and described the second driving signal input can input high level and described the first low level, described the second driving signal input is connected with first end.
Preferably, described the second drop-down module also comprises the second drop-down control transistor, the transistorized grid of this second drop-down control and described second drives signal output part to be connected, the transistorized source electrode of described the second drop-down control is connected with described the first low level input end, and the transistorized drain electrode of described the second drop-down control is connected with described first end.
Preferably, described shifting deposit unit also comprises the second driving signal output module, this the second driving signal output module comprises that second pulls up transistor and the second output pull-down transistor, described the second grid pulling up transistor is connected with described the first grid pulling up transistor, described the second drain electrode pulling up transistor is connected with described the first clock signal input terminal, described the second source electrode pulling up transistor and described second drives signal output part to be connected, the grid of described the second output pull-down transistor is connected with the grid of described the first output pull-down transistor, the source electrode of described the second output pull-down transistor is connected with described the first low level input end, the drain electrode of described the second output pull-down transistor and described second drives signal output part to be connected.
Preferably, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 3rd drop-down control transistor and the 4th drop-down control transistor, the transistorized resistance of described the 4th drop-down control is less than the resistance of the 3rd pull-down transistor, the transistorized grid of described the 3rd drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 3rd drop-down control is connected with described the second end, the transistorized grid of described the 4th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 4th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 4th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
Preferably, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 3rd drop-down control transistor, the 4th drop-down control transistor, the 5th drop-down control transistor and the 6th drop-down control transistor, the transistorized resistance of described the 4th drop-down control is less than the resistance of the 3rd pull-down transistor, the transistorized resistance of described the 6th drop-down control is less than the transistorized resistance of described the 5th drop-down control, the transistorized grid of described the 3rd drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 3rd drop-down control is connected with the transistorized drain electrode of described the 4th drop-down control, the transistorized grid of described the 4th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 4th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 4th drop-down control is connected with the transistorized source electrode of described the 3rd drop-down control, the transistorized grid of described the 5th drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 5th drop-down control is connected with described the second end, the transistorized grid of described the 6th drop-down control is connected with described second clock signal input part, the transistorized source electrode of described the 6th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 6th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
Preferably, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 7th drop-down control transistor and drop-down electric capacity, the resistance of this drop-down electric capacity is greater than the transistorized resistance of described the 7th drop-down control, one end of described drop-down electric capacity is connected with described second clock signal input part, the other end of described drop-down electric capacity is connected with described the second end, the transistorized grid of described the 7th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 7th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 7th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
Preferably, described first pull up transistor, at least one in the first output pull-down transistor, switching transistor, reset transistor be depletion mode transistor.
Preferably, described first pull up transistor, the first output pull-down transistor, switching transistor, reset transistor be N channel thin-film transistor.
As another aspect of the present utility model, a kind of shift register is also provided, this shift register comprises multistage shifting deposit unit, wherein, described shifting deposit unit is above-mentioned shifting deposit unit provided by the utility model, and first of the first driving signal input of shifting deposit unit and shifting deposit unit described in upper level drives signal output part to be connected described in next stage.
As an also aspect of the present utility model, a kind of display device is provided, this display device comprises thin film transistor (TFT), data line, grid line and the shift register being electrically connected to this grid line, wherein, described shift register is above-mentioned shift register provided by the utility model, and first of described shift register drives signal output part to be connected with described grid line.
In shifting deposit unit provided by the utility model, in evaluate phase, the grid potential of the first output pull-down transistor is the first low level, and source potential is the 3rd low level, and therefore, the first output pull-down transistor is closed completely in evaluate phase; The source potential of reset transistor is the second low level, and grid potential is the first low level, and therefore, reset transistor is closed completely; The source potential of switching transistor identical with the current potential that above draws node (higher than high level), the grid potential of switching transistor is the first low level, therefore, switching transistor also cuts out completely.
Even if the first output pull-down transistor, switching transistor and reset transistor are depletion mode transistor, this the first output pull-down transistor, switching transistor and reset transistor also can be closed extremely completely at evaluation, can not produce electric leakage, thereby can make to draw node to be coupled to higher current potential.
Accompanying drawing explanation
Accompanying drawing is to be used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Fig. 1 is the circuit diagram of existing basic shifting deposit unit;
Fig. 2 is the sequential chart of each signal when work of the shifting deposit unit shown in Fig. 1;
Fig. 3 is the performance diagram of enhancement transistor;
Fig. 4 is the performance diagram of depletion mode transistor;
Fig. 5 is the schematic diagram of shifting deposit unit provided by the utility model;
Fig. 6 is the circuit diagram of shifting deposit unit the first embodiment provided by the utility model;
Fig. 7 is the circuit diagram of the second embodiment of shifting deposit unit provided by the utility model;
Fig. 8 is the circuit diagram of the third embodiment of shifting deposit unit provided by the utility model;
Fig. 9 is the circuit diagram of the 4th kind of embodiment of shifting deposit unit provided by the utility model;
The sequential chart of each signal when Figure 10 is shifting deposit unit work provided by the utility model;
Figure 11 is the schematic diagram of shift register provided by the utility model.
Description of reference numerals
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the utility model, is not limited to the utility model.
As shown in Figure 5, as an aspect of the present utility model, a kind of shifting deposit unit is provided, this shifting deposit unit comprises the first driving signal input 10, first drives signal output part 11, the first clock signal input terminal CLK, first T1 that pulls up transistor, the first output pull-down transistor T2, switching transistor T3, reset transistor T4 and bootstrap capacitor C1, the drain electrode of switching transistor T3 is connected with the first driving signal input 10, the drain electrode of the first output pull-down transistor T2 is connected 11 with the first driving signal output part, one end of bootstrap capacitor C1 is connected with the first grid that pulls up transistor T1, the other end is connected with the first driving signal output part 11, the first grid that pulls up transistor T1 is connected with the source electrode of switching transistor T3, the first drain electrode that pulls up transistor T1 is connected with the first clock signal input terminal CLK, the first drain electrode that pulls up transistor T1 is connected with the first driving signal output part 11, the drain electrode of reset transistor T4 is connected with the source electrode of switching transistor T3, wherein, described shifting deposit unit also comprises drop-down unit 13, the first end a of this drop-down unit 13 is connected with the grid of switching transistor T3, the second end b of drop-down unit 13 is connected with the grid of reset transistor T4, the 3rd end c of drop-down unit 13 is connected with the grid of the first output pull-down transistor T2, the source electrode of reset transistor T4 is connected with the second low level input end that can export the second low level VGL2, the source electrode of the first output pull-down transistor T2 is connected with the 3rd low level input end that can export the 3rd low level VGL3, in evaluate phase, drop-down unit 13 can be to the grid of the first output pull-down transistor T2, the grid of the grid of switching transistor T3 and reset transistor T4 is exported the first low level VGL1, the threshold voltage that the difference of this first low level VGL1 and the second low level VGL2 is less than reset transistor T4 (, VGL1-VGL2 < V
th, T4), the difference of the first low level VGL1 and the 3rd low level VGL3 is less than threshold voltage (that is, the VGL1-VGL3 < V of the first output pull-down transistor T2
th, T2).
Those skilled in the art should be understood that, the first grid that pulls up transistor T1 forms and draws node PU, the grid of the first output pull-down transistor T2 forms pull-down node PD, this pull-down node PD overlap with the 3rd end c of drop-down unit 13 (referring to Fig. 6 to Fig. 9).
Evaluate phase (that is, the stage in Figure 10 2.), the grid potential of the first output pull-down transistor T2 is the first low level VGL1, and source potential is the 3rd low level VGL3, and therefore, the first output pull-down transistor T2 closes completely in evaluate phase; The source potential of reset transistor T4 is the second low level VGL2, and grid potential is the first low level VGL1, and therefore, reset transistor T4 closes completely; The source potential of switching transistor T3 identical with the current potential that above draws node PU (higher than high level VGH), the grid potential of switching transistor T3 is the first low level VGL1, therefore, switching transistor T3 also closes completely.
Even if the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 are depletion mode transistor, this the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 also can close extremely completely at evaluation, can not produce electric leakage, thereby can make to draw node to be coupled to higher current potential, first T1 that pulls up transistor is opened, and make the first driving signal output part can export high level VGH.
Should be understood that, pre-charging stage (that is, the stage in Figure 10 is 1.), the first end a of drop-down unit 13 should open switching transistor T3 to the grid output high level of switching transistor T3, on draw node PU to charge.And in pre-charging stage, reset transistor T4 and the first output pull-down transistor T2 should at least roughly close, to guarantee normally carrying out of pre-charging stage.
It is to be further understood that at reseting stage, the second end b of drop-down unit 13 should open reset transistor T4 to the grid output high level VGH of reset transistor T4, thus on draw node PU to discharge.
The concrete structure of drop-down unit 13 is described below in conjunction with Fig. 6 to Fig. 9.
As shown in Fig. 6 to Fig. 9, described shifting deposit unit can comprise the first drop-down module 13a and the second drop-down module 13b, the first drop-down module 13a is in pre-charging stage (, stage in Figure 10 is 1.) pull down the second end b of unit and the 3rd end c of drop-down unit exports the second low level VGL2, the difference of this second low level VGL2 and the 3rd low level VGL3 is less than the threshold voltage V of the first output pull-down transistor T2
th, T2, (be VGL2-VGL3 < V
th, T2), the second drop-down module 13b exports the first low level VGL1 for pull down first end a, the second end b and the 3rd end c of unit in described evaluate phase.
In pre-charging stage, the first output pull-down transistor T2 closes completely, and reset transistor T4 roughly closes, therefore, can be normally on draw node PU to charge.
More specifically, in order to make the second drop-down module 13b can pull down in evaluate phase the first end a of unit, the second end b and the 3rd end c export the first low level VGL1, as shown in Fig. 6 to 9, described shifting deposit unit can also comprise the second driving signal output part 12, this second driving signal output part 12 and first drives signal output part 11 to synchronize, and can export high level VGH and the first low level VGL1, the second drop-down module 13b can comprise the first drop-down control transistor T 10 and the second driving signal input 14, the grid of this first drop-down control transistor T 10 is connected with the second driving signal output part 12, the source electrode of the first drop-down control transistor T 10 is connected with described the first low level input end, the drain electrode of the first drop-down control transistor T 10 is connected with the 3rd end c with the second end b of described drop-down unit, the second driving signal input 14 is connected with the first end a of described drop-down unit, the second driving signal input 14 is synchronizeed with the first driving signal input 10, and the second driving signal input 14 can be to first end a input high level VGH and the first low level VGL1.
The second driving signal input 14 with the meaning that the first driving signal input 10 is synchronizeed is, when by the first driving signal input 10 during to the drain electrode input high level VGH of switching transistor T3, grid input high level VGH by from the second driving signal input 14 to switching transistor T3, when during to the drain electrode input low level of switching transistor T3, inputting the first low level VGL1 by the second driving signal input 14 to the drain electrode of switching transistor T3 by the first driving signal input 10.
The second driving signal input 14 can guarantee that switching transistor T3 opens in pre-charging stage, and closes in evaluate phase.
So-called second drives signal output part 12 and first to drive signal output part 11 to synchronize refers to, when the first driving signal output part 11 output high level, second drives signal output part 12 also to export high level, when the first driving signal output part 11 output low level, second drives also output low level of signal output part 12.First drives 11 of signal output parts to export high level VGH in evaluate phase, therefore second drives signal output part 12 also only at evaluate phase output high level VGH.
In evaluate phase, the grid of the first drop-down control transistor T 10 is the high level VGH of the second driving signal output part 12 outputs, so the first drop-down control transistor T 10 conductings, the drain potential of the first drop-down control transistor T 10 is the first low level VGL1, the current potential of the second end b of described drop-down unit and the 3rd end c can be pulled low to the first low level VGL1.
In order to ensure switching transistor, T3 closes in evaluate phase, preferably, the second drop-down module 13b can also comprise the second drop-down control transistor T 9, the grid of this second drop-down control transistor T 9 is connected with the second driving signal output part 12, the source electrode of the second drop-down control transistor T 9 is connected with described the first low level input end, and the drain electrode of the second drop-down control transistor T 9 is connected with the first end a of described drop-down unit.
In evaluate phase, second drives signal output part 12 to the grid output high level of the second drop-down control transistor T 9, makes the second drop-down control transistor T 9 conductings, and further the current potential of the second end a of described drop-down unit is pulled down to the first low level VGL1.
Introduce below and how by second, to drive signal output part 12 outputs and the first two driving signal that drives signal to synchronize.
As shown in Fig. 6 to Fig. 7, shifting deposit unit also comprises the second driving signal output module 15, this second drives signal output module 15 to comprise the second pull up transistor T5 and the second output pull-down transistor T6, the pull up transistor grid (above drawing node PU) of T1 of the second grid and first that pulls up transistor T5 is connected, the second drain electrode that pulls up transistor T5 is connected with the first clock signal input terminal CLK, the second source electrode that pulls up transistor T5 is connected with the second driving signal output part 12, the grid of the second output pull-down transistor T6 is connected with the grid (pull-down node PD) of the first output pull-down transistor T2, the source electrode of the second output pull-down transistor T6 is connected with described the first low level input end, the drain electrode of the second output pull-down transistor T6 is connected with the second driving signal output part 12.
As mentioned above, the second grid that pulls up transistor T5 draws on also node PU to be connected, therefore the second output pull-down transistor T6 is connected with pull-down node PD, in evaluate phase, second drives signal output part 12 can export high level VGH, and in pre-charging stage, reseting stage and inoperative stage, second drives signal output part 12 can export the first low level VGL1.Therefore,, in pre-charging stage, reseting stage and inoperative stage, the first drop-down pilot angle transistor T 10 and the second drop-down control transistor T 9 are roughly closed (although have leakage current, very little).
The first drop-down module 13a has following effect: the first, at reseting stage, draw high the current potential at pull-down node PD place, thereby make reset transistor T4 conducting, on draw node PU to discharge; The second, in inoperative stage of shifting deposit unit, to pull-down node PD, exchange drop-down, be that pull-down node PD can be in alternating voltage state, avoid long direct current (DC) bias to cause the transmission curve of lower the first output pull-down transistor T2 to be offset ageing failure to the right, and then improve the serviceable life of whole shifting deposit unit.
Below in conjunction with Fig. 7 to Fig. 9, introduce several embodiments of the first drop-down module 13a.
In the first embodiment as shown in Figure 7, described shifting deposit unit also comprises second clock signal input part CLKB, this second clock signal input part CLKB is contrary with the first clock signal input terminal CLK, the first drop-down module 13a comprises the 3rd drop-down control transistor T 7 and the 4th drop-down control transistor T 8, the resistance of the 4th drop-down control transistor T 8 is less than the resistance of the 3rd drop-down control transistor T 7, the grid of the 3rd drop-down control transistor T 7 is connected with second clock signal input part CLKB with drain electrode, the source electrode of the 3rd drop-down control transistor T 7 is connected with the second end b, the grid of the 4th drop-down control transistor T 8 is connected with the second driving signal input 14, the source electrode of the 4th drop-down control transistor T 8 is connected with described the second low level input end, the drain electrode of the 4th drop-down control transistor T 8 is connected with the second end b, the second end b is connected with the 3rd end c.
Wherein, the meaning that the first clock signal input terminal CLK is contrary with second clock signal input part CLKB is, when from the first clock signal input terminal CLK input high level, from second clock signal input part CLKB input low level, when from the first clock signal input terminal CLK input low level, from second clock signal input part CLKB input high level.
Below in conjunction with Fig. 7 and Figure 10, specifically introduce the principle of work of the shifting deposit unit of the utility model the first embodiment.
Pre-charging stage (stage in Figure 10 1.), by the first driving signal input 10 input high level VGH, by the second driving signal input 14 input high level VGH, by the first clock signal input terminal CLK, input the first low level VGL1, by second clock signal input part CLKB input high level VGH.
Switching transistor T3 conducting, to on draw node PU point to charge, making on this, to draw the current potential at node PU place is high level VGH, now, first T1 and second T5 that pulls up transistor that pulls up transistor opens, the first driving signal input 11 and second drives signal output part 12 all to export the first low level VGL1 by the first clock signal input terminal CLK input, and therefore, the first drop-down control transistor T 10 and the second drop-down control transistor T 9 are roughly closed.In this stage, the 3rd drop-down control transistor T 7 and the equal conducting of the 4th drop-down control transistor T 8.Because the resistance of the 4th drop-down control transistor T 8 is less than the resistance of the 3rd drop-down control transistor T 7, therefore, the current potential at the second end b place of described drop-down unit approaches the second low level VGL2, because the second end b is connected with the 3rd end c, therefore, the 3rd end c(, pull-down node PD) current potential be the second low level VGL2.Therefore, the first output pull-down transistor T2 closes completely, and reset transistor T4 roughly closes, and charging process can normally be carried out.
Evaluate phase (stage in Figure 10 2.), by the first driving signal input 10 input low levels, by second driving signal input 14 input the first low level VGL1, by the first clock signal input terminal CLK input high level VGH, by second clock signal input part CLKB, input the first low level VGL1.
On draw the current potential at node PU place to be coupled to higher by bootstrap capacitor C1, first T1 and second T5 that pulls up transistor that pulls up transistor is opened, first drives signal output part 11 and second to drive signal output part 12 can export high level VGH, the first drop-down control transistor T 10 and the second drop-down control transistor T 9 are all the high level VGH conducting of the second driving signal output part 12 outputs because of grid potential, therefore, the 3rd end c(, pull-down node PD) and the grid of switching transistor T3 be all pulled down to the first low level VGL1, thereby the first output pull-down transistor T2 and switching transistor T3 are thoroughly closed.In evaluate phase, the 3rd drop-down control transistor T 7 and the 4th drop-down control transistor T 8 are closed, and the second end b of drop-down unit is connected with the 3rd end c, therefore, the current potential of the second end b is identical with the current potential of the 3rd end c, is the first low level VGL1, and reset transistor T4 is thoroughly closed.Hence one can see that, in evaluate phase, the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 all thoroughly close, and do not have leaky, make to draw node PU can there is higher current potential, guarantee from the sufficiently high high level VGH of the first driving signal output part 11 output.
At reseting stage, by the first driving signal input 10 input low levels, by the second driving signal input 14 input low levels, by the first clock signal input terminal CLK, input the first low level VGL1, by second clock signal input part CLKB input high level VGH.
Second drives signal output part 12 output low levels, the first drop-down control transistor T 10 and the second drop-down control transistor T 9 are closed, switching transistor T3 closes, from second clock signal input part CLKB input high level VGH, from second driving signal input 14 input the first low level VGL1, the 3rd drop-down control transistor T 7 is opened, the 4th drop-down control transistor T 8 is closed, therefore the second end b place current potential is high level VGH, because the second end b is connected with the 3rd end c, therefore, the current potential at the 3rd end c place is also high level VGH, therefore, the first output pull-down transistor T2, the second output pull-down transistor T6 and equal conducting of reset transistor T4, reset transistor T4 on draw node PU to discharge, first drives signal output part output the 3rd low level VGL3, second drives signal output part to export the first low level VGL1.
In the inoperative stage, the alternating state of the 3rd drop-down control transistor T 7 in opening and closing, be that pull-down node PD can be in alternating voltage state, avoid long direct current (DC) bias to cause the transmission curve of lower the first output pull-down transistor T2 to be offset ageing failure to the right, and then improve the serviceable life of whole shifting deposit unit.
In the second embodiment shown in Fig. 8, described the first drop-down module 13a comprises the 3rd drop-down control transistor T 7, the 4th drop-down control transistor T 8, the 5th drop-down control transistor T 11 and the 6th drop-down control transistor T 12, the resistance of the 4th drop-down control transistor T 8 is less than the resistance of the 3rd drop-down control transistor T 7, the resistance of the 6th drop-down control transistor T 12 is less than the resistance of the 5th drop-down control transistor T 11, the grid of the 3rd drop-down control transistor T 7 is connected with second clock signal input part CLKB with drain electrode, the source electrode of the 3rd drop-down control transistor T 7 is connected with the drain electrode of the 4th drop-down control transistor T 8, the grid of the 4th drop-down control transistor T 8 is connected with the second driving signal input 14, the source electrode of the 4th drop-down control transistor T 8 is connected with described the second low level input end, the drain electrode of the 4th drop-down control transistor T 8 is connected with the source electrode of the 3rd drop-down control transistor T 7, the grid of the 5th drop-down control transistor T 11 is connected with second clock signal input part CLKB with drain electrode, the source electrode of the 5th drop-down control transistor T 11 is connected with the second end b of described drop-down unit, the grid of the 6th drop-down control transistor T 12 is connected with described second clock signal input part, the source electrode of the 6th drop-down control transistor T 12 is connected with described the second low level input end, the drain electrode of the 6th drop-down control transistor T 12 is connected with the second end b of described drop-down unit, the second end b of described drop-down unit is connected with the 3rd end c of described drop-down unit.
Due in the present embodiment, the second drop-down module 13b and second drives the structure of signal output module 15 identical with the first embodiment, principle of work is also identical, therefore, only introduce the second drop-down module 13b herein at each working stage and the state in inoperative stage of shifting deposit unit.
In pre-charging stage, the 3rd drop-down control transistor T 7, the 4th drop-down control transistor T 8, the 6th drop-down control transistor T 12 is all opened, because the resistance of the 3rd drop-down control transistor T 7 is greater than the resistance of the 4th drop-down control transistor T 8, therefore, the grid potential of the 5th drop-down control transistor T 11 is for approaching the second low level VGL2, therefore, the 5th drop-down control transistor T 11 is roughly closed, so, the drain potential of the 6th drop-down control transistor T 12 (, the second end b of described drop-down unit) be the second low level VGL2, it is hereby ensured that the first output pull-down transistor T2 thoroughly closes in pre-charging stage, to guarantee carrying out smoothly of pre-charging stage.
In evaluate phase, drop-down control transistor T the 8, the 5th drop-down control transistor T 11 of the 3rd drop-down control transistor T the 7, the 4th and the 6th drop-down control transistor T 12 are all closed.
At reseting stage, the 3rd drop-down control transistor T 7 and the 5th drop-down control transistor T 11 are opened, the 4th drop-down control transistor T 8 and the 6th drop-down control transistor T 12 are closed, the current potential at the second end b place of described drop-down unit is high level, can make reset transistor T4 open, on draw node to discharge.
In the inoperative stage, the 3rd drop-down control transistor T 7 and the alternating state of the 5th drop-down control transistor T 11 in opening and closing, pull-down node PD can be in alternating voltage state.
In order to make the structure of shifting deposit unit simpler, the third embodiment as shown in Figure 9, the first drop-down module 13a can comprise the 7th drop-down control transistor T 13 and drop-down capacitor C 2, one end of this drop-down capacitor C 2 is connected with second clock signal input part CLKB, the other end of drop-down capacitor C 2 is connected with the second end b of described drop-down unit, the grid of the 7th drop-down control transistor T 13 is connected with the second driving signal input 14, the source electrode of the 7th drop-down control transistor T 13 is connected with described the second low level input end, the drain electrode of the 7th drop-down control transistor T 13 is connected with the second end b of described drop-down unit, the second end b of described drop-down unit is connected with the 3rd end c of described drop-down unit.
In pre-charging stage, drop-down capacitor C 2 is charged, the 7th drop-down control transistor T 13 conductings, because the resistance of drop-down capacitor C 2 is greater than the resistance of the 7th drop-down control transistor T 13, therefore the current potential at the second end b place of described drop-down unit approaches the second low level VGL2.
In evaluate phase, the 7th drop-down control transistor T 13 is closed, and drop-down capacitor C 2 stops charging.
At reseting stage, the 7th drop-down control transistor T 13 is closed, 2 chargings of drop-down capacitor C and, making the current potential at the second end b place of drop-down unit is high level VGH, makes reset transistor T4 unlatching, on draw node PU to discharge.
In the inoperative stage, the 7th drop-down control transistor T 13 is closed, and drop-down capacitor C 2 is the state in charging and power-off alternately, thereby exchanges drop-down to pull-down node PD.
Preferably, in shifting deposit unit provided by the utility model, the first pull up transistor at least one in T1, the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 is depletion mode transistor.Further preferably, the first pull up transistor T1, the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 can be all depletion mode transistor.In background technology, described the advantage of depletion mode transistor, repeated no more here.
In several embodiments provided by the utility model, first pulls up transistor, and T1, first exports pull-down transistor T2, switching transistor T3 and reset transistor T4 is N channel thin-film transistor.
As another one of the present utility model aspect, as shown in figure 11, a kind of shift register is also provided, this shift register comprises multistage shifting deposit unit, wherein, described shifting deposit unit is above-mentioned shifting deposit unit provided by the utility model, the first driving signal input 10(n of shifting deposit unit described in next stage) drive signal output part 11(n-1 with first of shifting deposit unit described in upper level) be connected.Herein, n representative is natural number.
Should be understood that, 10(1) representative is the first driving signal input of first order shifting deposit unit, 11(1) representative is that first of first order shifting deposit unit drives signal output part, 10(n-1) representative is the first driving signal input of (n-1) level shifting deposit unit, 11(n-1) representative is that first of (n-1) level shifting deposit unit drives signal output part, 10(n) representative is the first driving signal input of n level shifting deposit unit, 11(n) representative is that first of n level shifting deposit unit drives signal output part, V
ddand V
ssrepresentative is positive pole and the negative pole for the power supply of shift LD list device power supply respectively.
When described shifting deposit unit comprises the second driving signal output module, second of upper level shifting deposit unit drives signal output part 12(n-1) with the second driving signal input 14(n of next stage shifting deposit unit) be connected.
In Figure 11,14(1) represent the second driving signal input of first order shifting deposit unit, 12(1) represent that second of first order shifting deposit unit drives signal output part; 14(n-1) represent the second driving signal input of (n-1) level shifting deposit unit unit, 12(n-1) represent that second of (n-1) level shifting deposit unit drives signal output part; 14(n) represent the second driving signal input of n level shifting deposit unit, 12(n) represent that second of n level shifting deposit unit drives signal output part.
Depletion mode transistor can be applied in shifting deposit unit provided by the utility model.
As an also aspect of the present utility model, a kind of display device is provided, this display device comprises thin film transistor (TFT), data line, grid line and the shift register being electrically connected to this grid line, wherein, described shift register is above-mentioned shift register provided by the utility model, and the driving signal output part of described shift register is connected with described grid line.
The same with prior art, described display device can comprise many grid lines and many data lines, many data lines and many grid lines intersect to form a plurality of pixel cells, in each pixel cell, be provided with a thin film transistor (TFT), every one-level shifting deposit unit and a corresponding connection of grid line, open thin film transistor (TFT) by providing high level VGH to grid line.
In described display device, in gate drivers, the used first pull up transistor T1, the first output pull-down transistor T2, switching transistor T3 and reset transistor T4 can be all depletion mode transistor.In background technology, described the advantage of depletion mode transistor, repeated no more here.
Be understandable that, above embodiment is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (12)
1. a shifting deposit unit, this shifting deposit unit comprises the first driving signal input, first drives signal output part, the first clock signal input terminal, first pulls up transistor, the first output pull-down transistor, switching transistor, reset transistor and bootstrap capacitor, the drain electrode of described switching transistor is connected with described the first driving signal input, the drain electrode of described the first output pull-down transistor and described first drives signal output part to be connected, one end of described bootstrap capacitor is connected with described the first grid pulling up transistor, the other end and described first drives signal output part to be connected, described the first grid pulling up transistor is connected with the source electrode of described switching transistor, described the first drain electrode pulling up transistor is connected with described the first clock signal input terminal, described the first drain electrode pulling up transistor and described first drives signal output part to be connected, the drain electrode of described reset transistor is connected with the source electrode of described switching transistor, it is characterized in that, described shifting deposit unit also comprises drop-down unit, the first end of this drop-down unit is connected with the grid of described switching transistor, the second end of described drop-down unit is connected with the grid of described reset transistor, the 3rd end of described drop-down unit is connected with the grid of described the first output pull-down transistor, the source electrode of described reset transistor with can export second low level the second low level input end and be connected, the source electrode of described the first output pull-down transistor with can export the 3rd low level the 3rd low level input end and be connected, in evaluate phase, described drop-down unit can be to the grid of described the first output pull-down transistor, the grid of described switching transistor and the grid of described reset transistor are exported the first low level, described the first low level and described the second low level difference are less than the threshold voltage of described reset transistor, described the first low level and described the 3rd low level difference are less than the threshold voltage of described the first output pull-down transistor.
2. shifting deposit unit according to claim 1, it is characterized in that, this shifting deposit unit comprises the first drop-down module and the second drop-down module, described the first drop-down module is for exporting the second low level in pre-charging stage to described the second end and described the 3rd end, this second low level and described the 3rd low level difference are less than the threshold voltage of described the first output pull-down transistor, and described the second drop-down module is for exporting described the first low level in described evaluate phase to described the second end and described the 3rd end.
3. shifting deposit unit according to claim 2, it is characterized in that, this shifting deposit unit comprises the second driving signal output part, this second driving signal output part and described first drives signal output part to synchronize, and can export high level and described the first low level, described the second drop-down module comprises the first drop-down control transistor and the second driving signal input, the transistorized grid of this first drop-down control and described second drives signal output part to be connected, the transistorized source electrode of described the first drop-down control is connected with described the first low level input end, the transistorized drain electrode of described the first drop-down control is connected with described the 3rd end with described the second end, described the second driving signal input is synchronizeed with described the first driving signal input, and described the second driving signal input can input high level and described the first low level, described the second driving signal input is connected with first end.
4. shifting deposit unit according to claim 3, it is characterized in that, described the second drop-down module also comprises the second drop-down control transistor, the transistorized grid of this second drop-down control and described second drives signal output part to be connected, the transistorized source electrode of described the second drop-down control is connected with described the first low level input end, and the transistorized drain electrode of described the second drop-down control is connected with described first end.
5. according to the shifting deposit unit described in claim 3 or 4, it is characterized in that, this shifting deposit unit also comprises the second driving signal output module, this the second driving signal output module comprises that second pulls up transistor and the second output pull-down transistor, described the second grid pulling up transistor is connected with described the first grid pulling up transistor, described the second drain electrode pulling up transistor is connected with described the first clock signal input terminal, described the second source electrode pulling up transistor and described second drives signal output part to be connected, the grid of described the second output pull-down transistor is connected with the grid of described the first output pull-down transistor, the source electrode of described the second output pull-down transistor is connected with described the first low level input end, the drain electrode of described the second output pull-down transistor and described second drives signal output part to be connected.
6. according to the shifting deposit unit described in claim 3 or 4, it is characterized in that, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 3rd drop-down control transistor and the 4th drop-down control transistor, the transistorized resistance of described the 4th drop-down control is less than the resistance of the 3rd pull-down transistor, the transistorized grid of described the 3rd drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 3rd drop-down control is connected with described the second end, the transistorized grid of described the 4th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 4th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 4th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
7. according to the shifting deposit unit described in claim 3 or 4, it is characterized in that, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 3rd drop-down control transistor, the 4th drop-down control transistor, the 5th drop-down control transistor and the 6th drop-down control transistor, the transistorized resistance of described the 4th drop-down control is less than the resistance of the 3rd pull-down transistor, the transistorized resistance of described the 6th drop-down control is less than the transistorized resistance of described the 5th drop-down control, the transistorized grid of described the 3rd drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 3rd drop-down control is connected with the transistorized drain electrode of described the 4th drop-down control, the transistorized grid of described the 4th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 4th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 4th drop-down control is connected with the transistorized source electrode of described the 3rd drop-down control, the transistorized grid of described the 5th drop-down control is connected with described second clock signal input part with drain electrode, the transistorized source electrode of described the 5th drop-down control is connected with described the second end, the transistorized grid of described the 6th drop-down control is connected with described second clock signal input part, the transistorized source electrode of described the 6th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 6th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
8. according to the shifting deposit unit described in claim 3 or 4, it is characterized in that, described shifting deposit unit also comprises second clock signal input part, this second clock signal input part is contrary with described the first clock signal input terminal, described the first drop-down module comprises the 7th drop-down control transistor and drop-down electric capacity, the resistance of this drop-down electric capacity is greater than the transistorized resistance of described the 7th drop-down control, one end of described drop-down electric capacity is connected with described second clock signal input part, the other end of described drop-down electric capacity is connected with described the second end, the transistorized grid of described the 7th drop-down control is connected with described the second driving signal input, the transistorized source electrode of described the 7th drop-down control is connected with described the second low level input end, the transistorized drain electrode of described the 7th drop-down control is connected with described the second end, described the second end is connected with described the 3rd end.
9. shifting deposit unit according to claim 1, is characterized in that, described first pulls up transistor, at least one in the first output pull-down transistor, switching transistor, reset transistor be depletion mode transistor.
10. shifting deposit unit according to claim 9, is characterized in that, described first pulls up transistor, the first output pull-down transistor, switching transistor, reset transistor be N channel thin-film transistor.
11. 1 kinds of shift registers, this shift register comprises multistage shifting deposit unit, it is characterized in that, described shifting deposit unit is the shifting deposit unit described in any one in claim 1 to 10, and first of the first driving signal input of shifting deposit unit and shifting deposit unit described in upper level drives signal output part to be connected described in next stage.
12. 1 kinds of display device, this display device comprises thin film transistor (TFT), data line, grid line and the shift register being electrically connected to this grid line, it is characterized in that, described shift register is the shift register described in claim 11, and first of described shift register drives signal output part to be connected with described grid line.
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| CN201320487520.0U CN203422915U (en) | 2013-08-09 | 2013-08-09 | Shift register unit, shift register and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103440839A (en) * | 2013-08-09 | 2013-12-11 | 京东方科技集团股份有限公司 | Shift registering unit, shift register and display device |
| CN104810003A (en) * | 2015-05-21 | 2015-07-29 | 合肥京东方光电科技有限公司 | Shifting register, driving method of shifting register, grid driving circuit and display device |
| WO2016141652A1 (en) * | 2015-03-09 | 2016-09-15 | 京东方科技集团股份有限公司 | Shift register unit, shift register, display panel and display device |
| CN108010494A (en) * | 2016-10-31 | 2018-05-08 | 乐金显示有限公司 | Gate drivers and the display device using the gate drivers |
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2013
- 2013-08-09 CN CN201320487520.0U patent/CN203422915U/en not_active Withdrawn - After Issue
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| CN103440839A (en) * | 2013-08-09 | 2013-12-11 | 京东方科技集团股份有限公司 | Shift registering unit, shift register and display device |
| WO2015018149A1 (en) * | 2013-08-09 | 2015-02-12 | 京东方科技集团股份有限公司 | Shift register unit, shift register, gate driver and display panel |
| CN103440839B (en) * | 2013-08-09 | 2016-03-23 | 京东方科技集团股份有限公司 | Shifting deposit unit, shift register and display device |
| US9396813B2 (en) | 2013-08-09 | 2016-07-19 | Boe Technology Group Co., Ltd. | Shift register cell, shift register, gate driver and display panel |
| WO2016141652A1 (en) * | 2015-03-09 | 2016-09-15 | 京东方科技集团股份有限公司 | Shift register unit, shift register, display panel and display device |
| US10403228B2 (en) | 2015-03-09 | 2019-09-03 | Boe Technology Group Co., Ltd. | Shift register unit, shift register, display panel and display device |
| CN104810003A (en) * | 2015-05-21 | 2015-07-29 | 合肥京东方光电科技有限公司 | Shifting register, driving method of shifting register, grid driving circuit and display device |
| US10121437B2 (en) | 2015-05-21 | 2018-11-06 | Boe Technology Group Co., Ltd. | Shift register and method for driving the same, gate driving circuit and display device |
| CN108010494A (en) * | 2016-10-31 | 2018-05-08 | 乐金显示有限公司 | Gate drivers and the display device using the gate drivers |
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