CN202736497U - Shifting register unit, shifting register and display device - Google Patents
Shifting register unit, shifting register and display device Download PDFInfo
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- CN202736497U CN202736497U CN2012203726261U CN201220372626U CN202736497U CN 202736497 U CN202736497 U CN 202736497U CN 2012203726261 U CN2012203726261 U CN 2012203726261U CN 201220372626 U CN201220372626 U CN 201220372626U CN 202736497 U CN202736497 U CN 202736497U
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Abstract
Description
Technical field
The utility model relates to the organic light emitting display field, relates in particular to a kind of shift register cell, shift register and display device.
Background technology
Along with the development of flat pannel display, high resolving power, narrow frame becomes the trend of development, and will realize high resolving power, narrow frame demonstration, integrated gate drive circuitry is most important solution on the panel.For the a-si(amorphous silicon) and the p-si(polysilicon) technology, existing various ripe shift register circuits can well be realized this target.Oxide TFT(transistor) as a kind of very potential semiconductor technology, simpler than p-si technique, cost is lower, higher than the a-si mobility, thereby more and more come into one's own, be likely the OLED(Organic Light Emitting Diode future), the flexible main flow backboard Driving technique that shows.Yet oxide TFT is a kind of depletion mode transistor, and above-mentioned a-si TFT and p-si TFT are the transistor of enhancement mode.
Fig. 1 is the circuit diagram of traditional basic shift register cell.As shown in Figure 1, this basic shift register cell comprise draw thin film transistor (TFT) T1, pull-down thin film T2, bootstrap capacitor C1, on draw control thin film transistor (TFT) T3, drop-down control thin film transistor (TFT) T4, memory capacitance C2, the first clock signal input terminal CK, second clock signal input part CKB, input end Input, reset terminal Reset and output terminal Output;
On draw node (PU point) to be the node that is connected with the grid of T1, pull-down node (PD point) is the node that is connected with the grid of T2;
And from input end Input input start signal STV, VGL is low level.
Fig. 2 is the sequential chart of basic shift register cell each signal when work as shown in Figure 1, and VGH is high level.
When using the circuit of this basic shift register cell of enhancement mode TFT fabrication techniques, the circuit of the shift register cell that this is basic can work, see Fig. 2 solid line part, if yet when using oxide transistor (depletion mode transistor) to make this circuit, because pull-down transistor can't be closed, circuit malfunction is seen Fig. 2 dotted portion.
The difference of enhancement transistor and depletion mode transistor is seen Fig. 3 and Fig. 4, and Fig. 3 is the performance diagram of enhancement transistor, and the longitudinal axis of Fig. 3 is the drain current i of enhancement transistor D, the transverse axis of Fig. 3 is the gate source voltage V of enhancement transistor Gs, from Fig. 3, can see, when Vgs is zero, i DBe zero, illustrate that enhancement transistor was closed fully when Vgs was zero; Fig. 4 is the performance diagram of depletion mode transistor, and the longitudinal axis of same Fig. 4 is the drain current i of depletion mode transistor D, the transverse axis of Fig. 4 is the gate source voltage Vgs of depletion mode transistor, is Vgs when being zero but Fig. 4 shows, i DMuch larger than zero, and only at gate source voltage Vgs be-during 6V, i DJust be zero, therefore, be that 0 o'clock depletion mode transistor still is in conducting state at gate source voltage Vgs, can't close, so the existing circuit that uses a-si technology or p-si technology to work, when using oxide transistor to make, because oxide transistor can not be closed, leakage current is larger, so the circuit of traditional basic shift register cell as described in Figure 1 is just no longer applicable.
The utility model content
Fundamental purpose of the present utility model is to provide a kind of shift register cell, shift register and display device, with the impact on shift register of the leakage problem that solves depletion type TFT.
In order to achieve the above object, the utility model provides a kind of shift register cell, comprising:
Be used for will drawing node to move high level in evaluate phase, and pull down to first low level the first output control module at reseting stage, its with on draw node to be connected;
Be used in reseting stage and inoperative stage pull-down node being moved to the second output control module of high level, it is connected with pull-down node;
Be used for by classification output carry signal and driving signal, and so that keep high level and keep low level classification output module in reseting stage, pre-charging stage and inoperative stage in evaluate phase at described driving signal, respectively with on draw node, pull-down node, carry signal output terminal and be connected signal output part and be connected;
Be used for keeping electric capacity in evaluate phase by described the first output control module node level that draws that to keep the described level that draws node be high level, be connected between described the first low level output end and the transistorized source electrode of described the first film.
During enforcement, described the first output control module comprises the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT); Described the first film transistor, grid is connected with described input end with drain electrode, and source electrode is connected with the drain electrode of described the second thin film transistor (TFT); Described the second thin film transistor (TFT), grid is connected with described input end, source electrode with described on draw node to be connected; Described the 3rd thin film transistor (TFT), grid is connected with reset terminal, source electrode is connected source electrode with the drain electrode of described the 4th thin film transistor (TFT) respectively and is connected with the first film, drain electrode with described on draw node to be connected; Described the 4th thin film transistor (TFT), grid is connected with described reset terminal, and source electrode is connected with the first low level output end.
During enforcement, described classification output module comprises:
Be used for pre-charging stage, reseting stage and inoperative stage under the control of described the first output control module and the second output control module so that the carry signal output terminal is exported the first low level, and evaluate phase under the control of described the first output control module and the second output control module so that the carry output unit of carry signal output terminal output high level be connected with described the first output control module, described the second output control module and the carry signal output terminal of being connected respectively;
Be used under the control of described the first output control module and the second output control module, exporting high level so that drive signal output part in evaluate phase, and under the control of described the first output control module and the second output control module, export second low level driver output unit so that drive signal output part in pre-charging stage, reseting stage and inoperative stage, be connected with described the first output control module, described the second output control module and the driving signal output part of being connected respectively.
During enforcement, described carry output unit comprises the first carry output film transistor and the second carry output film transistor; Described driver output unit comprises that first drives thin film transistor (TFT), the second driving thin film transistor (TFT) and bootstrap capacitor;
Described the first carry output control thin film transistor (TFT), grid is connected with described the first output control module, and source electrode is connected with described carry signal output terminal, and drain electrode is connected with clock signal input terminal;
Described the second carry output film transistor, grid is connected with described the second output control module, and source electrode is connected with the first low level output end, and drain electrode is connected with described carry signal output terminal;
Be parallel with described bootstrap capacitor between the grid of described the first driving thin film transistor (TFT) and the source electrode;
Described first drives thin film transistor (TFT), and grid is connected with described the first output control module, and source electrode is connected with described driving signal output part, and drain electrode is connected with described clock signal input terminal;
Described second drives thin film transistor (TFT), and grid is connected with described the second output control module, and source electrode is connected with the second low level output end, and drain electrode is connected with described driving signal output part.
During enforcement, the second low level is greater than the first low level.
During enforcement, described the second output control module comprises drop-down control thin film transistor (TFT) and drop-down electric capacity, wherein:
Described drop-down control thin film transistor (TFT), grid with described on draw node to be connected, source electrode is connected with the first low level output end, drain electrode respectively with described pull-down node be connected the first end of drop-down electric capacity and be connected;
The second end of described drop-down electric capacity is connected with described clock signal input terminal.
During enforcement, described the first carry output film transistor, described the second carry output film transistor, described first drive thin film transistor (TFT) and described the second driving thin film transistor (TFT) all is the depletion type thin film transistor (TFT).
The present invention also provides a kind of shift register, comprises multistage above-mentioned shift register cell;
Except first order shift register cell, the input end of every one-level shift register cell is connected the carry signal output terminal and is connected with the upper level shift register cell;
Except the afterbody shift register cell, the reset terminal of every one-level shift register cell is connected the carry signal output terminal and is connected with the next stage shift register cell;
The input end access start signal of first order shift register cell;
The driving signal of the reset terminal access afterbody shift register cell output of afterbody shift register cell.
The invention provides a kind of display device, comprise above-mentioned shift register.
Compared with prior art, shift register cell described in the utility model, shift register and display device, drawing the node level to keep electric capacity in the utilization, to keep the level that draws node in evaluate phase be high level, thereby go to stablize described classification output module comprises with on draw that node is connected the existing current potential of source electrode of thin film transistor (TFT) that is used for drawing driving, so that drew the thin film transistor (TFT) that drives signal when grid potential is drop-down on should being used for, the voltage difference of grid and source electrode less than zero simultaneously less than threshold voltage, therefore for depletion mode transistor, it is in closed condition, greatly reduced leakage current, draw node potential by drop-down on having prevented, thereby solved the electric leakage problem of depletion type shift register circuit, guaranteed the normal operation of shift register cell; And adopted the classification output module, by classification output carry signal and driving signal, and so that keep high level and keep low level in reseting stage, pre-charging stage and inoperative stage in evaluate phase at described driving signal, thereby solve the leakage problem of depletion type TFT to the impact of the driving signal of shift register cell.
Description of drawings
Fig. 1 is the circuit diagram of traditional basic shift register cell;
Fig. 2 is the sequential chart of this basic shift register cell each signal when work;
Fig. 3 is the performance diagram of enhancement transistor;
Fig. 4 is the performance diagram of depletion mode transistor;
Fig. 5 is the circuit diagram of the first embodiment of shift register cell described in the utility model;
Fig. 6 is the circuit diagram of the second embodiment of shift register cell described in the utility model;
Fig. 7 is the circuit diagram of the 3rd embodiment of shift register cell described in the utility model;
Fig. 8 is the sequential chart of each signal of the 3rd embodiment when work of shift register cell described in the utility model;
Fig. 9 is the circuit diagram of the 4th embodiment of shift register cell described in the utility model;
Figure 10 is the circuit diagram of an embodiment of shift register described in the utility model.
Embodiment
For so that the purpose of this utility model, technical scheme and advantage are expressed clearlyer, below in conjunction with drawings and the specific embodiments the utility model is further described in detail again.
The utility model provides a kind of shift register cell, shift register and display device, with the impact on shift register of the leakage problem that solves depletion type TFT.
As shown in Figure 5, the first embodiment of shift register cell described in the utility model comprises:
The first output control module 51, its with on draw node PU to be connected, be used for will drawing node to move high level in evaluate phase, will draw node to pull down to the first low level at reseting stage;
The second output control module 52, it is connected with pull-down node PD, is used for moving pull-down node to high level at reseting stage and inoperative stage;
Described the first output control module 51 comprises the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4;
Described the first film transistor T 1, grid and drain electrode and input end Input(n) be connected, the drain electrode of described the second thin film transistor (TFT) T2 of source electrode connects;
Described the second thin film transistor (TFT) T2, grid and described input end Input(n) be connected, source electrode with described on draw node PU to be connected;
Described the 3rd thin film transistor (TFT) T3, grid and reset terminal RST(n) be connected, source electrode is connected with the source electrode that the drain electrode of described the 4th thin film transistor (TFT) T4 is connected with the first film transistor T respectively, drain electrode with described on draw node PU to be connected;
Described the 4th thin film transistor (TFT) T4, grid and reset terminal RST(n) be connected, source electrode is connected with the first low level output end;
The first embodiment of shift register cell described in the utility model also comprises:
Classification output module 53, respectively with on draw node (PU point), pull-down node (PD point), carry signal output terminal CA(n) be connected signal output part OUT(n) be connected, be used for by classification output carry signal and driving signal, and so that keep high level and keep low level in reseting stage and pre-charging stage and inoperative stage in evaluate phase at described driving signal;
On draw the node level to keep capacitor C 1, be connected between the transistorized source electrode T1 of described the first low level output end and described the first film, be used for keeping by described the first output control module 51 in evaluate phase that described to draw the level of node (PU point) be high level;
The carry signal output terminal of the first embodiment of shift register cell described in the utility model and the input end Input(n+1 of next stage shift register cell) be connected, also with the reset terminal RST(n-1 of upper level shift register cell) be connected (not showing among Fig. 5);
The M point is the node that is connected with the source electrode of described the first film transistor T 1, and described the first low level output end is exported the first low level VGL1.
The first embodiment of shift register cell described in the utility model mainly is to draw the node level to keep capacitor C 1 on using to keep in evaluate phase that described to draw the level of node (PU point) be high level.Concrete operation mainly is the existing current potential by the source electrode of the capacitor C 1 stable thin film transistor (TFT) (not showing among Fig. 5) that is connected with the PU point, so that this thin film transistor (TFT) is when grid potential is drop-down, the voltage difference of grid and source electrode less than zero simultaneously less than threshold voltage, therefore for depletion mode transistor, it is in closed condition, greatly reduced leakage current, prevented that PU point current potential is by drop-down, thereby solved the electric leakage problem of depletion type shift register circuit, guaranteed the normal operation of shift register cell.
And, in the first embodiment of shift register cell described in the utility model, adopted described classification output module 53, by classification output carry signal and driving signal, and so that keep high level and keep low level in reseting stage and pre-charging stage and inoperative stage in evaluate phase at described driving signal, thereby solve the leakage problem of depletion type TFT to the impact of the driving signal of shift register cell.
As shown in Figure 6, the circuit diagram of the second embodiment of shift register cell described in the utility model.The second embodiment of shift register cell described in the utility model is based on the first embodiment of shift register cell described in the utility model.In this second embodiment, described classification output module 53 comprises driver output unit 531 and carry output unit 532, wherein,
Described carry output unit 532 adopts the first low level output end to drive;
Described driver output unit 531 adopts the second low level output end to drive;
Described carry output unit 532, be used for pre-charging stage, reseting stage and inoperative stage under the control of described the first output control module 51 so that carry signal output terminal CA(n) output the first low level VGL1, and evaluate phase under the control of the second output control module so that carry signal output terminal output high level;
Described driver output unit 531, be used for evaluate phase under the control of described the second output control module 52 and the first output control module 51 so that drive signal output part OUT(n) the output high level, and reseting stage under the control of the first output control module 51 and the second output control module 52 so that drive signal output part OUT(n) output the second low level VGL2.
Described the first low level output end is exported the first low level VGL1, and described the second low level output end is exported the second low level VGL2;
Described the first low level VGL1 is different with the second low level VGL2, thereby avoids the leakage problem of depletion type TFT on the impact of the driving signal of shift register cell.
As shown in Figure 7, the circuit diagram of the 3rd embodiment of shift register cell described in the utility model.The 3rd embodiment of shift register cell described in the utility model is based on the second embodiment of shift register cell described in the utility model.In the 3rd embodiment,
Described carry output unit 532 comprises the first carry output film transistor T 5 and the second carry output film transistor T 6;
Described driver output unit 531 comprises that first drives thin film transistor (TFT) T7, the second driving thin film transistor (TFT) T8 and bootstrap capacitor C2;
Described the first carry output film transistor T 5, grid is connected with described the first output control module 51, source electrode and described carry signal output terminal CA(n) be connected, drain electrode is connected with clock signal input terminal;
Be parallel with described bootstrap capacitor C2 between the grid of described the first driving thin film transistor (TFT) T7 and the source electrode;
Described first drives thin film transistor (TFT) T7, and grid is connected with described the first output control module 51, source electrode and described driving signal output part OUT(n) be connected, drain electrode is connected with described clock signal input terminal;
Described the second carry output film transistor T 6, grid is connected with described the second output control module 52, source electrode is connected with the first low level output end, drain electrode and described carry signal output terminal CA(n) be connected;
Described second drives thin film transistor (TFT) T8, and grid is connected with described the second output control module 52, and source electrode is connected with the second low level output end, drain electrode and described driving signal output part OUT(n) be connected;
Described the first output control module 51 also respectively with the first low level output end be connected input end Input(n) be connected;
Described the second output control module 52 also is connected with the first low level output end.
Further, T5, T6, T7 and T8 are N-shaped TFT(thin film transistor (TFT)s);
Further, described the first carry output film transistor T 5, described the second carry output film transistor T 6, described the first driving thin film transistor (TFT) T7 and described the second driving thin film transistor (TFT) T8 are the depletion type thin film transistor (TFT)s;
Wherein, from clock signal input terminal input clock signal CK, described the first low level output end is exported the first low level VGL1, and described the second low level output end is exported the second low level VGL2, and VGL1＜VGL2.
In the 3rd embodiment of shift register cell described in the utility model, the PU point is the node that is connected with the grid of described the first carry output control thin film transistor (TFT) T5, and the PD point is the node that is connected with the grid of described the second carry output control thin film transistor (TFT) T6.PU point current potential, PD point current potential are controlled by the first output control module 51, the second output control module 52 respectively.
The 3rd embodiment of shift register cell described in the utility model has used two different drop-down current potentials: VGL1 and VGL2, a drop-down current potential VGL2 is used for driving signal output, a drop-down current potential VGL1 is used for feedback and carry signal output, and VGL2 is greater than VGL1, the importation of shift register cell at the corresponding levels and the part that resets have been used two TFT series connection simultaneously, the centre of two TFT connects together, and is connected in the M point with capacitor C 1.The other clock signal C K that needs of the 3rd embodiment of shift register cell described in the utility model, high level is VGH, low level is VGL1; The signal function of the second output control module 52 outputs is in the PD point, and high level is VGH, and low level is VGL1; According to shift register cell at the corresponding levels and the reset terminal RST (n-1) of upper level shift register cell and being connected of the input end Input (n+1) that is connected the next stage shift register cell, as can be known the input end Input(n of shift register cell at the corresponding levels) and reset terminal RST(n) high level, the low level of the signal that receives be respectively VGH, VGL1.
As shown in Figure 8, the course of work of the 3rd embodiment of shift register cell described in the utility model is divided into three phases:
First stage is pre-charging stage S1: clock signal input terminal and reset terminal RST(n) output the first low level VGL1, input end Input(n) output high level VGH, therefore T1, T2 open, and, also by the M point C1 are charged simultaneously to bootstrap capacitor C2 charging by the PU point; Because the source voltage of T4 is VGL1, while RST(n) current potential also is VGL1, therefore be 0 Vgs(gate source voltage for T4), T4 is in certain opening (corresponding its family curve, can see that it is in linear zone, certain resistance is arranged), along with input end Input(n) to the charging of C1, M point current potential raises rapidly, for T3, its source potential is the current potential that M is ordered, and the grid potential of T3 is VGL1, so the Vgs of T3 is less than 0, after M point current potential rises to certain value, T3 thoroughly closes, because T3 closes, the current potential that PU is ordered can arrive VGH very soon; And the current potential that PD is ordered is VGL1, and the Vgs of T6 is that 0, T6 opens; For T8, because VGL2 is greater than VGL1, the Vgs of T8 is less than 0, so T8 closes.Because the rising of PU point current potential, T5, T7 open, OUT(n) output low level VGL1, CA(n) output low level VGL1;
Second stage is that evaluate phase S2:CK saltus step is high level, input end Input(n) jump in potential is the first low level VGL1, RST(n) still export the first low level VGL1, the Vgs of T1 and the Vgs of T4 are 0, therefore T1 and T4 are in certain opening (be in linear zone, certain resistance is arranged); The grid potential of T2 and the grid potential of T3 all are VGL1, the source potential of T2 and the source potential of T3 are M point current potential, the M point is owing to being connected with C1, although C1 can slowly discharge by T1 and T4, but M point current potential can very fast saltus step not become VGL1, but slow decreasing, as long as the capacitance of C1 reaches a certain predetermined value, the potential difference (PD) at C1 two ends can keep the certain value greater than VGL1 within the time of half pulsewidth, therefore the gate source voltage Vgs of the gate source voltage Vgs of T2 and T3 is less than 0 and can guarantee that it is in closed condition, closing of T2 and T3 can remain unchanged so that PU point current potential continues as high level, therefore T5 and T7 continue to open, and the current potential that PD is ordered continues to keep low level VGL1, so T8 continues to close, T6 keeps certain opening, this moment, CK was high level, by C2 PU point current potential was further improved, and T5 and T7 further open, so OUT(n) output high level VGH, simultaneously CA(n) output high level VGH;
Phase III is that reseting stage S3:CK saltus step is the first low level VGL1, RST(n) and PD point output high level VGH, therefore T6 and T8 fully open, T3 and T4 fully open, therefore PU point and M point current potential are pulled down to VGL1, the unlatching of T6 and T8 is so that OUT(n) output VGL2, and CA(n) output VGL1;
To the EO of this shift register cell, after PU point current potential is pulled down to VGL1, because OUT(n) output VGL2, the Vgs of T7 closes less than 0, T7, therefore also can not have influence on OUT(n when CK is high level again) output.Although and T5 might be in crack opening, because the unlatching of T6, so CA(n) output VGL1.
Fig. 9 is the circuit diagram of the 4th embodiment of shift register cell described in the utility model.The 4th embodiment of shift register cell described in the utility model is based on the 3rd embodiment of shift register cell described in the utility model.
As shown in Figure 9, in the 4th embodiment, described the second output control module 52 comprise drop-down control thin film transistor (TFT) T9 and on draw capacitor C 3, wherein:
Drop-down control thin film transistor (TFT) T9, grid with described on draw node (PU point) to be connected, source electrode is connected with the first low level output end, the drain electrode respectively with described pull-down node (PD point) be connected on draw the first end of capacitor C 3 to be connected;
Draw the second end of capacitor C 3 to be connected with described clock signal input terminal on described.
Should be noted: the second output control module 52 of the present utility model has a variety of schemes; the second output control module as shown in Figure 9 is exactly one of embodiment; but the difference of the second output control module is not the essential distinction of this patent and other schemes; as long as used the technical solution of the utility model, which kind of embodiment the second output control module uses all in the protection domain of the utility model patent.
The utility model also provides a kind of shift register, comprises multistage above-mentioned shift register cell;
Except first order shift register cell, the input end of every one-level shift register cell is connected the carry signal output terminal and is connected with the upper level shift register cell;
Except the afterbody shift register cell, the reset terminal of every one-level shift register cell is connected the carry signal output terminal and is connected with the next stage shift register cell;
The input end access start signal of first order shift register cell;
The driving signal of the reset terminal access afterbody shift register cell output of afterbody shift register cell.
As shown in figure 10, an embodiment of shift register described in the utility model is connected and composed by N level shift register cell, and with the line scanner as active matrix, N is generally the line number of active matrix, and N is positive integer;
S1, S2 ..., Sn ..., SN indicates respectively is first order shift register cell, second level shift register cell ..., n level shift register cell ..., N level shift register cell;
The clock signal phase of the clock signal of the first clock signal input terminal output and the input of second clock signal input part is opposite, and dutycycle is 50%;
Wherein, the input end IN of first order shift register access inceptive impulse signal STV, STV is that high level is effective;
The driving signal of the reset terminal access afterbody shift register cell output of afterbody shift register cell;
Except first order shift register cell, the input end of every one-level shift register cell is connected the carry signal output terminal and is connected with the upper level shift register cell; Every one-level shift register has two output terminals: CA(n) for the carry signal output terminal, its respectively with the input end Input(n+1 of next stage shift register cell) be connected reset terminal RST(n-1 with the upper level shift register cell) be connected; OUT(n) for driving signal output part, it is connected with the horizontal scanning line Gn of active matrix; Wherein, n is positive integer, and n is less than or equal to N;
The clock control signal of adjacent two-stage shift register cell is anti-phase each other, such as: the clock signal input terminal of the second level shift register cell adjacent with this first order shift register cell is connected clock signal C KB if the input end of clock of first order shift register cell connects clock signal C K, and clock signal C K and clock signal C KB are anti-phase each other.
Embodiment of the present utility model also provides a kind of display device, comprises shift register as described above in Example, and described display device can comprise liquid crystal indicator, for example liquid crystal panel, LCD TV, mobile phone, liquid crystal display.Except liquid crystal indicator, described display device can also comprise the display device of organic light emitting display or other types, such as electronic reader etc.This shift register can be used as the sweep circuit of display device or gate driver circuit etc., so that the function of lining by line scan to be provided, sweep signal is delivered to the viewing area.
Above explanation is just illustrative for the utility model; and it is nonrestrictive; those of ordinary skills understand; in the situation that does not break away from the spirit and scope that claims limit; can make many modifications, variation or equivalence, but all will fall in the protection domain of the present utility model.
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012203726261U CN202736497U (en) | 2012-07-30 | 2012-07-30 | Shifting register unit, shifting register and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012203726261U CN202736497U (en) | 2012-07-30 | 2012-07-30 | Shifting register unit, shifting register and display device |
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| CN202736497U true CN202736497U (en) | 2013-02-13 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819998A (en) * | 2012-07-30 | 2012-12-12 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| WO2013152604A1 (en) * | 2012-04-13 | 2013-10-17 | 京东方科技集团股份有限公司 | Shift register unit and driving method for the same, shift register, and display device |
| CN104269145A (en) * | 2014-09-05 | 2015-01-07 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display device |
| WO2016119357A1 (en) * | 2015-01-27 | 2016-08-04 | 京东方科技集团股份有限公司 | Goa circuit and driving method therefor, display panel and display device |
| CN106297634A (en) * | 2016-08-31 | 2017-01-04 | 上海天马微电子有限公司 | A kind of shift register, gate driver circuit and driving method |
| CN107424552A (en) * | 2017-06-13 | 2017-12-01 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
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2012
- 2012-07-30 CN CN2012203726261U patent/CN202736497U/en not_active IP Right Cessation
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013152604A1 (en) * | 2012-04-13 | 2013-10-17 | 京东方科技集团股份有限公司 | Shift register unit and driving method for the same, shift register, and display device |
| CN102819998A (en) * | 2012-07-30 | 2012-12-12 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| WO2014019315A1 (en) * | 2012-07-30 | 2014-02-06 | 京东方科技集团股份有限公司 | Shift register unit, shift register and display device |
| CN102819998B (en) * | 2012-07-30 | 2015-01-14 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN104269145A (en) * | 2014-09-05 | 2015-01-07 | 京东方科技集团股份有限公司 | Shifting register, grid drive circuit and display device |
| WO2016119357A1 (en) * | 2015-01-27 | 2016-08-04 | 京东方科技集团股份有限公司 | Goa circuit and driving method therefor, display panel and display device |
| CN106297634A (en) * | 2016-08-31 | 2017-01-04 | 上海天马微电子有限公司 | A kind of shift register, gate driver circuit and driving method |
| CN106297634B (en) * | 2016-08-31 | 2019-05-10 | 上海天马微电子有限公司 | A kind of shift register, gate driving circuit and driving method |
| CN107424552A (en) * | 2017-06-13 | 2017-12-01 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
| CN107424552B (en) * | 2017-06-13 | 2019-11-05 | 京东方科技集团股份有限公司 | Shift register cell, driving method, gate driving circuit and display device |
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Granted publication date: 20130213 Effective date of abandoning: 20150114 |