CN203368918U - Test circuit - Google Patents
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- CN203368918U CN203368918U CN 201320493105 CN201320493105U CN203368918U CN 203368918 U CN203368918 U CN 203368918U CN 201320493105 CN201320493105 CN 201320493105 CN 201320493105 U CN201320493105 U CN 201320493105U CN 203368918 U CN203368918 U CN 203368918U
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Abstract
The utility model discloses a test circuit and relates to the printed circuit board test field. The upper layer and the lower layer of each core board are respectively provided with a bonding sheet for connecting with other core boards. Each core board is composed of two connection layers and a dielectric layer arranged between the two connection layers. The test circuit comprises signal layers and grounding layers, wherein each signal layer is a connection layer which is at least provided with one signal circuit; and each grounding layer is a connection layer which is not provided with a signal circuit. The projections of the signal circuits on the signal layers are not overlapped in a vertical direction. The signal circuits are divided into a standard circuit which accords with pre-set standard specifications of the signal circuits and a difference circuit which is different from one standard parameter of the pre-set standard specifications of the signal circuits. The standard circuit and the difference circuit are arranged in different signal layers.
Description
Technical field
The utility model relates to the printed circuit board test field, is specifically related to a kind of test circuit.
Background technology
At printed circuit board (PCB) (Printed Circuit Board, PCB) design, manufacture and application, the product that the high-frequency high-speed of take is feature has progressively occupied the critical role of whole industrial chain, this class wiring board is widely used on the large-scale communication class equipment of high-end server, system board, communication base station, switch etc., and this just requires the high-speed line plate to have lower loss of signal.
The high-speed line plate is generally used low-k (low Dk) material, low roughness Copper Foil to reduce loss of signal, material and Copper Foil have a certain impact to the loss tool, in addition, PCB design, manufacturing process and method of measurement all also cause appreciable impact to the loss of signal.
Therefore, how exactly measuring-signal loss, the source of correctly being familiar with loss of signal become particularly important, and this not only is related to the drain performance of product, also relates to the reasonable utilization of the resources of production, avoids increasing the problem of enterprise's intangible cost.
Current most of manufacturer is placed on eye in the measurement of new material and Copper Foil loss, but ignored the impact of wiring board design factor and technological factor, prior art does not have the unified unified test circuit that is specifically designed to the every design factor of test and technological factor yet.
The utility model content
The utility model embodiment provides a kind of test circuit, in order to by this test circuit, reaches the purpose of abundant optimized circuit plate design and processes.
A kind of test circuit that the utility model embodiment provides, described test circuit is formed by stacking by a plurality of central layers, each described central layer the upper and lower is equipped with the bonding sheet for being connected with other central layer, described central layer by two-layer conductting layer and be positioned in the middle of dielectric layer form, described test circuit comprises signals layer and ground plane;
Described signals layer is at least being provided with the conductting layer of a bars circuit;
Described ground plane is the conductting layer of signalization circuit not;
The projection in vertical direction of signal line on described signals layer is not overlapping mutually;
Described signal line is divided into the standard circuit of the standard specification that meets default signal line, and has the difference circuit of difference with wherein canonical parameter of the standard specification of default signal line; Described standard circuit and described difference circuit are positioned at the unlike signal layer.
Preferably, the set that described standard specification is following all single standard:
The anti-pad anti-pad diameter of signal line, signal line length, the wide annular ring of becate and through-hole diameter drill diameter.
On the basis of above-described embodiment, preferably, described signals layer also is provided with for carrying out the copper cash of resonance test, the parallel isolated both sides that are arranged on described standard circuit of described copper cash.
On the basis of above-described embodiment, preferably, at least one standard circuit is provided with for carrying out the breach of circuit breach test.
On the basis of above-described embodiment, preferably, at least one neighbouring two-layer ground plane that is provided with the signals layer of standard circuit forms the reference layer of this signals layer by etching, on the consistent and vertical direction of the figure of described reference layer symmetrically.
On the basis of above-described embodiment, preferably, what the figure of described reference layer was following situation is any or several:
The figure of described reference layer is two independently rectangles, length is identical with the length of described standard circuit, be arranged on the both sides of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of rectangular long limit on signals layer and the outer rim of standard circuit are distinguished tangent;
The figure of described reference layer is an independently rectangle, length is identical with the length of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of rectangular whole figure on signals layer covers described standard circuit fully;
The figure of described reference layer comprises the mutual discontinuous rectangle of polylith, each rectangular length all is less than the length of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of each described rectangle on signals layer overlaps with the position of described standard circuit.
On the basis of above-described embodiment, preferably, at least one is provided with the back drill that all through holes on the signals layer of standard circuit are provided with different depth.
On the basis of an above-mentioned arbitrary embodiment, preferably, every layer signal layer is equipped with 4 bars circuits.
On the basis of above-described embodiment, preferably, the thickness of the conductting layer of part is greater than the thickness of remainder conductting layer, and the thickness of the two-layer conductting layer of same central layer is identical.
On the basis of above-described embodiment, usually, described dielectric layer consists of epoxy resin and glass fibre.
The utility model embodiment has designed the difference circuit of different size in the different layers of test circuit, and standard circuit has also been designed to different test environments, thereby provide a kind of, can carry out multiple test test circuit.
The accompanying drawing explanation
The structural representation of the signal line that Fig. 1 provides for the utility model embodiment;
The embodiment schematic diagram that Fig. 2 tests for the anti-pad that the utility model embodiment provides;
The embodiment schematic diagram of the holding wire length testing that Fig. 3 provides for the utility model embodiment;
The embodiment schematic diagram that Fig. 4 tests for the minimum annular ring that the utility model embodiment provides;
The embodiment schematic diagram that Fig. 5 tests for the resonance that the utility model embodiment provides;
The embodiment schematic diagram that Fig. 6 tests for the circuit breach that the utility model embodiment provides;
The embodiment schematic diagram that Fig. 7 a tests for the reference layer that the utility model embodiment provides;
The embodiment schematic diagram that Fig. 7 b tests for the reference layer that the utility model embodiment provides;
The embodiment schematic diagram that Fig. 7 c tests for the reference layer that the utility model embodiment provides.
Embodiment
Due in prior art when consider reducing loss of signal, structural design and the circuit of not focusing on printed circuit board (PCB) distribute, and there is no unified test circuit template.
In view of the situation, of the present utility modelly be intended to design a kind of test circuit, designed different folded structures, circuit, aperture, reference layer etc. in a circuit, for the signal integrity from line design and technique making aspect evaluation circuits itself.Owing to having simulated the different situations that may occur in reality in whole circuit, complete test so once just can provide a plurality of reference results, thereby the design personnel can make according to these reference result optimal design, Optimization Technology, finally reach the signal integrity optimization function when the actual production printed circuit board.
Particularly, the utility model embodiment provides a kind of test circuit, described test circuit is formed by stacking by multi-layer coreboard, each described central layer the upper and lower is equipped with the bonding sheet (prepreg for being connected with other central layer, be called for short the P sheet), described central layer by two-layer conductting layer and be positioned in the middle of dielectric layer form
Described test circuit comprises signals layer and ground plane;
Described signals layer is at least being provided with the conductting layer of a bars circuit;
Described ground plane is the conductting layer of signalization circuit not;
The projection in vertical direction of signal line on described signals layer is not overlapping mutually;
Described signal line is divided into the standard circuit of the standard specification that meets default signal line, and has the difference circuit of difference with wherein canonical parameter of the standard specification of default signal line; Described standard circuit and described difference circuit are positioned at the unlike signal layer.
At first, it should be noted that, this test circuit is that multiple-layer stacked forms, its concrete number of plies can be according to the situation setting in when design, usually, can be consistent with the pcb board number of plies that actual needs is produced, pcb board generally is not less than 14 layers under prior art, the thickness of every layer (as dielectric layer, P lamella and quantity, conductting layer thickness), without unanimously, only needs impedance unanimously to get final product.
In the utility model above-described embodiment, the signal line (standard circuit) that both having designed in test circuit meets standard requirements, also designed the signal line (difference circuit) that does not meet standard specification, and when design difference circuit, only allow the parameter of a standard of an arbitrary difference circuit different from standard circuit, purpose is that what impact the parameter variation meeting of single of test produces to loss of signal.Because this test circuit is provided with many difference circuits, again because these parameters and loss of signal are that linear dependence is (as larger as through-hole diameter in theory, loss is less), so the purpose of test is to have what kind of linear relationship for testing out every parameter and loss of signal in fact.
Be understandable that, every layer of how many a few bars circuit of specific design can need to be set according to test, and the signal line of every layer of design should design in different zones, and the projection on vertical direction is not overlapping, in order to avoid can influence each other when through hole is set.
In general, signal line is to form by etching, due to used for test, shape is special requirement not generally, as shown in Figure 1, generally comprise circuit main body 1.1, the circuit end points of test and be positioned at the pad pad1.2 on end points, described signal line is positioned on signals layer, by through hole 1.3, causes skin, and described through hole is holed by PCB and electroplating technology obtains, described through hole is through described pad center, with whole piece signal line electrical communication.
According to the above description, usually, the set that the default standard specification of described signal line is following all single standard:
The anti-pad anti-pad diameter of signal line, signal line length, the wide annular ring of becate and through-hole diameter drill diameter.
The standard of above-mentioned standard of take is example, below introduces in detail several tests according to above-mentioned 4 parameter designing:
1, the anti-pad of anti-pad() test:
As shown in Figure 2, at first explain the anti-pad test: due to when making the through hole 1.3 at circuit end points pad1.2 place, through hole 1.3 need to run through all layers, because ground plane is conductting layer, for through hole is not contacted with the material of conductting layer, produce circular Shi Tong district 2 by the PCB etch process on the position of the vertical corresponding described through hole in everywhere on described ground plane, be anti-pad2, and this test is exactly by making the anti-pad2 of different sizes, test the test of different anti-pad diameter e on the impact of holding wire loss.
Particularly, at described anti-pad, 4 kinds of diameters can be set, for example 20mil, 22mil, 28mil, 38mil are tetra-kinds, for fear of mutual impact, four kinds of anti-pad diameters should lay respectively on each ground plane on the vertical direction of four groups of signal lines (strip line) end points, namely, on the diametric(al) of a through hole, the diameter that the anti-pad on all ground planes etches should be consistent.Just can show according to the test result of these 4 difference circuits in test that afterwards unlike signal loss result sets up the linear relationship between loss of signal and anti-pad diameter.
2, holding wire length testing:
The purpose of this test is to design the holding wire of different length, and the test signal line length is for the impact of loss of signal.
As shown in Figure 3,3 difference circuits that length is different have been designed.In order to be beneficial to test, generally the difference circuit of the different length of design all is arranged in the same layer signals layer, it should be noted that: in order to guarantee the accurate letter of test result, the width of difference circuit, spacing should be consistent.Just can show according to the test result of these 3 difference circuits in test that afterwards unlike signal loss result sets up the linear relationship between the length of loss of signal and signal line.
3, the wide test of becate:
First the concept of minimum annular ring made an explanation, as shown in Figure 4, in figure, e is through-hole diameter, the pad diameter of the end points that the f is signal line, and minimum annular ring=f-e, and the size of this minimum annular ring also can cause different impacts to loss of signal.
In test, because drawing, needs the linear result of minimum annular ring and loss of signal a plurality of ring widthes can be set, the difference circuit that the ring width size is 5mil, 12mil, 20mil, 25mil for example can be set, distinguish the test signal integrity performance.Just can show according to the test result of these 4 difference circuits in test that afterwards unlike signal loss result sets up the linear relationship between loss of signal and minimum annular ring.
Size that it should be noted that the checking ring width is during on the affecting of loss of signal, fixedly the size of difference line width, length, spacing.
4, through-hole diameter drill diameter test:
The purpose of this test is the through-hole aperture (drill diameter) different by design, the test signal integrity performance, for example 4 difference circuits can be set respectively, through hole is set to respectively to 8mil, 12mil, 16mil and 20mil, in test, just can show according to the test result of these 4 difference circuits that afterwards unlike signal loss result sets up the linear relationship between loss of signal and through-hole diameter.
According to above-mentioned 4 specific embodiment that provide, this test circuit is after test, can draw the linear relationship of anti-pad anti-pad diameter, signal line length, the wide annular ring of becate and through-hole diameter drill diameter and the loss of signal of signal line, the more important thing is and set up the ratio of the two from the slope of linear relationship, the parameter of reference can be provided for later actual production.
On the basis of above-described embodiment, this test circuit, except having changed the parameters of signal line, is provided with outside a plurality of difference circuits, can also utilize the standard circuit of setting to carry out the emulation testing of some simulation actual scenes:
For example, resonance test:
Described signals layer also is provided with for carrying out the copper cash of resonance test, the parallel isolated both sides that are arranged on described standard circuit of described copper cash.
In this above-described embodiment, both sides in standard circuit also are provided with copper cash, for carrying out the resonance test, in order to draw better the relation between resonance and loss of signal, as shown in Figure 5, can suitably regulate the distance of copper cash and standard circuit, the different test mode of many groups is set, distance can be set to 5mil, 8mil, 10mil, 14mil.
It should be noted that, for the ease of test, generally all test groups being placed in same layer and carrying out, is exactly that the result of test is more accurate in order just to allow this test only have this single variable of copper cash for the whole selection standard circuits of signal line of testing.
Can also comprise the test of circuit breach:
Be specially, at least one standard circuit is provided with for carrying out the breach of circuit breach test.
In the present embodiment, carry out the relation of measurement circuit breach and loss of signal by the circuit breach of the different sizes of design on standard circuit, as shown in Figure 6, described circuit breach is arranged on a side of described holding wire, described circuit breach affects the effective width of standard circuit, but do not cause the circuit open circuit, for testing the impact of this signal line loss of signal in tool situation jaggy; Described circuit breach preferably is set to semicircle, described semicircular size means with longest diameter size h, this h has represented the size of circuit breach, generally by PCB expose, etch process is produced on holding wire, described circuit breach size can be controlled by the PCB exposure technology, in order to draw the linear relationship of the two, the many groups of standard circuit with circuit breach of general design are tested together, for example, can design four groups of holding wires, on two circuits of described every group of holding wire, each is with a breach; Described breach specification h is respectively 4mil, 6mil, 8mil, 10mil.
Be understandable that, all be arranged in the same layer signals layer for the ease of testing all standard circuit with the circuit breach, the purpose that standard circuit is arranged to the circuit breach, exactly for only there being variable of circuit breach, makes the result of test more accurate.
Owing in general PCB circuit board, including reference layer, be the mode that distance is the shortest, loop area is minimum with high speed signal for assurance, so can also comprise the reference layer test in this test circuit:
Specifically be preferably, at least one neighbouring two-layer ground plane that is provided with the signals layer of standard circuit forms the reference layer of this signals layer by etching, on the consistent and vertical direction of the figure of described reference layer symmetrically.
Because the figure of reference layer etching can produce different impacts to loss of signal, so the purpose of this test is to obtain the relation of reference layer figure and loss of signal, usually, what the figure of described reference layer was following situation is any or several:
As shown in Figure 7a, the figure of described reference layer is two independently rectangles, length is identical with the length of described standard circuit, be arranged on the both sides of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of rectangular long limit on signals layer and the outer rim of standard circuit are distinguished tangent;
As shown in Figure 7b, the figure of described reference layer is an independently rectangle, length is identical with the length of described standard circuit, and the position arranged matches with the position of standard circuit on signals layer, and the upright projection of rectangular whole figure on signals layer covers described standard circuit fully;
As shown in Figure 7 c, the figure of described reference layer comprises the mutual discontinuous rectangle of polylith, each rectangular length all is less than the length of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of each described rectangle on signals layer overlaps with the position of described standard circuit.
In the above-described embodiment, by in various criterion circuit above and below, etching difform reference layer, the impact of test reference layer shape on signal integrity, at corresponding various criterion signal location, difform reference layer being set can be by once testing and can draw different test results.Signal line in the reference layer test is all selected as standard circuit makes only to have test variable of reference layer shape in test exactly, is that the result of test is more accurate.
This test circuit also can comprise back drill stub length testing, particularly:
At least one is provided with the back drill that all through holes on the signals layer of standard circuit are provided with different depth.
At first back drill is once explained, in the pcb board manufacture process, in fact to can be used as be the circuit of transmission of signal to through hole, the nothing of some through hole end connects, this will cause the resonance of turning back of signal also can alleviate, the reflection that may cause signal to transmit, scattering, delay etc., bring the problem of " distortion " to signal, back drill is exactly a kind of technological means for addressing this problem, effect is the through hole section of boring to fall not play any connection or transmitting effect in fact, and signal has just been avoided the problem of " distortion " like this.
Described back drill generally completes by PCB back drill bore process, has unique a kind of diameter; Described back drill position is on through hole, can all carry out back drill to all through holes that are provided with in this layer signal layer of standard circuit, the described back drill degree of depth is controlled by described PCB back drill bore process, thereby obtain different back drill stub length, just can obtain different test results according to different back drill stub length like this in test process, thereby can obtain the linear relationship between back drill stub length and loss of signal.Because signal lines all in this test is standard circuit, only there is this variable of back drill stub length, the result of test is very accurate.
Be understandable that, a few bars circuits specifically are set on the multilayer signal layer comprised in this test circuit can need to be set according to test, the circuit of every layer of setting is more, the test result of so above-mentioned each test is more, certainly the linear relationship obtained is more accurate, for example, every layer signal layer can be equipped with 4 bars circuits.
Be understandable that, the impact of the thickness that this test circuit can also the test conduction layer on loss of signal, the thickness of conductting layer that can part is set to be greater than the thickness of remainder conductting layer, and the thickness of the two-layer conductting layer of same central layer is identical.
Owing to being provided with different conductting layer thickness, can be when the testing differentia circuit, the signals layer that same test is distributed in to different-thickness carries out, for example, when carrying out the minimum annular ring test, can be by a part of difference line design at thicker signals layer, another part difference line design, at thinner signals layer, so just can also be tested out to the impact of signals layer thickness on loss of signal in test minimum annular ring and loss of signal.
Usually, described dielectric layer and P sheet consist of epoxy resin and glass fibre.Described glass fibre can adopt various specification (main specifications has 7637,7630,7628,7615,1506,2116,2113,3313,1080,106,104), and described glass fibre also can be different from the ratio of epoxy resin as required.
Be understandable that, in order to guarantee the test result accuracy of this test circuit, should guarantee that the constituent of the bilevel dielectric layer of signals layer or P sheet is consistent with ratio, to avoid that test result is caused to interference.
In sum; the test circuit that the utility model is introduced is only protected a kind of structure of design; concrete test process and test result can utilize the equipment existed in prior art to carry out; utilize this test circuit can once test the parameter testing of carrying out a plurality of projects, for follow-up actual PCB production provides reference frame.
Obviously, those skilled in the art can carry out various changes and modification and not break away from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model also is intended to comprise these changes and modification interior.
Claims (10)
1. a test circuit, described test circuit is formed by stacking by a plurality of central layers, each described central layer the upper and lower is equipped with the bonding sheet for being connected with other central layer, described central layer by two-layer conductting layer and the dielectric layer in the middle of being positioned at form, it is characterized in that,
Described test circuit comprises signals layer and ground plane;
Described signals layer is at least being provided with the conductting layer of a bars circuit;
Described ground plane is the conductting layer of signalization circuit not;
The projection in vertical direction of signal line on described signals layer is not overlapping mutually;
Described signal line is divided into the standard circuit of the standard specification that meets default signal line, and has the difference circuit of difference with wherein canonical parameter of the standard specification of default signal line; Described standard circuit and described difference circuit are positioned at the unlike signal layer.
2. test circuit as claimed in claim 1, is characterized in that, the set that described standard specification is following all single standard:
The anti-pad anti-pad diameter of signal line, signal line length, the wide annular ring of becate and through-hole diameter drill diameter.
3. test circuit as claimed in claim 2, is characterized in that, described signals layer also is provided with for carrying out the copper cash of resonance test, the parallel isolated both sides that are arranged on described standard circuit of described copper cash.
4. test circuit as claimed in claim 2, is characterized in that, at least one standard circuit is provided with for carrying out the breach of circuit breach test.
5. test circuit as claimed in claim 2, it is characterized in that, at least one neighbouring two-layer ground plane that is provided with the signals layer of standard circuit forms the reference layer of this signals layer by etching, on the consistent and vertical direction of the figure of described reference layer symmetrically.
6. test circuit as claimed in claim 5, is characterized in that, what the figure of described reference layer was following situation is any or several:
The figure of described reference layer is two independently rectangles, length is identical with the length of described standard circuit, be arranged on the both sides of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of rectangular long limit on signals layer and the outer rim of standard circuit are distinguished tangent;
The figure of described reference layer is an independently rectangle, length is identical with the length of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of rectangular whole figure on signals layer covers described standard circuit fully;
The figure of described reference layer comprises the mutual discontinuous rectangle of polylith, each rectangular length all is less than the length of described standard circuit, and match with the position of the standard circuit on signals layer in the position arranged, the upright projection of each described rectangle on signals layer overlaps with the position of described standard circuit.
7. test circuit as claimed in claim 2, is characterized in that, at least one is provided with the back drill that all through holes on the signals layer of standard circuit are provided with different depth.
8. as an arbitrary described test circuit of claim in claim 1-7, it is characterized in that, every layer signal layer is equipped with 4 bars circuits.
9. test circuit as claimed in claim 8, is characterized in that, the thickness of the conductting layer of part is greater than the thickness of remainder conductting layer, and the thickness of the two-layer conductting layer of same central layer is identical.
10. test circuit as claimed in claim 9, is characterized in that, described dielectric layer consists of epoxy resin and glass fibre.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320493105 CN203368918U (en) | 2013-08-13 | 2013-08-13 | Test circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320493105 CN203368918U (en) | 2013-08-13 | 2013-08-13 | Test circuit |
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| Publication Number | Publication Date |
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| CN203368918U true CN203368918U (en) | 2013-12-25 |
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| CN 201320493105 Expired - Lifetime CN203368918U (en) | 2013-08-13 | 2013-08-13 | Test circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470978A (en) * | 2019-09-19 | 2019-11-19 | 浪潮商用机器有限公司 | A kind of test method and test device of PCB anti-pad |
-
2013
- 2013-08-13 CN CN 201320493105 patent/CN203368918U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110470978A (en) * | 2019-09-19 | 2019-11-19 | 浪潮商用机器有限公司 | A kind of test method and test device of PCB anti-pad |
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Address after: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee after: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee after: ZHUHAI FOUNDER TECH. HI-DENSITY ELECTRONIC Co.,Ltd. Patentee after: ZHUHAI FOUNDER PCB DEVELOPMENT Co.,Ltd. Patentee after: PKU FOUNDER INFORMATION INDUSTRY GROUP CO.,LTD. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: ZHUHAI FOUNDER TECH. HI-DENSITY ELECTRONIC Co.,Ltd. Patentee before: ZHUHAI FOUNDER PCB DEVELOPMENT Co.,Ltd. Patentee before: FOUNDER INFORMATION INDUSTRY HOLDINGS Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220922 Address after: 3007, Hengqin international financial center building, No. 58, Huajin street, Hengqin new area, Zhuhai, Guangdong 519031 Patentee after: New founder holdings development Co.,Ltd. Patentee after: ZHUHAI FOUNDER TECH. HI-DENSITY ELECTRONIC Co.,Ltd. Patentee after: ZHUHAI FOUNDER PCB DEVELOPMENT Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: ZHUHAI FOUNDER TECH. HI-DENSITY ELECTRONIC Co.,Ltd. Patentee before: ZHUHAI FOUNDER PCB DEVELOPMENT Co.,Ltd. Patentee before: PKU FOUNDER INFORMATION INDUSTRY GROUP CO.,LTD. |
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