CN203368430U - Novel solid-state switch network circuit - Google Patents

Novel solid-state switch network circuit Download PDF

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Publication number
CN203368430U
CN203368430U CN 201320440886 CN201320440886U CN203368430U CN 203368430 U CN203368430 U CN 203368430U CN 201320440886 CN201320440886 CN 201320440886 CN 201320440886 U CN201320440886 U CN 201320440886U CN 203368430 U CN203368430 U CN 203368430U
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cell
field effect
effect transistor
type field
source electrode
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CN 201320440886
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赵恩海
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YANCHENG HUIZHONG NEW ENERGY TECHNOLOGY CO., LTD.
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赵恩海
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Abstract

A novel solid-state switch network circuit employs solid-state switches formed by semiconductor devices. The anodes and the cathodes of all cells in a series battery are led out to input/output terminals of the circuit. Via the input/output terminals, the circuit performs voltage measurement and balance management of corresponding cells.

Description

A kind of novel solid switching network circuit
Technical field
The utility model relates to a kind of solid switch lattice network.The solid switch that this circuit adopts semiconductor device to form, be drawn out to the positive and negative electrode of each battery in series battery on the input/output terminal of this switching network circuit, by this input/output terminal, corresponding battery carried out to voltage measurement and balanced management.
Background technology
Rechargeable battery, as lithium battery, lead-acid battery etc., when series connection is used in groups, need the electric weight of each cell voltage of monitoring and each battery of balanced management.For the battery pack of a large amount of series connection, generally adopt application-specific integrated circuit (ASIC) or, with flying each cell voltage of capacitance measurement, adopt the conductive discharge form, in charging process, battery electric quantity is carried out to passive balanced management.Although application-specific integrated circuit (ASIC) is easy to use, cost compare is high.Traditional capacitance measurement method that flies needs the switch that speed is higher, and easily, also there is the shortcoming that cost is higher in loss of accuracy.And passive equilibrium exists euqalizing current little, the heat management difficulty, easily reduce the shortcomings such as battery cycle life.
Summary of the invention
In order to overcome, the precision that in existing measurement battery pack, each cell voltage circuit exists is low, the high in cost of production shortcoming, with overcome passive equilibrium and exist euqalizing current little, the heat management difficulty, easily reduce the shortcomings such as battery cycle life, the utility model provides a kind of novel solid switching network circuit, this circuit is drawn out to the positive and negative electrode of each battery in series battery on the input/output terminal of this switching network circuit, by this input/output terminal, corresponding battery is carried out to voltage measurement and balanced management.
The utility model solves the technical scheme that its technical problem adopts: if the series-connected cell joint number is even number, and battery Cell 1, Cell 2, Cell 3cell 2n-1, Cell 2n-1, Cell 2nbe connected into successively battery pack, the positive pole of battery pack is Cell 2npositive pole, the negative pole of battery pack is Cell 1negative pole, Cell 1, Cell 3cell 2n-1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1drain electrode, T l1, T l3t l2n-1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1source electrode, Cell 2cell 2n-2, Cell 2npositive pole connect respectively N-type field effect transistor T l2t l2n-2, T l2ndrain electrode, T l2t l2n-2, T l2nsource electrode connect respectively N-type field effect transistor T r2t r2n-2, T r2nsource electrode, Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2n-2, T r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, if the series-connected cell joint number is odd number, battery Cell 1, Cell 2, Cell 3cell 2n-1, Cell 2n, Cell 2n+1be connected into successively battery pack, the positive pole of battery pack is Cell 2n+1positive pole, the negative pole of battery pack is Cell 1negative pole, Cell 1, Cell 3cell 2n-1, Cell 2n+1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1, T l2n+1drain electrode, T l1, T l3t l2n-1, T l2n+1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1, T r2n+1source electrode, Cell 2cell 2npositive pole connect respectively N-type field effect transistor T l2t l2ndrain electrode, T l2t l2nsource electrode connect respectively N-type field effect transistor T r2t r2nsource electrode, Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1, T r2n+1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, wherein n represents random natural number.
The beneficial effects of the utility model are that circuit structure is simple, and measure error is little, and higher euqalizing current can be provided.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the utility model is further illustrated.
Fig. 1 and Fig. 2 are schematic diagrams of the present utility model.
In Fig. 1 and Fig. 2, Cell 1, Cell 2, Cell 3cell 2n-2, Cell 2n-1, Cell 2n, Cell 2n+1be battery, they are composed in series battery pack as shown in the figure successively.T l0, T r0, T l1, T r1, T l2, T r2, T l3,t r3t l2n-2, T r2n-2, T l2n-1, T r2n-1, T l2n, T r2n, T l2n+1, T r2n+1, T e0, T e1, T 00, T 01it is the N-type field effect transistor.G l0, G r0, G l1, G r1, G l2, G r2, G l3, G r3g l2n-2, G r2n-2, G l2n-1, G r2n-1, G l2n, G r2n, G l2n+1, G r2n+1, G e0, G e1, G 00, G 01respectively T l0, T r0, T l1, T r1, T l2, T r2, T l3, T r3t l2n-2, T r2n-2, T l2n-1, T r2n-1, T l2n, T r2n, T l2n+1, T r2n+1, T e0, T e1, T 00, T 01grid.I/O+ is the forward input/output terminal, and I/O-is the negative sense input/output terminal.In figure, dotted line represents abridged battery, N-type field effect transistor and connecting line thereof.
Embodiment
What Fig. 1 showed is the working method while connecting the even number batteries in battery pack.In Fig. 1, battery Cell in series battery 1, Cell 3cell 2n-1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1drain electrode, T l1, T l3t l2n-1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1source electrode, battery Cell 2cell 2n-2, Cell 2npositive pole connect respectively N-type field effect transistor T l2t l2n-2, T l2ndrain electrode, T l2t l2n-2, T l2nsource electrode connect respectively N-type field effect transistor T r2t r2n-2, T r2nsource electrode, battery Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2n-2, T r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, wherein n represents random natural number, in figure, dotted line represents abridged battery, N-type field effect transistor and connecting line thereof.
Measure or balancing battery Cell 1the time, at G l1, G r1, G l0, G r0, G 01, G e0on add the logical one signal, N-type field effect transistor T l0, T r0, T l1, T r1, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 1anodal short circuit, I/O-and Cell 1the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 1voltage or to Cell 1carry out the charge and discharge balanced management.
Measure or balancing battery Cell 2the time, at G l2, G r2, G l1, G r1, G e1, G 00on add the logical one signal, N-type field effect transistor T l2, T r2, T l1, T r1, T e1, T 00conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2anodal short circuit, I/O-and Cell 2the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2voltage or to Cell 2carry out the charge and discharge balanced management.
Measure or balancing battery Cell 3the time, at G l3, G r3, G l2, G r2, G 01, G e0on add the logical one signal, N-type field effect transistor T l3, T r3, T l2, T r2, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 3anodal short circuit, I/O-and Cell 3the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 3voltage or to Cell 3carry out the charge and discharge balanced management.
Measure or balancing battery Cell 2n-1the time, at G l2n-1, G r2n-1, G l2n-2,g r2n-2,g 01, G e0on add the logical one signal, N-type field effect transistor T l2n-1, T r2n-1, T l2n-2, T r2n-2, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2n-1anodal short circuit, I/O-and Cell 2n-1the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2n-1voltage or to Cell 2n-1carry out the charge and discharge balanced management.
Measure or balancing battery Cell 2nthe time, at G l2n, G r2n, G l2n-1, G r2n-1, G e1, G 00on add the logical one signal, N-type field effect transistor T l2n, T r2n, T l2n-1, T r2n-1, T e1, T 00conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2nanodal short circuit, I/O-and Cell 2nthe negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2nvoltage or to Cell 2ncarry out the charge and discharge balanced management.
For being connected on Cell 3and Cell 2n-1between measurement or the balanced way of battery, can be according to battery Cell 2n-1and Cell 2nmeasured or balanced mode is analogized.
What Fig. 2 showed is the working method while connecting the odd number batteries in battery pack.In Fig. 2, battery Cell in series battery 1, Cell 3cell 2n-1, Cell 2n+1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1, T l2n+1drain electrode, T l1, T l3t l2n-1, T l2n+1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1, T r2n+1source electrode, battery Cell 2cell 2npositive pole connect respectively N-type field effect transistor T l2t l2ndrain electrode, T l2t l2nsource electrode connect respectively N-type field effect transistor T r2t r2nsource electrode, battery Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1, T r2n+1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, wherein n represents random natural number, in figure, dotted line represents abridged battery, N-type field effect transistor and connecting line thereof.
Measure or balancing battery Cell 1the time, at G l1, G r1, G l0, G r0, G 01, G e0on add the logical one signal, N-type field effect transistor T l0, T r0, T l1, T r1, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 1anodal short circuit, I/O-and Cell 1the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 1voltage or to Cell 1carry out the charge and discharge balanced management.
Measure or balancing battery Cell 2the time, at G l2, G r2, G l1, G r1, G e1, G 00on add the logical one signal, N-type field effect transistor T l2, T r2, T l1, T r1, T e1, T 00conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2anodal short circuit, I/O-and Cell 2the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2voltage or to Cell 2carry out the charge and discharge balanced management.
Measure or balancing battery Cell 3the time, at G l3, G r3, G l2, G r2, G 01, G e0on add the logical one signal, N-type field effect transistor T l3, T r3, T l2, T r2, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 3anodal short circuit, I/O-and Cell 3the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 3voltage or to Cell 3carry out the charge and discharge balanced management.
Measure or balancing battery Cell 2nthe time, at G l2n, G r2n, G l2n-1, G r2n-1, G e1, G 00on add the logical one signal, N-type field effect transistor T l2n, T r2n, T l2n-1, T r2n-1, T e1, T 00conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2nanodal short circuit, I/O-and Cell 2nthe negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2nvoltage or to Cell 2ncarry out the charge and discharge balanced management.
Measure or balancing battery Cell 2n+1the time, at G l2n+1, G r2n+1, G l2n, G r2n, G 01, G e0on add the logical one signal, N-type field effect transistor T l2n+1, T r2n+1, T l2n, T r2n, T 01, T e0conducting, other N-type field effect transistor keeps off state, because the internal resistance of N-type field effect transistor is lower, can be similar to and think I/O+ and Cell 2n+1anodal short circuit, I/O-and Cell 2n+1the negative pole short circuit, therefore, can be by I/O+ and I/O-two ends Measurement accuracy Cell 2n+1voltage or to Cell 2n+1carry out the charge and discharge balanced management.
For being connected on Cell 3and Cell 2nbetween measurement or the balanced way of battery, can be according to battery Cell 2nand Cell 2n+1measured or balanced mode is analogized.

Claims (1)

1. a novel solid switching network circuit is characterized in that: if the series-connected cell joint number is even number, and battery Cell 1, Cell 2, Cell 3cell 2n-2, Cell 2n-1, Cell 2nbe connected into successively battery pack, the positive pole of battery pack is Cell 2npositive pole, the negative pole of battery pack is Cell 1negative pole, Cell 1, Cell 3cell 2n-1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1drain electrode, T l1, T l3t l2n-1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1source electrode, Cell 2cell 2n-2, Cell 2npositive pole connect respectively N-type field effect transistor T l2t l2n-2, T l2ndrain electrode, T l2t l2n-2, T l2nsource electrode connect respectively N-type field effect transistor T r2t r2n-2, T r2nsource electrode, Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2n-2, T r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, if the series-connected cell joint number is odd number, battery Cell 1, Cell 2, Cell 3cell 2n-1, Cell 2n, Cell 2n+1be connected into successively battery pack, the positive pole of battery pack is Cell 2n+1positive pole, the negative pole of battery pack is Cell 1negative pole, Cell 1, Cell 3cell 2n-1, Cell 2n+1positive pole connect respectively N-type field effect transistor T l1, T l3t l2n-1, T l2n+1drain electrode, T l1, T l3t l2n-1, T l2n+1source electrode connect respectively N-type field effect transistor T r1, T r3t r2n-1, T r2n+1source electrode, Cell 2cell 2npositive pole connect respectively N-type field effect transistor T l2t l2ndrain electrode, T l2t l2nsource electrode connect respectively N-type field effect transistor T r2t r2nsource electrode, Cell 1negative pole and N-type field effect transistor T l0drain electrode connect, T l0source electrode connect N-type field effect transistor T r0source electrode, T r1, T r3t r2n-1t r2n+1drain electrode be connected, and connect N-type field effect transistor T 00drain electrode and N-type field effect transistor T 01source electrode, T r0, T r2t r2ndrain electrode be connected, and connect N-type field effect transistor T e0drain electrode and N-type field effect transistor T e1source electrode, T 00source electrode connect T e0source electrode form negative sense input/output terminal I/O-, T 01drain electrode connect T e1drain electrode form forward input/output terminal I/O+, wherein n represents random natural number.
CN 201320440886 2013-07-24 2013-07-24 Novel solid-state switch network circuit Expired - Fee Related CN203368430U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104467774A (en) * 2013-07-24 2015-03-25 赵恩海 Switch network circuit with solid switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104467774A (en) * 2013-07-24 2015-03-25 赵恩海 Switch network circuit with solid switch

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GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: YANCHENG HUIZHONG NEW ENERGY TECHNOLOGY CO., LTD.

Free format text: FORMER OWNER: ZHAO ENHAI

Effective date: 20150615

C41 Transfer of patent application or patent right or utility model
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Address after: 224051 No. 666 Yingbin Road, Nanyang Economic Zone, Jiangsu, Yancheng City

Patentee after: YANCHENG HUIZHONG NEW ENERGY TECHNOLOGY CO., LTD.

Address before: 210036, room 36, building 602, phoenix garden, Longfeng garden, Gulou District, Nanjing, Jiangsu

Patentee before: Zhao Enhai

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20131225

Termination date: 20190724

CF01 Termination of patent right due to non-payment of annual fee