CN203365867U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN203365867U CN203365867U CN 201320490837 CN201320490837U CN203365867U CN 203365867 U CN203365867 U CN 203365867U CN 201320490837 CN201320490837 CN 201320490837 CN 201320490837 U CN201320490837 U CN 201320490837U CN 203365867 U CN203365867 U CN 203365867U
- Authority
- CN
- China
- Prior art keywords
- protective seam
- array base
- base palte
- electrode
- narrow slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The utility model provides an array substrate and a display device. The array substrate comprises a substrate, common electrodes and pixel electrodes, wherein the common electrodes have slit structures and are formed on the substrate, and the pixel electrodes have slit structures and do not overlap with the common electrodes. The scheme provided by the utility model can be favorable for reducing the storage capacitance of the common electrodes and pixel electrodes and ensuring the image quality.
Description
Technical field
The utility model relates to the display technique field, refers to especially a kind of array base palte and display device.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, the Thin Film Transistor (TFT) liquid crystal display) be to utilize the variation that is arranged on electric field intensity on liquid crystal layer, change the degree of the rotation of liquid crystal molecule, thereby the power of control printing opacity shows image.In general, complete display panels must have the layer of liquid crystal molecule of filling in backlight module group, polaroid, upper substrate (normally color membrane substrates) and infrabasal plate (normally array base palte) and the box that is comprised of their two substrates and forms.
Be formed with data line and grid line that transverse and longitudinal is intersected on array base palte, data line and grid line enclose and form the pixel cell that matrix form is arranged.Each pixel cell comprises TFT switch and pixel electrode; Wherein, the TFT switch comprises gate electrode, source electrode, drain electrode and active layer; Gate electrode connects grid line, source electrode connection data line, and drain electrode connects pixel electrode, and active layer is formed between source, drain electrode and gate electrode.
Generally also be formed with public electrode on array base palte, for pixel electrode, forming electric field, the electric field intensity between public electrode and pixel electrode changes the degree of the rotation of controlling liquid crystal molecule.
ADS-DS (ADvanced Super Dimension Switch), be called for short ADS, it is a senior super dimension switch technology, the electric field produced by electric field that in same plane, the gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved the liquid crystal work efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
As shown in Figure 1, public electrode 111 at the tft array substrate 110 of ADS pattern is very large with the memory capacitance (Cst) of pixel electrode 112, almost account for whole pixel region, large scale product particularly, after elemental area change greatly, it is larger that memory capacitance can become, usually in order to adapt to so large memory capacitance, need the larger thin film transistor (TFT) of design to be full of, larger thin film transistor (TFT) one is to take elemental area, the 2nd, the coupling capacitance Cgd of thin film transistor (TFT) itself, it is large that Cgs etc. also can become, thereby affect picture disply, thereby be subject in design a lot of restrictions, generally, solve such problem one of the most direct method be that ADS type pixel electrode 112 and public electrode 111 form state as shown in Figure 2, but current technique can't directly realize, reason is that pixel electrode 112 and public electrode 111 are all transparency electrodes, by process equipment, exposed, in the processes such as development, the contraposition effect of transparent membrane is limited, equipment can't be accomplished real structure as shown in Figure 2 at all, if because technique contraposition deviation causes the relative displacement in an effective display area territory of pixel electrode and public electrode inhomogeneous, such as a part of area pixel electrode 112 with respect to public electrode 111 to left avertence, and another part area pixel electrode 112 with respect to public electrode 111 to right avertence, there will be the interregional inequality of Cst, be reflected in picture, there will be on a display display gray scale between regional inhomogeneous, human eye perceives to be exactly between picture area the display brightness inequality cause distortion, it is very fatal display defect, and there is no good solution in prior art.
The utility model content
The technical problems to be solved in the utility model is to provide a kind of array base palte and display device, and can make the pixel electrode of array base palte and the overlapping of public electrode is 0, reduces the overlapping coupling capacitance of public electrode and pixel electrode, guarantees picture quality.
For solving the problems of the technologies described above, embodiment of the present utility model provides a kind of array base palte, comprising:
Substrate; And
Be formed at the public electrode of the narrow slit structure on described substrate, and with the pixel electrode of the overlapping narrow slit structure of described public electrode zero.
Wherein, described array base palte comprises the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure.
Wherein, the thin film transistor (TFT) of described bottom grating structure comprises: be formed at grid, grid line, gate insulation layer on described substrate, and be formed at semiconductor layer, data line, source/drain electrode on described gate insulation layer;
Also be formed with the protective seam that is positioned at the narrow slit structure on described semiconductor layer, source/drain electrode and the figure of passivation layer on described substrate, and described protective seam and passivation layer are rhythmo structure.
Wherein, in the rhythmo structure of protective seam and passivation layer, protective seam is wider than the width of passivation layer.
Wherein, the thin film transistor (TFT) of described top gate structure comprises: be formed at semiconductor layer, data line, source/drain electrode on described substrate, and be formed at grid, grid line and the gate insulation layer on source/drain electrode and data line;
Also be formed with the protective seam that is positioned at the narrow slit structure on described grid, grid line and the figure of gate insulation layer on described substrate, and described protective seam and gate insulation layer are rhythmo structure.
Wherein, in the rhythmo structure of protective seam and gate insulation layer, protective seam is wider than the width of gate insulation layer.
Wherein, the public electrode of described narrow slit structure is positioned on described protective seam figure; The pixel electrode of described narrow slit structure is formed at the slit areas in described narrow slit structure.
Wherein, described protective seam adopts inorganic insulation resin material or organic photo resin material to make.
Embodiment of the present utility model also provides a kind of display device, comprises array base palte as above.
The beneficial effect of technique scheme of the present utility model is as follows:
In such scheme, by be formed with the public electrode of narrow slit structure on substrate, and with the pixel electrode of the overlapping narrow slit structure of described public electrode zero, thereby can reduce the memory capacitance of public electrode and pixel electrode, the assurance picture quality.
The accompanying drawing explanation
The public electrode that Fig. 1 is existing array base palte and the pictorial diagram of pixel electrode;
The pictorial diagram of the pixel electrode of the narrow slit structure that Fig. 2 is existing array base palte and the public electrode of narrow slit structure;
The forming process schematic diagram that Fig. 3-Fig. 8 is array base palte of the present utility model.
Embodiment
For making the technical problems to be solved in the utility model, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.
As shown in Figure 8, embodiment of the present utility model also provides a kind of array base palte, comprising:
This array base palte adopts as the making of above-mentioned embodiment of the method obtains, and this array base palte comprises:
Wherein, described array base palte comprises the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure;
Wherein, the bottom grating structure thin film transistor (TFT) comprises: be formed at grid 12, grid line, gate insulation layer 13 on described substrate 11, and be formed at semiconductor layer 14, data line, source electrode 15 on described gate insulation layer 13, drain 16; On described substrate, also have: be formed at described semiconductor layer 14, source electrode 15, the protective seam 18 of the narrow slit structure on 16 and the figure of passivation layer drain;
And the thin film transistor (TFT) of top gate structure comprises: be formed at semiconductor layer, data line, source/drain electrode on described substrate, and be formed at grid, grid line and gate insulation layer on source/drain electrode and data line;
Also be formed with the protective seam that is positioned at the narrow slit structure on described grid, grid line and the figure of gate insulation layer on described substrate, and described protective seam and gate insulation layer are rhythmo structure;
As shown in Figure 8, in the rhythmo structure of protective seam and passivation layer, protective seam is wider than the width of passivation layer; Thereby can be used in the transparent conductive film process primary depositing of making public electrode and pixel electrode, just can obtain being positioned at the public electrode 20 of protective seam top and the pixel electrode 19 that is positioned at slit areas; And the etching of public electrode and the etching technics of pixel electrode have been saved; and because the bottom of protective seam figure covers the top of passivation layer; therefore; when the deposit transparent conductive film; the public electrode 20 be positioned on protective seam can not produce overlapping with the pixel electrode 19 be positioned on gate insulation layer; therefore, avoid the memory capacitance between public electrode and pixel electrode, guaranteed picture quality.
In top gate structure, the passivation layer of narrow slit structure is formed by gate insulation layer; In the rhythmo structure of protective seam and gate insulation layer, protective seam is wider than the width of gate insulation layer; Also can be used in the transparent conductive film process primary depositing of making public electrode and pixel electrode, just can obtain being positioned at the public electrode 20 of protective seam top and the pixel electrode 19 that is positioned at slit areas; And the etching of public electrode and the etching technics of pixel electrode have been saved; and because the bottom of protective seam figure covers the top of passivation layer; therefore; when the deposit transparent conductive film; the public electrode 20 be positioned on protective seam can not produce overlapping with the pixel electrode 19 be positioned on gate insulation layer; therefore, avoid the memory capacitance between public electrode and pixel electrode, guaranteed picture quality.
In the embodiment of above-mentioned array base palte, no matter, in above-mentioned bottom grating structure or top gate structure, pixel electrode directly overlaps with drain electrode.The public electrode 20 of described narrow slit structure is positioned on described protective seam figure; The pixel electrode 19 of described narrow slit structure is formed at the slit areas in described narrow slit structure; That is to say, between described pixel electrode and described public electrode, be formed with passivation layer and protective seam.
In addition, public electrode and pixel electrode, when making, can, by making the transparent conductive film process primary depositing of public electrode and pixel electrode, just can obtain being positioned at the public electrode 20 of protective seam top and the pixel electrode 19 that is positioned at slit areas; And the etching of public electrode and the etching technics of pixel electrode have been saved; and because the bottom of protective seam figure covers the top of passivation layer; therefore; when the deposit transparent conductive film; the public electrode 20 be positioned on protective seam can not produce overlapping with the pixel electrode 19 be positioned on gate insulation layer; therefore, avoid the memory capacitance between public electrode and pixel electrode, guaranteed picture quality.
In the embodiment of above-mentioned array base palte, the material of described protective seam can be selected photosensitive resin material or inorganic insulating material.Described public electrode 20 adopts identical metal material to make with described pixel electrode 19.The embodiment of this array base palte has pixel electrode and the public electrode of narrow slit structure equally by formation, it is 0 overlapping making public electrode and pixel electrode, thereby has avoided the memory capacitance between public electrode and pixel electrode, guarantees picture quality.
The preparation process of above-mentioned array base palte is as follows:
As shown in Figure 3, at first, provide a substrate 11, form grid 12, grid line (not shown), gate insulation layer 13, semiconductor layer 14, data line (not shown), source electrode 15 on substrate 11, drain 16; Concrete, this step can comprise:
Step 31 forms the grid metal level on substrate, adopts composition technique to form the figure of grid line and grid;
Step 32 forms gate insulation layer on the substrate that is formed with grid line and gate patterns;
Step 33, be formed with formation semiconductor layer film on gate insulation layer, forms the figure of semiconductor layer by composition technique;
Step 34, be formed with formation source leakage metal level film on semiconductor layer; Form the figure of source electrode, drain electrode and data line by linking up technique;
In addition, the formation for semiconductor layer and source/drain electrode can also specifically realize by following steps:
Step 34 ', be formed with on the substrate of gate insulation layer, form successively semiconductor layer film and source/leakage metal level film, utilize composition technique to leak the metal level film to described source and the semiconductor layer film is processed, obtain semiconductor active layer 14, data line (not shown), source electrode 15,16 figure drains;
Wherein, step 34 ' concrete implementation procedure can comprise:
Step 341, be coated with photoresist being formed with on described source/leakage metal level film;
Step 342, utilize intermediate tone mask plate or gray tone mask plate to be exposed to described photoresist, forms the complete reserve area of photoresist, photoresist part reserve area and photoresist after developing and remove zone fully; Wherein, the corresponding source region of the complete reserve area of described photoresist, drain region and data line zone, the gap area between the corresponding source electrode of described photoresist half reserve area and drain electrode, other regional corresponding photoresists are removed zone fully;
Step 343, utilize etching technics to get rid of described photoresist and remove regional source leakage metal level film, semiconductor layer film fully, exposes this regional gate insulation layer;
Step 344, utilize plasma ashing technique to get rid of the photoresist of described photoresist half reserve area, exposes this regional source and leak the metal level film;
Step 345, utilize etching technics to leak the metal level film to the source exposed and carry out etching, exposes semiconductor layer, in this zone, forms the slit areas figure between thin film transistor (TFT) source electrode and drain electrode;
Step 346, utilize plasma ashing technique or photoresist stripping process to get rid of the photoresist of the complete reserve area of described photoresist, forms the figure that comprises the slit between data line, source electrode, drain electrode and source electrode and drain electrode.
Above-mentioned steps is only a specific implementation example of such scheme of the present utility model, but in embodiment of the present utility model, be not limited to above-mentioned performing step, those skilled in the art can know, under different mode, for example under top grid pattern or bottom gate pattern, the forming process of above-mentioned figure can have difference a little, as the adjustment by sequence of steps; The perhaps order adjustment of the step of above-mentioned masking process, can realize the transistorized structure of above-mentioned array base palte upper film.Fig. 3 is only the schematic diagram of bottom grating structure, specifically comprises: grid 12, grid line (not shown), gate insulation layer 13, semiconductor layer 14, data line, source electrode 15, drain 16.
As shown in Figure 4, being formed with grid level 12, grid line (not shown), gate insulation layer 13, semiconductor layer 14, data line, source electrode 15, continue to form passivation layer 17 on 16 the substrate of draining.
As shown in Figure 5, continue to form the protective seam figure 18 of narrow slit structure on the substrate 11 that is formed with passivation layer 17; Wherein, the specific implementation process of the protective seam figure of this narrow slit structure can comprise:
Step 51 forms protective seam on described passivation layer;
Wherein, described protective seam can be resin material, and this resin material is the inorganic insulation resin material;
The film forming density of described inorganic insulation resin material gets final product than the density of passivation layer 17 is high; in follow-up composition technique, can make like this etch rate of protective seam lower than the etch rate of passivation layer, thereby can guarantee that the etching chamfering appears in passivation layer and protective seam on cross section.
Further, described protective seam can select the organic photo resin material to form.Can save so the follow-up etching procedure to protective seam.
Step 52, carry out composition to described protective seam and described passivation layer, obtains as shown in Figure 5, has the protective seam of narrow slit structure and the figure of passivation layer.
Wherein, the zone of the slit respective pixel electrode in described narrow slit structure, the zone of the corresponding public electrode of the protective seam in described narrow slit structure.
Wherein, the specific implementation process of above-mentioned steps 52 can comprise following two kinds of methods:
Method one forms photoresist on described protective seam; Utilize common composition technique; successively to forming slot pattern as shown in Figure 6 after protective seam 18 and passivation layer 17 etchings; can realize very smoothly tomography in order to make later pixel electrode and public electrode; generally can select the etching liquid different with the protective seam etch rate to passivation layer; faster than protective seam with the etch rate of guaranteeing passivation layer; the final like this contact portion of passivation layer and protective seam that can make realizes the etching chamfering; in the zone of passivation layer and protective seam lamination, the slit width of protective seam is wider than passivation layer.
Method two, when the material of described protective seam can be used the organic photo resin material, at first, by exposure, developing process can form the narrow slit structure of protective seam, utilize the pattern of protective seam directly the passivation layer exposed to be carried out to etching, pass through etching technics, control etching time or etch rate and obtain the protective seam with narrow slit structure as shown in Figure 6 and the figure of passivation layer, and in the rhythmo structure of passivation layer and protective seam, the xsect of passivation layer is narrower than protective seam, while being beneficial to later pixel electrode and public electrode formation, can produce good offset to guarantee the tomography of public electrode and pixel electrode.
Above-mentioned steps is only a specific implementation example of such scheme of the present utility model, but in embodiment of the present utility model, be not limited to above-mentioned performing step, those skilled in the art can know, under different mode, the forming process of above-mentioned figure can have difference a little, as the order adjustment of step; The perhaps merging of the step of above-mentioned etching technics, can realize having the protective seam of narrow slit structure and the figure of passivation layer.
Further, for example, when thin film transistor (TFT) adopts top gate structure, can on array base palte, form successively the figure of semiconductor layer, source/drain electrode and data line; And then form successively the figure of gate insulation layer and grid, grid line on the substrate that forms active/drain electrode and data line; Form protective seam on the figure that is formed with grid and grid line; utilize composition technique to be processed protective seam and gate insulation layer; the protective seam of formation narrow slit structure and gate insulation layer are (in this top gate structure; passivation layer is formed by gate insulation layer); the zone of the slit respective pixel electrode in described narrow slit structure, the figure of the corresponding public electrode of the protective seam figure in described narrow slit structure.
As shown in Figure 7, form transparent conductive film on the substrate that is formed with protective seam and passivation layer figure; Described transparent conductive film is used to form public electrode and pixel electrode; This transparent conductive film, through one-pass film-forming technique, just can obtain the pixel electrode 19 that is arranged in the public electrode 20 on protective seam and is positioned at the slit areas of narrow slit structure; And because the bottom of protective seam figure covers the top of passivation layer, and passivation layer and protective seam form the etching chamfering, the width that is protective seam is wider than the width of passivation layer, therefore, when forming transparent conductive film, the public electrode 20 be arranged on protective seam can not produce overlapping with the pixel electrode 19 that is positioned at the slit areas of narrow slit structure, and be to be interspersed at horizontal level, therefore, the zero overlapping memory capacitance that can make between public electrode and pixel electrode minimizes, thereby guarantees picture quality;
And with respect to the manufacture craft of traditional array base palte, carry out respectively the making of pixel electrode and public electrode, in embodiment of the present utility model, reduced manufacture craft, shortened manufacturing process, improve the make efficiency of array base palte.
As shown in Figure 8, after forming transparent conductive film, can also comprise:
By composition technique, the transparent conductive film of described thin film transistor (TFT) (semiconductor layer, source electrode, drain electrode) top is removed, final public electrode and the figure of pixel electrode have been obtained, the transparent conductive film of semiconductor top belongs to the part of public electrode like this, be present in the thin film transistor (TFT) top, can produce signal to thin film transistor (TFT) and disturb the load that increases thin film transistor (TFT), and can produce some unwanted stray capacitances, such as increasing Cdc etc., after removal, can be down to minimum by the harmful effect to thin film transistor (TFT).
To sum up, above-described embodiment of the present utility model can be applied to the tft array substrate of ADS pattern, make the metal level of public electrode and pixel electrode by one-pass film-forming technique simultaneously, and formation has pixel electrode and the public electrode of narrow slit structure, it is 0 overlapping making public electrode and pixel electrode, thereby avoided the memory capacitance between public electrode and pixel electrode, guaranteed picture quality;
And with respect to the manufacture craft of traditional array base palte, carry out respectively the making of pixel electrode and public electrode, in embodiment of the present utility model, reduced manufacture craft, shortened manufacturing process, improve the make efficiency of array base palte.
Embodiment of the present utility model also provides a kind of display device, comprises array base palte as above.Wherein, this display device has been used any one array base palte as described as above-mentioned embodiment.Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The above is preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from principle described in the utility model; can also make some improvements and modifications, these improvements and modifications also should be considered as protection domain of the present utility model.
Claims (9)
1. an array base palte, is characterized in that, comprising:
Substrate; And
Be formed at the public electrode of the narrow slit structure on described substrate, and with the pixel electrode of the overlapping narrow slit structure of described public electrode zero.
2. array base palte according to claim 1, is characterized in that, described array base palte comprises the thin film transistor (TFT) of bottom grating structure or the thin film transistor (TFT) of top gate structure.
3. array base palte according to claim 2, it is characterized in that, the thin film transistor (TFT) of described bottom grating structure comprises: be formed at grid, grid line, gate insulation layer on described substrate, and be formed at semiconductor layer, data line, source/drain electrode on described gate insulation layer;
Also be formed with the protective seam that is positioned at the narrow slit structure on described semiconductor layer, source/drain electrode and the figure of passivation layer on described substrate, and described protective seam and passivation layer are rhythmo structure.
4. array base palte according to claim 3, is characterized in that, in the rhythmo structure of protective seam and passivation layer, protective seam is wider than the width of passivation layer.
5. array base palte according to claim 2, it is characterized in that, the thin film transistor (TFT) of described top gate structure comprises: be formed at semiconductor layer, data line, source/drain electrode on described substrate, and be formed at grid, grid line and the gate insulation layer on source/drain electrode and data line;
Also be formed with the protective seam that is positioned at the narrow slit structure on described grid, grid line and the figure of gate insulation layer on described substrate, and described protective seam and gate insulation layer are rhythmo structure.
6. array base palte according to claim 5, is characterized in that, in the rhythmo structure of protective seam and gate insulation layer, protective seam is wider than the width of gate insulation layer.
7. according to the described array base palte of claim 3 or 5, it is characterized in that, the public electrode of described narrow slit structure is positioned on described protective seam figure; The pixel electrode of described narrow slit structure is formed at the slit areas in described narrow slit structure.
8. according to the described array base palte of claim 3 or 5, it is characterized in that, described protective seam adopts inorganic insulation resin material or organic photo resin material to make.
9. a display device, is characterized in that, comprises as the described array base palte of claim 1-8 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320490837 CN203365867U (en) | 2013-08-12 | 2013-08-12 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320490837 CN203365867U (en) | 2013-08-12 | 2013-08-12 | Array substrate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203365867U true CN203365867U (en) | 2013-12-25 |
Family
ID=49813611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320490837 Expired - Lifetime CN203365867U (en) | 2013-08-12 | 2013-08-12 | Array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203365867U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413784A (en) * | 2013-08-12 | 2013-11-27 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
-
2013
- 2013-08-12 CN CN 201320490837 patent/CN203365867U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103413784A (en) * | 2013-08-12 | 2013-11-27 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
| CN103413784B (en) * | 2013-08-12 | 2015-07-01 | 京东方科技集团股份有限公司 | Array substrate, preparing method thereof and display device |
| US9690146B2 (en) | 2013-08-12 | 2017-06-27 | Boe Technology Group Co., Ltd. | Array substrate, its manufacturing method, and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102148259B (en) | Thin film transistor, array substrate and manufacturing methods thereof and liquid crystal display | |
| CN103151359B (en) | A kind of display unit, array base palte and preparation method thereof | |
| CN103226272B (en) | Array substrate and preparation method thereof, and display device | |
| CN102881688B (en) | Array substrate, display panel and array substrate manufacturing method | |
| CN102903675B (en) | TFT (Thin Film Transistor) array substrate, manufacturing method and display device | |
| CN104360557A (en) | Array substrate, manufacturing method thereof and display device | |
| CN104037126A (en) | Array substrate preparation method, array substrate and display device | |
| CN103474396B (en) | The manufacture method of TFT-LCD array substrate | |
| CN103413784B (en) | Array substrate, preparing method thereof and display device | |
| CN103439840A (en) | Array substrate, display device and method for manufacturing array substrate | |
| CN102629608B (en) | Array substrate, a manufacturing method thereof and display device | |
| CN103838044B (en) | Substrate and its manufacture method, display device | |
| US20120113377A1 (en) | Array substrate and manufacturing method thereof, and liquid crystal display | |
| CN103021944A (en) | TFT (thin-film transistor) array substrate, manufacturing method of TFT array substrate, and display device with TFT array substrate | |
| CN103107133A (en) | Array substrate, manufacturing method thereof and displaying device | |
| US10403761B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| CN106353944A (en) | Array base plate, manufacturing method of array base plate, display panel and display device | |
| CN102779783A (en) | Pixel structure, as well as manufacturing method and display device thereof | |
| CN106024705B (en) | The production method of TFT substrate | |
| US9147697B2 (en) | Manufacturing method of array substrate, array substrate, and display apparatus | |
| KR20150137218A (en) | Liquid crystal display device and method for manufacturing the same | |
| CN104020621A (en) | Array substrate and preparation method thereof and display device | |
| CN203277383U (en) | Array substrate and display device | |
| CN203365867U (en) | Array substrate and display device | |
| CN102854681A (en) | Array substrate, display device, and manufacture method of array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131225 |