CN203301444U - Novel power-on reset circuit for Xilinx FPGA - Google Patents

Abstract

Disclosed is a novel power-on reset circuit for a Xilinx FPGA. The power-on reset circuit includes a PROM chip, an FPGA chip, a resistor R1, a resistor R2, a capacitor C1 and a capacitor C2. In order to make a software have a fixed working start point after FPGA power-on configuration is completed, global reset signals are needed to be introduced from outside. After the circuit is powered on, the FPGA chip reads configuration information from the PROM and then initializing setting is carried out. When a DONE signal end of the FPGA chip is changed into a high level, an FPGA configuration process is over. Through an RC delay reset circuit, high-level signals at the DONE signal end generate global reset signals, which are then transmitted to an MRST end of the FPGA, and then the FPGA chip begins to work. The novel power-on reset circuit for the Xilinx FPGA enables the DONE signals to be input as the global reset signals of the software through the RC delay in a hardware circuit design.

Description

A kind of New X ilinx FPGA electrify restoration circuit

Technical field

The utility model relates to the novel electrify restoration circuit on a kind of Xilinx of being applied to FPGA.

Background technology

The fpga chip of Xilinx company is based on the volatility device of SRAM type technique, and circuit function relies on the bits position be stored in SRAM type configuration register to realize.Could work must read configuration information after fpga chip powers on from PROM after.

Layoutprocedure comprises 5 stages: initialization, empty config memory, and load configuration data, CRC check, START-UP.After FPGA powers on, just as the FPGA device power source, meet the demands and can automatically carry out initialization.After initialization procedure was completed, device can be set to low level with INIT, DONE signal, starts simultaneously to empty config memory.After having emptied config memory, the INIT signal will be set to high level again.After the INIT signal set high again, device was sampled to configuration mode pin M0, M1, M2, to determine which kind of mode loading configuration data with.Device when loading configuration data, can produce a crc value according to certain algorithm, and this value will compare with built-in crc value in configuration file.After CRC check is correct, just enter the START-UP stage.The START-UP stage is that FPGA is transitioned into the process of User Status by configuration status, comprise overall ternary signal GTS is set low in the START-UP operation that in the stage, FPGA carries out, global reset signal GSR sets low level, and overall written allowance signal GWE sets low, and the DONE signal sets high.The DONE signal namely when the DONE signal is set high, shows that this moment, the FPGA layoutprocedure finished, enters User Status, therefore can be used as the Global reset input after the RC delay circuit.The configuration principle as shown in Figure 1.

Conventionally reset circuit comprises following several mode.

● use the lock flag pin of digital dock administration module (DCM)

, for adopting the system of DCM in the FPGA program, can adopt the Global reset of the locking settling signal (LOCKED) of DCM as program.Adopting the LOCKED signal is that clock signal can first arrive each trigger than reset signal as the shortcoming of Global reset,, if effective reset signal is not identical in the finish time of each trigger, can cause trigger to start in the different clock cycle.

● use the overall situation to start and put/reseting pin (GSR)

It is not identical that the problem that adopts the GSR pin to exist as the Global reset input of software is that reseting signal line arrives the time delay of each trigger, and it is also very possible differing tens of nanoseconds on larger slice, thin piece.The another one problem of GSR pin is that reset signal can only be at most and a user-defined clock synchronous, when each flip-flop operation, resets and will lose efficacy during in different clock.In addition, the also existence problem that can allow trigger in the same clock cycle, not start working of this repositioning method.

● adopt RC circuit serial connection delay chip mode

Be characterized in that circuit adopts absolute construction, shortcoming is that the value of RC exists certain error, thereby causes the time of electrification reset also to have error, and is accurate not.Its circuit diagram as shown in Figure 2.

The utility model content

The technical problem that the utility model solves is: overcome the deficiencies in the prior art, the electrify restoration circuit of a kind of new application in Xilinx FPGA is provided, utilize FPGA self DONE signal,, by the RC time delay, generate the global reset signal of software.

The technical solution of the utility model is: a kind of New X ilinx FPGA electrify restoration circuit comprises PROM, fpga chip, RC time-delay reset circuit; The CE end of PROM, D0 end, CF end are connected respectively DONE signal end, D0 end, the PROG_B end to fpga chip; The RC time-delay reset circuit comprises resistance R 1, resistance R 2, capacitor C 1, capacitor C 2; An end as pull-up resistor R1 is connected to power supply, and the other end of resistance R 1 is series resistance R2, capacitor C 1, the rear ground connection of capacitor C 2 successively; The node voltage of the common port of resistance R 2 and capacitor C 1 is connected to the MRST pin of fpga chip as power-on reset signal; After circuit powered on, fpga chip read configuration information from PROM, and carried out the initialization setting; When becoming high level, the FPGA layoutprocedure finishes when DONE signal end in fpga chip, and the high level signal of DONE signal end produces global reset signal by the RC time-delay reset circuit and delivers to the MRST end of FPGA, and fpga chip is started working.

In described RC time-delay reset circuit, the value of resistance R 1, resistance R 2, capacitor C 1, capacitor C 2 meets

t _r=-RCln(0.1)

In formula, t _rFor the electrification reset delay time; R=R1+R2; C=C1+C2.

The utility model advantage compared with prior art is: the utility model hardware circuit design, by the Global reset input of RC time delay as software, makes software have fixing work starting point the DONE signal.Concrete advantage is: (1) need not additionally to add hardware delay chip generating reset signal, only needs to use the RC delay circuit to realize; (2) FPGA is identified the input of the DONE of configuration status as reset signal generating circuit, guaranteed the sequential relationship of reset signal and FPGA configuration completion status; (3) global reset signal of access FPGA can be carried out delay process by software, makes the software reset more stable.Whole reset circuit is saved hardware cost, and the opportunity confirm that resets, guaranteed FPGA software security reliable reset.

Description of drawings

Fig. 1 is the Virtex-II of Xilinx company Series FPGA configuration schematic diagram;

Fig. 2 is conventional FPGA electrify restoration circuit schematic diagram;

Fig. 3 is the utility model FPGA electrify restoration circuit schematic diagram;

Fig. 4 is DONE and MRST test waveform.

Embodiment

Figure 3 shows that the utility model FPGA electrify restoration circuit schematic diagram, wherein PROM uses the XCF16P of Xilinx company, and FPGA uses the Virtex-II of Xilinx company series of X C2V3000.In system, circuit design is inputted by the RC time delay DONE signal as the Global reset of software, the MRST signal in the figure that namely makes a summary.Hardware designs is mainly considered the requirement of electrification reset time delay greater than 10ms, resistance R 2 resistances in the RC time-delay reset circuit can be selected 4.7K Europe, in order to improve the withstand voltage properties of electric capacity, select the tantalum capacitances in series of two 22uF, namely capacitor C 1 and capacitor C 2 are 22uF.MRST signal elevating time (0～90% high level time) can calculate by RC time delay formula like this,, suc as formula (2), is about 100ms, meets the designing requirement of reset delay time

t _r=-RCln(0.1)

=(330+4700)Ω*11μF*ln(0.1)-----（1）

≈100ms

In formula: t _r----electrification reset delay time;

R----R1 and R2 series impedance;

C----C1 and C2 series capacitance value.

According to above parameter setting, the waveform that can obtain DONE signal and MRST signal by hardware testing as shown in Figure 4.After in Fig. 4, the DONE signal becomes high level 3.3V, the RC time-delay reset circuit starts capacitor C 1 and capacitor C 2 chargings, node voltage rising between resistance R 2 and capacitor C 1, this node is as reset signal MRST, the reset signal MRST rise time is about 100ms, meets system to the requirement of Global reset time delay greater than 10ms.

The content that is not described in detail in the utility model specification belongs to those skilled in the art's known technology.

Claims (1)

1. a New X ilinx FPGA electrify restoration circuit, is characterized in that: comprise PROM, fpga chip, RC time-delay reset circuit; The CE end of PROM, D0 end, CF end are connected respectively DONE signal end, D0 end, the PROG_B end to fpga chip; The RC time-delay reset circuit comprises resistance R 1, resistance R 2, capacitor C 1, capacitor C 2; An end as pull-up resistor R1 is connected to power supply, and the other end of resistance R 1 is series resistance R2, capacitor C 1, the rear ground connection of capacitor C 2 successively; The node voltage of the common port of resistance R 2 and capacitor C 1 is connected to the MRST pin of fpga chip as power-on reset signal; After circuit powered on, fpga chip read configuration information from PROM, and carried out the initialization setting; When becoming high level, the FPGA layoutprocedure finishes when DONE signal end in fpga chip, and the high level signal of DONE signal end produces global reset signal by the RC time-delay reset circuit and delivers to the MRST end of FPGA, and fpga chip is started working.

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