CN203299591U

CN203299591U - Multichannel synchronous data collection card based on PC104 bus

Info

Publication number: CN203299591U
Application number: CN2013203641910U
Authority: CN
Inventors: 叶明�
Original assignee: CHENGDU XUANJILI COMMUNICATION TECHNOLOGY Co Ltd
Current assignee: CHENGDU XUANJILI COMMUNICATION TECHNOLOGY Co Ltd
Priority date: 2013-06-24
Filing date: 2013-06-24
Publication date: 2013-11-20
Anticipated expiration: 2023-06-24

Abstract

The utility model discloses a multichannel synchronous data collection card based on a PC104 bus. The multichannel synchronous data collection card based on the PC104 bus comprises a conditioning circuit, an ADC, a clock circuit, an FPGA, an SRAM, a display and a PC104 bus controller, wherein the conditioning circuit inputs a simulation signal, an output end of the conditioning circuit and the FPGA are internally provided with a data parsing module, a format conversion module and a data synchronous module which are connected in series sequentially, an output end of the ADC is connected with an input end of the data parsing module, a storage end of the data synchronous module is connected with the SRAM, a communication end of the data synchronous module is connected with the PC104 bus controller, and the PC104 bus controller is further connected with the display through the PC104 bus. According to the multichannel synchronous data collection card based on the PC104 bus, the simulation signal is converted into a digital signal through the ADC by utilizing the FPGA, and the processed signal is then transmitted to the display by utilizing the PC104 bus controller, the PC104 bus controller is in a high resistance state when data transmission between the PC104 bus controller and the FPGA is not carried out, so data interference between the FPGA and the display is prevented, and data acquisition precision is improved.

Description

Multi-channel synchronous data acquisition card based on the PC104 bus

Technical field

The utility model relates to a kind of multi-channel synchronous data acquisition card, relates in particular to a kind of multi-channel synchronous data acquisition card based on the PC104 bus for the aeronautical data collection.

Background technology

The PC104 bus, as a kind of control bus of international standard, is widely applied in test with in controlling, but also there is no supporting with it multi-channel synchronous data acquisition card in the market.The aeronautical data capture card is for the collection of various aeronautical datas, as operational factor collection of aircraft engine etc., this class data acquisition card request has high-precision data acquisition ability and express-analysis and transmittability, so generally adopted FPGA as the programming device.But traditional multi-channel synchronous data acquisition card is low resistive state when FPGA does not transmit data to display (or main frame), so the data that can form between FPGA and display are disturbed, reduce the precision of data acquisition.

The utility model content

The purpose of this utility model provides a kind of noiseless, high-precision multi-channel synchronous data acquisition card based on the PC104 bus with regard to being in order to address the above problem.

The utility model is achieved through the following technical solutions above-mentioned purpose:

multi-channel synchronous data acquisition card based on the PC104 bus described in the utility model comprises modulate circuit, ADC, clock circuit, FPGA, SRAM, display and PC104 bus controller, described modulate circuit input simulating signal, in described FPGA, be provided with the data resolution module that is connected in series successively, format converting module and data simultaneous module, the output terminal of described ADC is connected with the input end of described data resolution module, the storage end of described data simultaneous module is connected with described SRAM, the communication terminal of described data simultaneous module is connected with described PC104 bus controller, described PC104 bus controller also is connected by the PC104 bus with described display.

ADC, the abbreviation of Analog-to-Digital Converter, finger print/number converter or analog/digital converter.Refer to by the analog signal conversion of continuous variable to be the device of discrete digital signal.The simulating signal of real world, such as temperature, pressure, sound or image etc., need to convert more easily the digital form that stores, processes and launch to.

FPGA(Field-Programmable Gate Array), i.e. field programmable gate array, it is the product that further develops on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.

SRAM is the abbreviation of English Static RAM, i.e. static RAM.It is a kind of internal memory with static access facility, does not need refresh circuit can preserve the data of its storage inside.

PC104 is a kind of industrial computer bus standard.The PC104 bus is a kind of industrial-controlled general line that defines for embedded Control specially.The PC104 bus controller is the communication controller of setting for the transmission of PC104 bus data.The PC104 bus controller can separate with the PC104 bus, also can integrate and be called PC104 bus controller or PC104 bus.

The beneficial effects of the utility model are:

The utility model utilizes FPGA that simulating signal is converted to digital signal through ADC, and recycling PC104 bus controller is transferred to display; The PC104 bus controller is high-impedance state when with FPGA, not carrying out data transmission, can prevent that the data between FPGA and display from disturbing, and improves accuracy of data acquisition; In addition, FPGA comprises data resolution module, format converting module and data simultaneous module three parts, has advantages of that the loss of data of preventing, data rate are fast, are particularly useful for the aeronautical data collection.

The accompanying drawing explanation

Fig. 1 is the circuit block diagram of the multi-channel synchronous data acquisition card based on the PC104 bus described in the utility model.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing:

as shown in Figure 1, multi-channel synchronous data acquisition card based on the PC104 bus described in the utility model comprises modulate circuit, ADC, clock circuit, FPGA, SRAM, display and PC104 bus controller, modulate circuit input simulating signal, the output terminal of modulate circuit is connected with the input end of ADC, the input end of clock of ADC is connected with the output terminal of clock circuit, in FPGA, be provided with the data resolution module that is connected in series successively, format converting module and data simultaneous module, the output terminal of ADC is connected with the input end of data resolution module, the storage end of data simultaneous module is connected with SRAM, the communication terminal of data simultaneous module is connected with the PC104 bus controller, the PC104 bus controller also is connected by the PC104 bus with display.

The model that in high-accuracy data acquisition device described in the utility model, critical piece adopts is as follows:

ADC: the AD7864 that adopts AD company to release, have the characteristics of high speed, low-power consumption, be the A/D converter of four-way synchronized sampling 12 bit parallel interfaces, it can be for motor control, non-interruption power supply control, data acquisition and communication etc.

FPGA: comprise data resolution module, format converting module and data simultaneous module three parts, all be located in FPGA.FPGA adopts the Cyclone III of ALTERA company series EP3C16, and low in energy consumption, logical resource and IO are abundant, and integrated PLL is for generation of the reference clock of serial decoder.Being described as follows of each module:

Data resolution module mainly is responsible for from parallel data stream, parsing data start flag, and this sign has identified the initial of radar system one frame data, in data head, has also comprised each extension set status information of radar system and antenna corner brace information.

Format converting module is responsible for the floating-point format (16 floating-points) that radar return data (32 fixed points) system that is converted to is required, and conversion loss is 0.02dB.

In floating data data writing buffer after data simultaneous module will be changed, because buffer consists of external SRAM, FPGA is by calling SRAM, and it is encapsulated as to fifo structure, notice PC104 bus controller reading out data when FIFO is in half-full state, while as FIFO, being in the near-space state, thereby notice PC104 bus controller suspends reading out data to guarantee that FIFO is not read sky and causes error in data.To write rhythm data fast due to FIFO read data rhythm ratio, thereby guaranteeing that FIFO not there will be writes full state, avoids loss of data.

The PC104 bus controller: adopting the crowd is emerging PC104 bus controller card, and its integrated level is high, and reliability is strong.

Claims

1. multi-channel synchronous data acquisition card based on the PC104 bus, comprise modulate circuit, ADC, clock circuit, FPGA, SRAM and display, described modulate circuit input simulating signal, it is characterized in that: also comprise the PC104 bus controller, in described FPGA, be provided with the data resolution module that is connected in series successively, format converting module and data simultaneous module, the output terminal of described ADC is connected with the input end of described data resolution module, the storage end of described data simultaneous module is connected with described SRAM, the communication terminal of described data simultaneous module is connected with described PC104 bus controller, described PC104 bus controller also is connected by the PC104 bus with described display.