CN203241990U - Storage device - Google Patents
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- CN203241990U CN203241990U CN 201320005176 CN201320005176U CN203241990U CN 203241990 U CN203241990 U CN 203241990U CN 201320005176 CN201320005176 CN 201320005176 CN 201320005176 U CN201320005176 U CN 201320005176U CN 203241990 U CN203241990 U CN 203241990U
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Abstract
Provided is a storage device. The storage device comprises a plurality of storage units, a storage unit interface circuit, an address mapping circuit and a processor. The processor is used for sending the logic address of the storage device to the address mapping circuit. The address mapping circuit maps the logic address to a physical address for the storage units, and sends the physical address to the storage unit interface circuit. The storage unit interface circuit accesses the storage units based on the physical address.
Description
Technical field
The utility model relates to solid storage device (Solid Storage Device, SSD), and more specifically, the utility model relates to for the logical address of memory device and the mapping between the physics.
Background technology
Similar with the mechanical type hard disk, solid storage device (SSD) also is large capacity, the non-volatile memory device for computer system.Solid storage device generally with flash memory (Flash) as storage medium.High performance solid storage device is used to high-performance computer.
Memory target is one or more logical blocks (Logic Unit) of shared chip enable (CE, the Chip Enable) signal in the nand flash memory encapsulation.Each logical block has logical unit number (LUN, Logic Unit Number).Can comprise one or more tube cores (Die) in the nand flash memory encapsulation.Typically, logical block is corresponding to single tube core.Logical block can comprise a plurality of planes (Plane).A plurality of planes in the logical block can parallel access, and a plurality of logical blocks in the nand flash memory chip independently of one another fill order and report condition.Can from
Http:// www.micron.com/～/media/Documents/Products/Other%20Documents/ONFI3_0Gol d.ashx acquisition " Open NAND Flash Interface Specification(Revision3.0) " in, implication about target (target), logical block, LUN, plane (Plane) is provided, and it is the part of prior art.
Publication number is that the Chinese patent application of CN102177556A discloses a kind of flash translation layer (FTL) (FTL, Flash Translation Layer).FTL forms virtual memory space with the storage block of flash memory, so that flash memories is shown as disc driver to main frame.FTL is by producing and keep table in storer, with the physical location in the flash chip that will be mapped to from the request to a sector of disc driver of main frame solid-state drive.
Referring to Fig. 1, it has showed the example of the look-up table of the Parallel Unit that is used for FTL.Because the logical block (Logic Unit) in the flash chip can the parallel mode access, thereby Parallel Unit can be a logical block.Can comprise a plurality of planes (Plane) in the logical block, Parallel Unit also can be a plane.And in the example corresponding to Fig. 1, solid-state drive comprises 8 channels (channel) (being also referred to as " passage ").Comprise a plurality of flash chips on each passage, can be by the access of 2 chip enable signal controls to the flash chip on each passage.In the example of Fig. 1, each chip is enabled (being called again " chip enable ") signal corresponding to a logical block, and each logical block has 2 planes.Thereby the solid-state drive of Fig. 1 comprises 32 Parallel Unit altogether.Each Parallel Unit is a plane.By the look-up table that provides among Fig. 1, the Parallel Unit numbering with 0-31 is mapped to specific passage, chip enable signal, logical block and plane.
Yet, may comprise the flash chip with different capabilities in the memory device, the passage of varying number.And may comprise the circuit subcard with different configurations in the memory device, have the passage of varying number, the flash chip of varying number on each subcard.This causes on physical configuration, and arranging of Parallel Unit is also non-linear with respect to circuit subcard or flash chip.Main frame needs then to think that storage space is continuous.Thereby, need in the variable situation of the physical configuration of memory device, be provided for the logical address of memory device and the mapping between the physical address.
Summary of the invention
According to first aspect of the present utility model, the address mapping method that is used for memory device is provided, comprising: receive the logical address that is used for memory device; Described logical address is mapped as physical address for storage unit; Access described storage unit based on described physical address.
According to the method for first aspect of the present utility model, wherein use look-up table that described logical address is mapped as physical address for storage unit.
Method according to first aspect of the present utility model comprises: obtain the first quantity of the storage unit on the first circuit board, obtain the second quantity of the storage unit on the second circuit board; Obtain ranges of logical addresses based on described the first quantity and described the second quantity, the value of described logical address is within described ranges of logical addresses; Provide described ranges of logical addresses to main frame.
Method according to first aspect of the present utility model, comprise: based on described the first quantity and described the second quantity, set up look-up table, for the physical address that each logical address in the described ranges of logical addresses is mapped to for the storage unit on first circuit board or the second circuit board.
Method according to first aspect of the present utility model comprises: the first quantity of obtaining the storage unit on the first circuit board; Obtain ranges of logical addresses based on described the first quantity, the value of described logical address is within described ranges of logical addresses; Provide described ranges of logical addresses to main frame.
Method according to first aspect of the present utility model comprises: based on described the first quantity, set up look-up table, for the physical address that each logical address in the described ranges of logical addresses is mapped to for the storage unit on the first circuit board.
Method according to first aspect of the present utility model comprises: again obtain the 3rd quantity of the storage unit on the described first circuit board, again obtain the 4th quantity of the storage unit on the second circuit board; Obtain the second ranges of logical addresses based on described the 3rd quantity and described the 4th quantity, the value of described logical address is within the second described ranges of logical addresses; Provide described the second ranges of logical addresses to main frame; Based on described the 3rd quantity and described the 4th quantity, set up look-up table, for the physical address that each logical address in described the second ranges of logical addresses is mapped to for the storage unit on first circuit board or the second circuit board.
Method according to first aspect of the present utility model comprises: the 5th quantity of obtaining the storage unit on the tertiary circuit plate; Obtain the 3rd ranges of logical addresses based on described the first quantity, described the second quantity and described the 5th quantity, the value of described logical address is within the 3rd described ranges of logical addresses; Provide described the 3rd ranges of logical addresses to main frame; Based on described the first quantity, described the second quantity and described the 5th quantity, set up look-up table, for the physical address that each logical address in described the 3rd ranges of logical addresses is mapped to for the storage unit on first circuit board, second circuit board or the tertiary circuit plate.
Method according to first aspect of the present utility model comprises: the 6th quantity of again obtaining the storage unit on the described first circuit board; Obtain the 4th ranges of logical addresses based on described the 6th quantity, the value of described logical address is within the 4th described ranges of logical addresses; Provide described the 4th ranges of logical addresses to main frame; Based on described the 6th quantity, set up look-up table, for the physical address that each logical address in described the 4th ranges of logical addresses is mapped to for the storage unit on the first circuit board.
According to the method for first aspect of the present utility model, described storage unit is tube core, logical block or the plane in the memory chip.
According to the method for first aspect of the present utility model, wherein, comprise a plurality of storage blocks in the described storage unit, when the storage block in the described storage unit was damaged, the mapping relations that described logical address is mapped as for the physical address of storage unit remained unchanged.
According to second aspect of the present utility model, a kind of address mapping method for memory device is provided, comprising: receive the physical address that is used for described storage unit from storage unit; Be logical address with described physical address map; Described logical address is sent to the main frame of the described memory device of access.
According to the method for second aspect of the present utility model, wherein use look-up table that described physical address map is logical address.
Method according to second aspect of the present utility model is stated comprises: obtain the first quantity of the storage element on the first circuit board, obtain the second quantity of the storage unit on the second circuit board; Obtain ranges of logical addresses based on described the first quantity and described the second quantity, the value of described logical address is within described ranges of logical addresses; Provide described ranges of logical addresses to main frame.
Method according to second aspect of the present utility model, comprise: based on described the first quantity and described the second quantity, set up look-up table, be used for to arrive for each physical address map of the storage unit on first circuit board or the second circuit board the logical address in the described ranges of logical addresses.
According to the method for second aspect of the present utility model, described storage unit is logical block, tube core or the plane in the memory chip.
According to the method for second aspect of the present utility model, wherein, comprise a plurality of storage blocks in the described storage unit, when the storage block in the described storage unit is damaged, be that the mapping relations of logical address remain unchanged with described physical address map.
Method according to second aspect of the present utility model comprises: again obtain the 3rd quantity of the storage unit on the described first circuit board, again obtain the 4th quantity of the storage unit on the second circuit board; Obtain the second ranges of logical addresses based on described the 3rd quantity and described the 4th quantity, the value of described logical address is within the second described ranges of logical addresses; Provide described the second ranges of logical addresses to main frame; Based on described the 3rd quantity and described the 4th quantity, set up look-up table, be used for arriving for each physical address map of the storage unit on first circuit board or the second circuit board the logical address in described the second ranges of logical addresses.
Method according to second aspect of the present utility model comprises: the 5th quantity of obtaining the storage unit on the tertiary circuit plate; Obtain the 3rd ranges of logical addresses based on described the first quantity, described the second quantity and described the 5th quantity, the value of described logical address is within the 3rd described ranges of logical addresses; Provide described the 3rd ranges of logical addresses to main frame; Based on described the first quantity, described the second quantity and described the 5th quantity, set up look-up table, be used for to arrive for each physical address map of the storage unit on first circuit board, second circuit board or the tertiary circuit plate the logical address in described the 3rd ranges of logical addresses.
Method according to second aspect of the present utility model comprises: the 6th quantity of again obtaining the storage unit on the described first circuit board; Obtain the 4th ranges of logical addresses based on described the 6th quantity, the value of described logical address is within the 4th described ranges of logical addresses; Provide described the 4th ranges of logical addresses to main frame; Based on described the 6th quantity, set up look-up table, be used for arriving for each physical address map of the storage unit on the first circuit board the logical address in described the 4th ranges of logical addresses.
According to the third aspect of the present utility model, a kind of memory device is provided, comprise a plurality of storage unit, storage unit interface circuit, address mapping circuit and processor, described processor will send to for the logical address of memory device described address mapping circuit; Described address mapping circuit is mapped as physical address for storage unit with described logical address, and described physical address is sent to described storage unit interface circuit; Described storage unit interface circuit is accessed described storage unit based on described physical address.
According to the memory device of the third aspect of the present utility model, wherein said address mapping circuit is lut circuits.
According to the memory device of the third aspect of the present utility model, also comprise testing circuit, host interface, first circuit board and second circuit board; Described a plurality of storage unit is arranged on described first circuit board and the described second circuit board; Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board; Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses.
Memory device according to the third aspect of the present utility model, wherein said processor is based on described the first quantity and described the second quantity, set up look-up table, and with the described address of described look-up table initialization mapping circuit, described look-up table is used for each logical address in the described ranges of logical addresses is mapped to physical address for the storage unit on first circuit board or the second circuit board.
According to the memory device of the third aspect of the present utility model, wherein said the first quantity is different from described the second quantity.
According to the memory device of the third aspect of the present utility model, also comprise testing circuit, host interface, first circuit board; Described a plurality of storage unit is arranged on the described first circuit board; Described testing circuit obtains the first quantity of the storage element on the described first circuit board; Described host interface will send to main frame based on the ranges of logical addresses that described the first quantity obtains, and the value of wherein said logical address is within described ranges of logical addresses.
According to the memory device of the third aspect of the present utility model, wherein said storage unit is logical block, tube core or the plane in the memory chip.
Memory device according to the third aspect of the present utility model, comprise a plurality of storage blocks in the wherein said storage unit, when the storage block in the described storage unit was damaged, the mapping relations that described logical address is mapped as for the physical address of storage unit remained unchanged.
According to the memory device of the third aspect of the present utility model, also comprise the second address mapping circuit, wherein said storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit; Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
According to the memory device of the third aspect of the present utility model, also comprise testing circuit, described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board; Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
Description of drawings
When reading together with accompanying drawing, by the detailed description of reference back to the embodiment of illustrating property, will understand best the utility model and preferably use pattern and its further purpose and advantage, wherein accompanying drawing comprises:
Fig. 1 has showed the look-up table that is used for the Parallel Unit of FTL in the prior art;
Fig. 2 is the front elevation according to the memory device of embodiment of the present utility model;
Fig. 3 A is the front elevation according to the circuit daughter board of the memory device of embodiment of the present utility model;
Fig. 3 B-3E is the side view according to the memory circuit daughter board of embodiment of the present utility model;
Fig. 4 is the process flow diagram according to the mapping of setting up logical address and physical address of embodiment of the present utility model;
Fig. 5 A-5D shows the look-up table that shines upon according to embodiment of the present utility model between LBA and PBA;
Fig. 6 is the process flow diagram according to the address mapping method of embodiment of the present utility model;
Fig. 7 shows the schematic diagram according to the organizational form of the storage unit of the memory device of embodiment of the present utility model;
Fig. 8 A-8B shows the figure of the address mapping relation of implementing embodiment of the present utility model;
Fig. 8 C-8F shows and implement the look-up table that shines upon of the present utility model between logic storage unit group address and physical memory cell group address;
Fig. 9 is the process flow diagram according to the cell group address mapping method of embodiment of the present utility model;
Figure 10 A-10D is the process flow diagram according to the mapping of setting up logical address and physical address of a plurality of embodiment of the present utility model; And
Figure 11 is the theory diagram according to the memory device of embodiment of the present utility model.
Embodiment
Fig. 2 is the front elevation according to the memory device of embodiment of the present utility model.Memory device shown in Figure 2 comprises circuit motherboard 400.Circuit motherboard 400 is the circuit boards with PCIE half high card form, and it can be connected to computing machine by the PCIE slot.Be furnished with circuit daughter board 410,420,430 and 440 on the circuit motherboard 400.In one embodiment, be furnished with respectively flash chip 411-413,421-423,431-433 and 441-443 on the circuit daughter board 410,420,430 and 440, so that circuit daughter board 410,420,430 and 440 provides memory capacity to memory device.Although each that figure 2 illustrates at circuit daughter board 410-440 placed three flash chips, one of ordinary skill in the art will recognize also can place at circuit daughter board 410-440 the flash chip of other quantity, for example, on circuit daughter board 410, place flash chip with the surperficial relative surface at flash chip 411-413 place.One of ordinary skill in the art also will recognize and the circuit daughter board of varying number can be connected to circuit motherboard 400.
Although figure 2 illustrates the memory device with PCIE interface that comprises flash chip, but one of ordinary skill in the art will recognize, it only is a kind of giving an example, the utility model is applicable to the various electronic with other functions, and can be coupled to computing machine by the multiple interfaces mode, multiple interfaces includes but not limited to SATA(Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), USB(Universal Serial Bus, USB (universal serial bus)), PCIE(Peripheral Component Interconnect Express, quick peripheral assembly interconnecting), SCSI(Small Computer System Interface, small computer system interface), IDE(Integrated Drive Electronics, the integrated drive electronics) etc.And the utility model also is applicable to comprise the storage chip of flash memory other types in addition, for example, and phase transition storage, Memister, ferroelectric memory etc.
Also be furnished with control circuit 660 on circuit motherboard 400, in order to the access of control to the flash chip on the circuit daughter board 410,420,430 and 440, and processing is from the interface command of computing machine.Also be furnished with the Memory such as DRAM(Dynamic Random Access on the circuit motherboard 400, dynamic RAM) storer 662,664,666 and 668.Storer 662,664,666 and 668 can be coupled to control circuit 660.Control circuit 660 can be FPGA(Field-programmable gate array, field programmable gate array), ASIC(Application Specific Integrated Circuit, the application specific integrated circuit) or the form of its combination.Control circuit 660 also can comprise processor or controller.Can comprise one, two or more processor core in the control circuit 660, each processor core is used for control or accesses the part or all of of a plurality of circuit subcards.Each processor core also can be used for accessing or the control circuit subcard on a plurality of flash chips partly or entirely.
Also be furnished with connector 628 and 629 on the circuit motherboard 400 as shown in Figure 2.Can also will respectively the circuit daughter board be connected to circuit motherboard 400 by connector 628 and 629.Thereby, on the circuit motherboard 400 with PCIE half high card form as shown in Figure 2, can connect nearly 6 circuit daughter boards.Circuit daughter board 410 is connected to circuit motherboard 400 by flexible PCB 640.Circuit daughter board 420 is connected to circuit motherboard 400 by flexible PCB 642.Circuit daughter board 430 is connected to circuit motherboard 400 by flexible PCB 644.Circuit daughter board 440 is connected to circuit motherboard 400 by flexible PCB 646.In a similar fashion, the circuit daughter board also is connected to circuit motherboard 400 by flexible PCB via connector 628 or 629.
A plurality of circuit daughter boards placement parallel to each other on the circuit motherboard 400.The minor face of the long edge circuit motherboard 400 of a plurality of circuit daughter boards is placed, and the minor face of a plurality of circuit daughter boards is placed along the long limit of circuit motherboard 400.The minor face of a plurality of circuit daughter boards is placed along same straight line substantially.Circuit daughter board 410 is relative with 420 head and the tail, and the spaces that form of shared flexible PCB 640,642, thus formation circuit daughter board group.Circuit daughter board 430 is relative with 440 head and the tail, and the spaces that form of shared flexible PCB 644,646, thus formation circuit daughter board group.Similarly, it is relative with 629 circuit daughter board also head and the tail to be connected to connector 628, and formation circuit daughter board group.Can have the space between a plurality of circuit daughter boards and the circuit motherboard, in this space, can arrange other electronic components.
In a preferred embodiment, also provide heat abstractor, be used for the flash chip on a plurality of circuit daughter boards and/or control circuit 660 and/or storer 662,664,666 and 668 heats that produce are delivered to the memory device outside.
Fig. 3 A is the front elevation of daughter board of implementing the memory device of embodiment of the present utility model.More clearly showed the circuit daughter board 410 among Fig. 2 among Fig. 3 A. Circuit daughter board 420 and 430 can have the physical aspect identical with circuit daughter board 410, but can have the memory capacity identical or different with circuit daughter board 410.In preferred example, the memory capacity of circuit daughter board 420 is two times of circuit daughter board 410.Be furnished with flash chip 411,412 and 413 at circuit daughter board 410.In an example, the unshowned one side at circuit daughter board 410 also is furnished with flash chip.Flash chip 411,412 and 413 can be the flash chip with same capability, also can be the flash chip with different capabilities.Flash chip on the circuit daughter board 410 can be organized as a plurality of passages, comprises the flash chip of two or other quantity on each passage.Each passage is parallel, can be simultaneously to circuit motherboard 400 the transmission of datas or from circuit motherboard 400 receive datas.On circuit daughter board 410, also can arrange a plurality of flash chips with other quantity.
Can hold in flash chip 411,412 and/or 413 the situation, arrange the size of circuit daughter board 410 as far as possible little, in order on circuit motherboard 400, can arrange the circuit daughter board of greater number, thereby improve the capacity of memory device.Owing to can arrange polylith circuit daughter board 410,420 and/or 430 at circuit motherboard, and circuit daughter board 410,420 and 430 can have the capacity that differs from one another, thereby memory device can have the combination of multiple different memory capacity.Referring to table 1, when circuit daughter board 410,420 and 430 can have 192GB(Giga Byte) when two kinds of memory capacity of 394GB, and when arranging maximum 6 circuit daughter boards 410 at circuit motherboard 400,420 or 430 the time, can obtaining having the memory device of multiple different memory sizes.Comprise 4 to the configuration of the memory device of 6 circuit daughter boards although in table 1, illustrated,, also can arrange 1-3 circuit daughter board at circuit motherboard 400, so that how different memory capacity to be provided.
Table 1 memory device, stores capacities chart
Thus, by the circuit daughter board of two kinds of different memory sizes is provided, obtain having the memory device of multiple different capabilities, can satisfy the demand of multiple different occasions.
And because circuit daughter board 410,420 and 430 has identical physical aspect, thereby the installation of circuit daughter board 410,420 and 430 on circuit motherboard 400 is interchangeable, thereby simplified the process of installing, and, when one of a plurality of circuit daughter boards break down, also can easily change.And, by with larger capacity and/or existing circuit daughter board on the circuit daughter board replacement circuit motherboard 400 of high-performance (access speed, reliability etc.) more, can easily realize renewal or upgrading to memory device.
One of ordinary skill in the art will recognize, the circuit daughter board with three kinds or more kinds of different memory sizes also can be provided, thereby the memory device with more kinds of memory capacity can be provided.For example, referring to table 2, (for example on circuit daughter board 410, can arrange the storage chip of varying number, 3-6 storage chip), thereby, have at each storage chip in the situation of 64GB memory capacity, can provide have respectively 192GB, 256GB, the circuit daughter board of 320GB and 384GB memory capacity.And by multiple circuit daughter board with different memory sizes is provided, can obtain having the memory device of more kinds of different memory sizes.Obviously, if each storage chip on the circuit daughter board 410 has different memory capacity, then can provide to have the memory device that further multiple different memory capacity makes up.
Table 2 circuit daughter board memory capacity table
| Chip capacity | Number of chips | The |
| 64GB | ||
| 3 | | |
| 64GB | ||
| 4 | | |
| 64GB | ||
| 5 | | |
| 64GB | ||
| 6 | 384GB |
Fig. 3 B-3E is the side view of circuit daughter board 410 of implementing the memory device of embodiment of the present utility model.In Fig. 3 B, be furnished with storage chip 411,412,413,414,415 and 416 on the circuit daughter board 410.When each storage chip provided 64GB memory capacity, the circuit daughter board among Fig. 3 B can provide the memory capacity of 384GB.In Fig. 3 C, be furnished with storage chip 411,412,413,414 and 415 on the circuit daughter board 410.When each storage chip provided 64GB memory capacity, the circuit daughter board among Fig. 3 C can provide the memory capacity of 320GB.In Fig. 3 D, be furnished with storage chip 411,412,413 and 414 on the circuit daughter board 410.When each storage chip provided 64GB memory capacity, the circuit daughter board among Fig. 3 D can provide the memory capacity of 256GB.In Fig. 3 E, be furnished with storage chip 411,412 and 413 on the circuit daughter board 410.When each storage chip provided 64GB memory capacity, the circuit daughter board among Fig. 3 E can provide the memory capacity of 192GB.
Next referring to Fig. 4, Fig. 4 is the process flow diagram according to the mapping of setting up logical address and physical address of embodiment of the present utility model.Owing to can comprise the circuit daughter board 410,420,430 of varying number on the circuit motherboard 400, and each circuit daughter board 410,420,430 can comprise the flash chip of varying number and/or memory capacity, thereby the memory capacity on the circuit motherboard 400 can be different.After circuit motherboard 400 powers on, after perhaps the configuration of the circuit daughter board on the circuit motherboard changes, set up the mapping management of logical address and physical address.In one embodiment, logical address is take the size of logical block (Logic Unit) as minimum unit, and physical address is also take logical block as minimum unit, so that logical address and physical address have one to one relation.In step 480, the quantity of the logical block on the acquisition cuicuit daughter board.In an example, in the interface of circuit daughter board 410, provide 3 lead-in wires, every lead-in wire is by the configuration on the electric signal indicating circuit daughter board 410 of its transmission.For example, comprise first passage, second channel and third channel on the circuit daughter board 410, wherein be furnished with 1 flash chip or 2 flash chips on each passage.One of ordinary skill in the art also can recognize the mode of the configuration of other indicating circuit daughter boards 410.Perhaps these 3 lead-in wires can be indicated the quantity of the logical block of arranging on each passage, for example are furnished with 8 logical blocks on the first passage, are furnished with 8 logical blocks on the second channel, and are furnished with 16 logical blocks on the third channel.For example, in the interface of circuit daughter board 410, provide 2 lead-in wires, it can transmit " 00 ", " 01 ", " 10 " and " 11 " four kinds of different states, a kind of customized configuration of each condition indication circuit daughter board 410.Comprise circuit daughter board 410 at circuit motherboard 400, and comprise 3 passages on the configuration information indicating circuit daughter board 410 of circuit daughter board 410,3 passages include in the situation of 16 logical blocks, and the quantity that can obtain the logical block of layout on the circuit motherboard 400 is 48.In another example, circuit motherboard 400 comprises circuit daughter board 410 and 420, comprise 24 logical blocks on the circuit daughter board 410, and comprise 48 logical blocks on the circuit daughter board 420, thereby by the number of logic cells summation to each circuit daughter board, the quantity that can obtain the logical block of layout on the circuit motherboard 400 is 72, and can obtain the distribution of these logical blocks on circuit daughter board 410 and 420.
In step 482, the computational logic address realm.According to the quantity of the logical block that has obtained, can determine the upper limit of the storage space take logical block as least unit of circuit motherboard 400, this upper limit is offered the upper limit of the logical address space of main frame as circuit motherboard 400 or memory device.When circuit motherboard 400 comprised 24 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-23; When circuit motherboard 400 comprised 48 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-47.
In step 484, the ranges of logical addresses that calculates is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.In an example, the ranges of logical addresses that calculates is stored specific memory location---for example register---so that main frame can be by the access to this register, and know the memory capacity that memory device has.When memory device comprises 48 logical blocks, inform that to main frame the ranges of logical addresses take logical block as least unit of memory device is 0-47.In an example, the ranges of logical addresses that provides to main frame with other unit as least unit, for example, with storage block, memory page or sector as least unit.The quantity of storage block, memory page or sector can be the multiple of number of logic cells.
In step 486, set up the two-way mapping table between logical address and physical address.In according to embodiment of the present utility model, logical address space and physical address space shine upon one by one.In an example, when logical address space with logical block during as least unit, logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.In another example, when main frame with storage block, memory page or sector during as the least unit accessing storage device, continuous a plurality of storage blocks, memory page or sector is organized as and has with the identical size of logical block in logic, thereby form with the logical address of logical block as least unit, thereby so that logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.
Fig. 5 A-5D show according to the utility model embodiment in the LBA(LBA (Logical Block Addressing), Logic Block Ad dress) with PBA(physical block address, Physical Block Address) between the look-up table that shines upon.In Fig. 5 A-Fig. 5 D, main frame is take storage block as the least unit accessing storage device.And the logical block of flash chip comprises a plurality of storage blocks.Thereby, in according to embodiment of the present utility model, ignore some low levels of LBA, obtain the logical address take logical block as least unit, and also ignore the some low levels among the PBA, as the physical address take logical block as least unit.By the look-up table that Fig. 5 A-5D provides, between logical address and physical address, set up one-to-one relationship.To will be appreciated that also the look-up table of Fig. 5 A-5D can be two-way, both can pass through logical address, obtain corresponding physical address; Also can pass through physical address, obtain corresponding logical address.Although the PBA that arranges according to " passage ", " chip enable ", " logical block " and " all the other positions " has been shown in Fig. 5 A-Fig. 5 D, one of ordinary skill in the art will recognize, it is only for giving an example, the arrangement mode of PBA is not limited to this, for example, PBA also can arrange according to the mode of " chip enable ", " logical block ", " passage " and " all the other positions ".And, included one or more planes (Plane) in all right description logic unit of PBA.
Referring to Fig. 5 A, memory device comprises 4 passages, control with 4 chip enable signal on each passage, and each chip enable signal can be controlled two logical blocks.Thereby memory device provides 32 logical blocks.Take logical block as least unit the time, main frame will know that the logical address space of memory device is 0-31.It is pointed out that storage block, memory page or sector that main frame can inside, access logic unit, but the content that its look-up table that to be not Fig. 5 A-5D provide is concerned about.Get back to Fig. 5 A, for example, the LBA that main frame provides is " 4[X] ", the logical address of " 4 " representative take logical block as least unit wherein, and " [X] " represents storage block, memory page or the sector of logical block inside.By the look-up table of Fig. 5 A, logical address " 4 " or LBA " 4[X] " are mapped to passage 0, chip enable 2, logical block 0.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 5 A provide is concerned about.And, the part of the storage block of storage unit inside, memory page or sector, be used to redundant storage piece, memory page or sector, so that when the storage block of storage unit inside, memory page or sector corruption, need not to change the mapping relations in the look-up table, because " [X] " represents storage block, memory page or the sector of logical block inside, and the content that its look-up table that to be not Fig. 5 A provide is concerned about.
Referring to Fig. 5 B, memory device comprises 4 passages, wherein 2 chip enable signal of passage 0 usefulness are controlled (reason is to have less flash chip), and passage 1-3 all controls with 4 chip enable signal, and two logical blocks of each chip enable signal control.Thereby memory device provides 28 logical blocks.Take logical block as least unit the time, main frame will know that the logical address space of memory device is 0-27.By the look-up table of Fig. 5 B, logical address " 4 " or LBA " 4[X] " are mapped to passage 1, chip enable 0, logical block 0.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 5 B provide is concerned about.
Referring to Fig. 5 C, memory device comprises 4 passages, control with 4 chip enable signal on each passage, and each chip enable signal can be controlled two logical blocks.Thereby memory device provides 32 logical blocks.Take logical block as least unit the time, main frame will know that the logical address space of memory device is 0-31.The look-up table of Fig. 5 C provides the mapping relations different from the look-up table of Fig. 5 A.By the look-up table of Fig. 5 C, logical address " 5 " or LBA " 5[X] " are mapped to passage 1, chip enable 2, logical block 1.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 5 C provide is concerned about.And in Fig. 5 A, just logical address " 5 " or LBA " 5[X] " are mapped to passage 0, chip enable 2, logical block 1.
Referring to Fig. 5 D, memory device comprises 4 passages, wherein 2 chip enable signal of passage 1 usefulness are controlled (reason is to have less flash chip), and passage 0,2 and 3 is all controlled with 4 chip enable signal, and two logical blocks of each chip enable signal control.Thereby memory device provides 28 logical blocks.Take logical block as least unit the time, main frame will know that the logical address space of memory device is 0-27.By the look-up table of Fig. 5 D, logical address " 4 " or LBA " 4[X] " are mapped to passage 0, chip enable 2, logical block 0.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 5 D provide is concerned about.
Although the mapping relations between specific logical address and the physical address are provided in Fig. 5 A-Fig. 5 D, one of ordinary skill in the art will recognize, have multiple other mapping mode between logical address and physical address.Because logical address space and physical address space are one to one, by being each address in the logical address space, distribute uniquely a physical address in the physical address space, one of ordinary skill in the art will obtain the various ways that shines upon one by one between logical address and physical address.
The look-up table of Fig. 5 A-Fig. 5 D can be implemented as lut circuits.In the situation that the configuration of the circuit daughter board on the circuit motherboard 400 does not change, lut circuits need not to change.
Then referring to Fig. 6, Fig. 6 is the process flow diagram according to the address mapping method of embodiment of the present utility model.In step 680, receive order.In an example, order is the order that is used for accessing storage device from main frame, carries or otherwise indicate the logical address that is used for accessing storage device in order.And in another example, order comes from the data that need to read and offers main frame from memory device, carries or indicate the physical address of institute's sense data in order.In another example still, mistake appears in the flash chip that order comes from memory device, carries or indicate the physical address that wrong position occurs in order.The concrete meaning of these orders is not intended to limit protection domain of the present utility model, but there is the order of various ways and/or purposes in explanation, need to shine upon wherein physical address or logical address.
In step 682, the direction of the address mapping that judgement will be carried out is the mapping from the logical address to the physical address, or the mapping from the physical address to the logical address.Can judge based on form and/or the purposes of order, also can judge based on ad hoc structure or coded portion in the order.
If physical address map is arrived logical address, for example, order comes from the data that need to read and offers main frame from memory device, so, proceed to step 684, based on carrying in the order or obtaining logical address by the indicated physical address of order.In an example, can be logical address with physical address map by the look-up table that provides such as Fig. 5 A-Fig. 5 D.In step 686, operate according to the logical address that obtains.For example, come from the data that need from memory device, to read in order and offer in the situation of main frame, logical address is sent to main frame together with the data of reading.In another example, the flash chip that comes from memory device in order occurs in the wrong situation logical address and/or error message being offered main frame.
If logical address is mapped to physical address, for example, order is the order that is used for accessing storage device from main frame, so, proceeds to step 688, based on carrying in the order or obtaining physical address by the indicated logical address of order.Can logical address be mapped as physical address by the look-up table that provides such as Fig. 5 A-Fig. 5 D.In step 690, according to the physical address access flash chip that obtains.For example, according to the order from main frame, with the physical address that obtains data are write flash chip, perhaps with the physical address sense data from flash chip that obtains.
In step 692, whether the number of logic cells on the testing circuit motherboard 400 changes.The variation of number of logic cells for example comes from and inserts circuit daughter board 410 to circuit motherboard 400, removes circuit daughter board 410 etc. from circuit motherboard 400.If the quantity of logical block changes, the step 480 that provides among Fig. 4 then is provided, again obtain number of logic cells, and set up the mapping table between logical address and the physical address.If number of logic cells does not change, then need not to change the mapping table between logical address and the physical address, and proceed to step 680, to wait for the reception to next order.
Fig. 7 shows the schematic diagram according to the organizational form of the storage unit of the memory device of another embodiment of the present utility model.Logical block 460-472 in the memory device is organized as cell group.Logical block be in the flash chip can independent fill order and the storage unit of report condition.For example, logical block can be a tube core in the flash chip.In other configurations, logical block also can comprise a plurality of tube cores.Comprise N logical block in each cell group, wherein L logical block is used for the storage user data, and M logical block is used for redundant data, and N=L+M, N, L and M are natural number.One of ordinary skill in the art will recognize by adjusting the quantity of L and M, different fault-tolerant abilitys can be provided.For example, when L=M=1, in each cell group, 1 logical block is used for the storage user data, and 1 logical block is used for store backup data in addition, when the user data appearance is wrong, can utilize Backup Data to recover to occur wrong user data.In another example, L=7, and M=1, adopt parity checking mode provide protection for user data.Also can adopt other fault-tolerant encoding mode to improve the reliability of memory device.Control circuit 660 control is to cell group and the wherein operation of each logical block, and the EDC error detection and correction of the data of cell group is also implemented by control circuit 660.
In a preferred embodiment, N logical block of formation cell group is positioned at same flash chip.So that when cell group generation irrecoverable error, can less cost remove or replace the flash chip that mistake occurs.In another embodiment, form N logical block of cell group from a plurality of or N circuit daughter board (410-440), so that some logical block faults in cell group or will use up serviceable life the time can realize reparation by changing circuit daughter board (410-440).
By logical block is organized as cell group, and take cell group as the unit storage user data and redundant data, can improve the reliability of memory device.And, but a plurality of logical block concurrent access, thereby, write the readwrite performance that can not affect memory device with sense data as the unit take cell group.One of ordinary skill in the art will recognize, also a plurality of planes or die groupings can be woven to cell group.
Yet in an example, main frame is with continuous linear address space accessing storage device 400, thereby needs to be mapped to from the linear address of main frame each cell group, is about to linear address and is converted to the storage unit group address.Fig. 8 A shows the schematic diagram according to the address mapping relation of embodiment of the present utility model.In the disclosed embodiment, memory device 400 comprises m cell group, and each cell group comprises n data block.Memory device 400 presents and has 0～(nm-1) linear address space of (with the 4KB/8KB/16KB data block as unit) address realm to the main frame that uses this memory device 400.Logical block can comprise a plurality of storage blocks, and each storage block can comprise a plurality of pages or leaves, and typically, one page is 4KB or 8KB or 16KB size.For clear, be indifferent to the Method of Data Organization of logical block inside here.In one embodiment, linear address is LBA(Logic Block Address, LBA (Logical Block Addressing))
Fig. 8 A shows memory device 400 and presents 0～(nm-1) the linear address range that has take data block as unit to main frame.Fig. 8 B then shows corresponding with each linear address of Fig. 8 A, is presented as the address pattern of storage unit group address and cell group bias internal.Among Fig. 8 B, the lateral attitude is corresponding to each cell group, and lengthwise position is corresponding to each cell group bias internal in the cell group.When each cell group comprised n data block, the lengthwise position of Fig. 8 B comprised n different cell group bias internal.For example, for the linear address 0 among Fig. 8 A, be mapped as No. 0 cell group and No. 0 cell group bias internal among Fig. 8 B.And the linear address 1 among Fig. 8 A is mapped as No. 1 cell group and No. 0 cell group bias internal among Fig. 8 B.Linear address m among Fig. 8 A is mapped as No. 0 cell group and No. 1 cell group bias internal among Fig. 8 B.Linear address nm-1 among Fig. 8 A is mapped as m-1 cell group and n-1 cell group bias internal among Fig. 8 B.The mapping relations of Fig. 8 A and Fig. 8 B can be expressed as, and with the number of linear address divided by cell group in the memory device 400, the remainder of gained is as the storage unit group address, and the merchant of gained is as the cell group bias internal.The storage unit group address is corresponding to specific a plurality of logical blocks (or tube core) of the specific flash memory chip of a cell group of formation of the circuit daughter board (410-440) of memory device 400.And the cell group bias internal has been indicated the linear address space in cell group.
Can use divider that the linear address among Fig. 8 A is mapped as storage unit group address and cell group bias internal among Fig. 8 B.Also can use the mode of look-up table to realize mapping.And when using look-up table, can at linear address, in the mapping of storage unit group address and cell group bias internal, adopt other mapping relations.Can start or the configuration of memory device 400 quantity that being used in the quantity by enumerating of the configuration of circuit daughter board (410-440) found cell group and the cell group stored the logical block of user data change the time is determined the size of the logical address space that memory device 400 presents to main frame at memory device 400, and set up the mapping relations that linear address arrives storage unit group address and cell group bias internal.(division obtains linear cell group)
It is pointed out that the cell group shown in Fig. 8 B, can be cell group (hereinafter being referred to as " logic storage unit group ") in logic, and it does not represent the physical location information relevant with flash chip.Thereby, also need the logic storage unit group address is mapped as the physical memory cell group address.Fig. 8 C-8F shows and implement the look-up table that shines upon of the present utility model between logic storage unit group address and physical memory cell group address.
In an example, main frame is with the LBA accessing storage device.LBA is converted into first logic storage unit group address and the form of organizing bias internal.In another example, main frame is directly with the address pattern accessing storage device of logic storage unit group address with the group bias internal.Referring to Fig. 8 C-Fig. 8 F, " logic storage unit group " row provide the logic storage unit group address and have been placed on the interior group bias internal of bracket.For example, for " 1[X] " of " logic storage unit group " row, " 1 " presentation logic storage unit group address wherein, and " [X] " expression group bias internal." [X] " can storage block or memory page be unit, in the address mapping that Fig. 8 C-Fig. 8 F provides, can ignore group bias internal " [X] " part.And a plurality of logical blocks in the memory device are organized as cell group.Each cell group comprises a plurality of storage blocks or memory page.
By the look-up table that Fig. 8 C-Fig. 8 F provides, between logic storage unit group address and physical memory cell group address, set up one-to-one relationship.To will be appreciated that also the look-up table of Fig. 8 C-8F can be two-way, both can pass through the logic storage unit group address, obtain corresponding physical memory cell group address; Also can pass through the physical memory cell group address, obtain corresponding logic storage unit group address.
Referring to Fig. 8 C, memory device comprises 10 passages, comprises two flash chips on each passage.A plurality of logical blocks on each flash chip form a cell group.Thereby memory device provides 20 cell group.Take cell group as least unit the time, main frame will know that the logic storage unit group address space of memory device is 0-19.It is pointed out that storage block, memory page or sector that main frame can inside, access logic cell group unit, but the content that its look-up table that to be not Fig. 8 C-8F provide is concerned about.Get back to Fig. 8 C, for example, the address that main frame provides is " 4[X] ", the logic storage unit group address of " 4 " representative take the cell group unit as least unit wherein, and storage block, memory page or the sector of " [X] " representative memory cell group inside.By the look-up table of Fig. 8 C, address " 4[X] " is mapped to passage 2, chip 0.And, hinted that here address " 4[X] " is mapped to all logical blocks of passage 2, chip 0.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 8 C provide is concerned about.And the physical memory cell group address has represented the information of passage, chip and/or the logical block at cell group place.
Referring to Fig. 8 D, memory device comprises 6 passages, comprises two flash chips on each passage.Each flash chip comprises 8 logical blocks, and per 4 logical blocks form a cell group.Thereby each flash chip comprises 2 cell group.Thereby memory device provides 24 cell group.Take cell group as least unit the time, main frame will know that the address space of the logic storage unit group of memory device is 0-23.By the look-up table of Fig. 8 D, address " 4[X] " is mapped to passage 1, chip 0, logical block 0-3.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 8 D provide is concerned about.
Referring to Fig. 8 E, memory device comprises 6 passages, comprises two flash chips on each passage.Each flash chip comprises 8 logical blocks, and per 8 logical blocks form a cell group.In the embodiment of Fig. 8 E, consist of 8 logical blocks of a cell group from two flash chips.And in the embodiment of Fig. 8 C and Fig. 8 D, consist of a plurality of logical blocks of a storage unit from identical flash chip.
Get back to Fig. 8 E, memory device provides 12 cell group.Take cell group as least unit the time, main frame will know that the logic storage unit group address space of memory device is 0-11.By the look-up table of Fig. 8 E, address " 4[X] " is mapped to passage 2, chip 0, logical block 0-3, and passage 2, chip 1, logical block 0-3.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 8 E provide is concerned about.
Continuation is referring to Fig. 8 F, and memory device comprises 4 passages, comprises two flash chips on each passage.Each flash chip comprises 2 logical blocks, and per 4 logical blocks form a cell group.In the embodiment of Fig. 8 F, consist of 4 logical blocks of a cell group from four flash chips.Thereby memory device provides 4 cell group.Take cell group as least unit the time, main frame will know that the logic storage unit group address space of memory device is 0-3.By the look-up table of Fig. 8 F, address " 3[X] " is mapped to the chip 1 on passage 0-3, each passage, the logical block 1 on each chip.And " [X] " remain unchanged, because the content that its look-up table that to be not Fig. 8 F provide is concerned about.
Although the mapping relations between specific logic storage unit group address and the physical memory cell group address are provided in Fig. 8 C-Fig. 8 F, but one of ordinary skill in the art will recognize, have multiple other mapping mode between logic storage unit group address and physical memory cell group address.Because logic storage unit group address space and physical memory cell group address space are one to one, by being each address in the logic storage unit group address space, distribute uniquely a physical address in the physical memory cell group address space, one of ordinary skill in the art will obtain the various ways that shines upon one by one between logic storage unit group address and physical memory cell group address.
The look-up table of Fig. 8 C-Fig. 8 F can be implemented as lut circuits.In the situation that the configuration of the circuit daughter board on the circuit motherboard 400 does not change, lut circuits need not to change.
Then referring to Fig. 9, Fig. 9 is the process flow diagram according to the cell group address mapping method of embodiment of the present utility model.Before implementing the address mapping, at first obtain the configuration information of cell group, and set up address mapping table.In step 990, obtain the cell group quantity on the circuit daughter board of memory device.In an example, the quantity of the logical block on the acquisition cuicuit daughter board 410, and with the quantity of the logical block number of logic cells N divided by each cell group, obtain the quantity of cell group.In an example, 3 lead-in wires that the interface by circuit daughter board 410 provides obtain the quantity of the logical block of circuit daughter board 410.In another example, circuit motherboard 400 comprises circuit daughter board 410 and 420, comprises 24 logical blocks on the circuit daughter board 410, and comprises 48 logical blocks on the circuit daughter board 420, and each cell group comprises 8 logical blocks.And then the quantity that can obtain on the circuit motherboard 400 cell group of arranging is 9, and can obtain the distribution of these cell group on circuit daughter board 410 and 420.
In step 992, computational logic cell group address realm.Quantity according to the cell group that has obtained, can determine the upper limit of the storage space take cell group as least unit of circuit motherboard 400, this upper limit be offered the upper limit in the logic storage unit group address space of main frame as circuit motherboard 400 or memory device.When circuit motherboard 400 comprised 7 cell group, the corresponding logic storage unit group address scope take cell group as least unit was 0-6.When circuit motherboard 400 comprised 48 cell group, the corresponding logic storage unit group address scope take cell group as least unit was 0-47.
In step 994, provide the logic storage unit group address that calculates scope.In an example, logic storage unit group address scope is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.In an example, with the specific memory location of logic storage unit group address scope range storage that calculates---register for example, main frame can obtain the address realm of logic storage unit group by accessing this register.
In step 996, set up the two-way mapping table between logic storage unit group address and physical memory cell group address.In according to embodiment of the present utility model, logic storage unit group address space and physical memory cell group address space are shone upon one by one.In an example, when main frame during take cell group as the unit accessing storage device, the logic storage unit group address space that main frame provides with obviously have one by one mapping relations with the physical memory cell group address space on the memory device.In another example, when main frame with storage block, memory page or sector during as the least unit accessing storage device, continuous a plurality of storage blocks, memory page or sector is organized as and has with the identical size of cell group in logic, thereby form with the logic storage unit group address of cell group as unit, thereby so that logic storage unit group address space with have one by one mapping relations with the physical memory cell group address space on the memory device.
In step 980, receive order.In an example, order is the order that is used for accessing storage device from main frame, carries or otherwise indicate the logic storage unit group address that is used for accessing storage device or the LBA that can be exchanged into the logical block group address in order.And in another example, order comes from the data that need to read and offers main frame from memory device, carries or indicate the physical memory cell group address of institute's sense data in order.In another example still, mistake appears in the flash chip that order comes from memory device, carries or indicate the physical memory cell group address that wrong position occurs in order.The concrete meaning of these orders is not intended to limit protection domain of the present utility model, but there is the order of various ways and/or purposes in explanation, need to shine upon wherein physical memory cell group address or logic storage unit group address.
In step 982, the direction of the address mapping that judgement will be carried out is the mapping from the logic storage unit group address to the physical memory cell group address, or the mapping from the physical memory cell group address to the logic storage unit group address.Can judge based on form and/or the purposes of order, also can judge based on ad hoc structure or coded portion in the order.
If the physical memory cell group address is mapped to the logic storage unit group address, for example, order comes from the data that need to read and offers main frame from memory device, so, proceed to step 984, based on carrying in the order or obtaining the logic storage unit group address by the indicated physical memory cell group address of order.In an example, can the physical memory cell group address be mapped as the logic storage unit group address by the look-up table that provides such as Fig. 8 C-Fig. 8 F.In step 986, operate according to the logic storage unit group address that obtains.For example, come from the data that need from memory device, to read in order and offer in the situation of main frame, logic storage unit group address or LBA are sent to main frame together with the data of reading.In another example, the flash chip that comes from memory device in order occurs in the wrong situation, and logic storage unit group address or LBA and/or error message are offered main frame.
If the logic storage unit group address is mapped to physical address, for example, order is the order that is used for accessing storage device from main frame, so, proceed to step 988, based on carrying in the order or obtaining the physical memory cell group address by indicated logic storage unit group address or the LBA of order.Can the logic storage unit group address be mapped as the physical memory cell group address by the look-up table that provides such as Fig. 8 C-Fig. 8 F.In step 989, according to the physical memory cell group address access flash chip that obtains.For example, according to the order from main frame, with the physical memory cell group address that obtains data are write flash chip, perhaps with the physical memory cell group address sense data from flash chip that obtains.
In step 992, whether the logic storage unit group quantity on the testing circuit motherboard 400 changes.The variation of logic storage unit group quantity for example comes from and inserts circuit daughter board 410 to circuit motherboard 400, removes circuit daughter board 410 etc. from circuit motherboard 400.If the quantity of logic storage unit group changes, then turn to step 990, again obtain logic storage unit group quantity, and set up the mapping table between logic storage unit group address and the physical memory cell group address.If logic storage unit group quantity does not change, then need not to change the mapping table between logic storage unit group address and the physical memory cell group address, and proceed to step 980, to wait for the reception to next order.
In the superincumbent description, described the address mapping between LBA and the PBA in conjunction with Fig. 4, Fig. 5 A-5D, Fig. 6, and the address of having described between logic storage unit group and the physical memory cell group in conjunction with Fig. 8 A-8F, Fig. 9 is shone upon.In optional embodiment, can also between logical address and physical address, shine upon one by one take plane (Plane) as unit.
Figure 10 A-10D is the process flow diagram according to the mapping of setting up logical address and physical address of embodiment of the present utility model.When the circuit daughter board on the circuit motherboard 400 changes, need to rebulid the mapping between logical address and the physical address.
Referring to Figure 10 A, circuit motherboard comprises circuit daughter board 410 and circuit daughter board 420.In step 1000, the quantity of the logical block on the acquisition cuicuit daughter board 410.In an example, in the interface of circuit daughter board 410, provide 3 lead-in wires, every lead-in wire is by the configuration on the electric signal indicating circuit daughter board 410 of its transmission.For example, comprise first passage, second channel and third channel on the circuit daughter board 410, wherein be furnished with 1 flash chip or 2 flash chips on each passage.One of ordinary skill in the art also can recognize the mode of the configuration of other indicating circuit daughter boards 410.Perhaps these 3 lead-in wires can be indicated the quantity of the logical block of arranging on each passage, for example are furnished with 8 logical blocks on the first passage, are furnished with 8 logical blocks on the second channel, and are furnished with 16 logical blocks on the third channel.In example still, comprise 3 passages on the configuration information indicating circuit daughter board 410 of circuit daughter board 410,3 passages include in the situation of 16 logical blocks, and the quantity that can obtain the logical block of arranging on the circuit motherboard 400 is 48.
In step 1002, the quantity of the logical block on the acquisition cuicuit daughter board 420.In an example, circuit motherboard 400 comprises circuit daughter board 410 and 420, comprise 24 logical blocks on the circuit daughter board 410, and comprise 48 logical blocks on the circuit daughter board 420, thereby by the number of logic cells summation to each circuit daughter board, the quantity that can obtain the logical block of layout on the circuit motherboard 400 is 72, and can obtain the distribution of these logical blocks on circuit daughter board 410 and 420.
In step 1004, the computational logic address realm.According to the quantity of the logical block that has obtained, can determine the upper limit of the storage space take logical block as least unit of circuit motherboard 400, this upper limit is offered the upper limit of the logical address space of main frame as circuit motherboard 400 or memory device.When circuit motherboard 400 comprised 72 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-71; When circuit motherboard 400 comprised 48 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-47.
In step 1006, the ranges of logical addresses that calculates is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.In an example, the ranges of logical addresses that calculates is stored specific memory location---for example register---so that main frame can be by the access to this register, and know the memory capacity that memory device has.When memory device comprises 72 logical blocks, inform that to main frame the ranges of logical addresses take logical block as least unit of memory device is 0-71.In an example, the ranges of logical addresses that provides to main frame with other unit as least unit, for example, with storage block, memory page, sector or cell group as least unit.The quantity of storage block, memory page or sector can be the multiple of number of logic cells, and each cell group can comprise N logical block.
In step 1008, set up the two-way mapping table between logical address and physical address.In according to embodiment of the present utility model, logical address space and physical address space shine upon one by one.In an example, when logical address space with logical block during as least unit, logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.In another example, when main frame with storage block, memory page or sector during as the least unit accessing storage device, continuous a plurality of storage blocks, memory page or sector is organized as and has with the identical size of logical block in logic, thereby form with the logical address of logical block as least unit, thereby so that logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.In another example still, when main frame during take cell group as the least unit accessing storage device, set up the one by one mapping relations between logic storage unit group and the physical memory cell group.In another example, provide ranges of logical addresses take storage block as least unit to main frame, and set up the one by one mapping relations between logic storage unit group and the physical memory cell group, and memory device will be converted to the logic storage unit group address from the logical address take storage block as least unit of main frame.
Referring to Figure 10 B, after on circuit motherboard 400, adding tertiary circuit daughter board (for example the circuit daughter board 430), rebulid the mapping between logical address and the physical address.In step 1010, insert circuit daughter board 430 to circuit motherboard 400.In step 1012, the quantity of the logical block on the acquisition cuicuit daughter board 430.In an example, in the interface of circuit daughter board 430, provide 3 lead-in wires, every lead-in wire is by the configuration on the electric signal indicating circuit daughter board 410 of its transmission.
In step 1014, the computational logic address realm.Quantity summation to the logical block of each circuit daughter board (circuit daughter board 410,420 and 430) of having obtained, can determine the upper limit of the storage space take logical block as least unit of circuit motherboard 400, this upper limit be offered the upper limit of the logical address space of main frame as circuit motherboard 400 or memory device.When circuit motherboard 400 comprised 72 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-71; When circuit motherboard 400 comprised 48 logical blocks, the corresponding ranges of logical addresses take logical block as least unit was 0-47.
In step 1016, the ranges of logical addresses that calculates is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.
In step 1018, set up the two-way mapping table between logical address and physical address.In according to embodiment of the present utility model, logical address space and physical address space shine upon one by one.In an example, when logical address space with logical block during as least unit, logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.In another example, when main frame with storage block, memory page or sector during as the least unit accessing storage device, continuous a plurality of storage blocks, memory page or sector is organized as and has with the identical size of logical block in logic, thereby form with the logical address of logical block as least unit, thereby so that logical address space obviously has one by one mapping relations with physical address space take the logical block of flash chip as least unit.In another example still, when main frame during take cell group as the least unit accessing storage device, set up the one by one mapping relations between logic storage unit group and the physical memory cell group.In another example, provide ranges of logical addresses take storage block as least unit to main frame, and set up the one by one mapping relations between logic storage unit group and the physical memory cell group, and memory device will be converted to the logic storage unit group address from the logical address take storage block as least unit of main frame.
Referring to Figure 10 C, behind the first circuit daughter board (for example the circuit daughter board 410) of having replaced circuit motherboard 400 and/or second circuit daughter board (for example the circuit daughter board 420), rebulid the mapping between logical address and the physical address.In step 1020, change the circuit daughter board 410 on the circuit motherboard 400.In step 1022, the quantity of the logical block on the acquisition cuicuit daughter board 410.In step 1024, the quantity of the logical block on the acquisition cuicuit daughter board 420.
In step 1026, the computational logic address realm.Quantity summation to the logical block of each circuit daughter board (circuit daughter board 410 and 420) of having obtained, can determine the upper limit of the storage space take logical block as least unit of circuit motherboard 400, this upper limit be offered the upper limit of the logical address space of main frame as circuit motherboard 400 or memory device.
In step 1028, the ranges of logical addresses that calculates is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.
In step 1029, set up the two-way mapping table between logical address and physical address.In according to embodiment of the present utility model, logical address space and physical address space shine upon one by one.
Referring to Figure 10 D, when remove the first circuit daughter board (for example the circuit daughter board 410) from circuit motherboard 400 after, rebulid the mapping between logical address and the physical address.In step 1030, remove the circuit daughter board 410 on the circuit motherboard 400.In step 1032, the quantity of the logical block on the acquisition cuicuit daughter board 420.In step 1034, the computational logic address realm.Quantity summation to the logical block of the circuit daughter board on the circuit motherboard 400 (circuit daughter board 410), can determine the upper limit of the storage space take logical block as least unit of circuit motherboard 400, this upper limit be offered the upper limit of the logical address space of main frame as circuit motherboard 400 or memory device.In step 1036, the ranges of logical addresses that calculates is offered main frame, make main frame know the memory capacity that circuit motherboard 400 or memory device have.In step 1038, set up the two-way mapping table between logical address and physical address.In according to embodiment of the present utility model, logical address space and physical address space shine upon one by one.
Figure 11 is the theory diagram according to the memory device of the utility model embodiment.The control circuit 660 of memory device is coupled to circuit daughter board 410,420.Circuit daughter board 410,420 is coupled to control circuit 660 by private bus separately.Can also comprise more circuit daughter board in the memory device.Control circuit 660 also is coupled to main frame 710 by host interface.Control circuit 660 comprises that also processor 728, logical address are to physical address mapping table circuit 732, physical address to logical address mapping table circuit 734 and flash interface circuit 730.
Processor 728 acquisition cuicuit daughter boards 410,420 configuration.Particularly, processor 728 obtains each the quantity of logical block of circuit daughter boards 410,420, and calculates the total amount of the logical block that all the circuit daughter boards 410,420 on the memory device have.And then processor 728 calculates the scope of the logical address take logical block as least unit that memory device presents to main frame 710.Processor 728 is also set up the two-way mapping table between logical address and physical address, and the logic-based address to the mapping table of physical address and the initialization logic address to physical address mapping table circuit 732, and based on physical address to the mapping table of logical address and the initialization physical address to logical address mapping table circuit 734.Logical address can realize by lut circuits to logical address mapping table circuit 734 to physical address mapping table circuit 732 and physical address, also can be by FPGA inner or outside RAM(Random Access Memory, random access storage device) realize.A plurality of flash chips that flash interface circuit 730 is used on the access circuit daughter board 410 and 420.Although figure 11 illustrates single flash interface circuit 730, be understandable that, a plurality of flash interface circuit 730 can be provided, with to a plurality of circuit daughter boards 410,420 and on a plurality of flash chips carry out concurrent access.
In control circuit 660, also comprise the testing circuit (not shown), for detection of circuit daughter board 410,420 configuration, with the quantity of acquisition cuicuit daughter board 410,420 the logical block that each was provided.And make circuit daughter board 410 that processor 728 addressable testing circuits obtain, 420 each the quantity of logical block.Testing circuit also detects circuit daughter board 410,420 variation (insert, remove etc.), and when detecting circuit daughter board 410,420 and change, again the quantity of acquisition cuicuit daughter board 410, each logical block that provides of 420.And, detecting circuit daughter board 410,420 in response to testing circuit and change, processor 728 rebulids logical address and arrives logical address mapping table 734 to physical address mapping table 732 and physical address.
Referring to the process flow diagram that provides among Fig. 6 or Fig. 9, when needs were converted to physical address with logical address, processor 728 logical address that will extract from order or that otherwise obtain sent to logical address to physical address mapping table circuit 732.Logical address as input, and produces the physical address corresponding with it as output to physical address mapping table circuit 732 receive logic addresses, and the physical address of exporting is sent to flash interface circuit 730.Flash interface circuit 730 is based on this physical address, the flash chip on the access circuit daughter board 410 and/or 420.When needs will be logical address from the physical address translations of flash interface circuit 730, flash interface circuit 730 sent to physical address to logical address mapping table circuit 734 with logical address.Physical address receives physical address as input to logical address mapping table circuit 734, and produces corresponding with it logical address as output, and this logical address is sent to processor 728.Then, for example, offer in the situation of main frame in the data that needs will be read from memory device, logical address is sent to main frame together with the data of reading.In another example, in the wrong situation of the flash chip appearance of memory device, logical address and/or error message are offered main frame.
In another embodiment, the quantity of the cell group that provides of testing circuit testing circuit daughter board 410 and 420.Processor 728 usefulness logic storage unit group addresss arrive physical address mapping table circuit 732 and physical address to logical address mapping table circuit 734 to the mapping relations initialization logic address between the physical memory cell group address.Processor 732 sends to logical address to physical address mapping table circuit 732 with the logic storage unit group address, logical address generates corresponding physical memory cell group address to physical address mapping table circuit 732, and send to flash interface circuit 730, so that the flash chip on flash interface circuit 730 access circuit daughter boards 410 and 420.And flash interface circuit 730 sends to physical address to logical address mapping table circuit 734 with the physical memory cell group address, and physical address sends to processor 728 to logical address mapping table circuit 734 with the logic storage unit group address that mapping obtains.
Storage system also is provided.Storage system according to the utility model embodiment comprises main frame 710 and memory device 400.One or more memory devices 400 can be connected to main frame 710.In an example, memory device 400 is connected to main frame 710 by the PCIE interface.Can also memory device 400 be coupled to main frame 710 with multiple other interface, multiple interfaces includes but not limited to SATA, USB, PCIE, SCSI, IDE, FC etc.
Represented description of the present utility model for the purpose that illustrates and describe, and be not intended to disclosed form limit or restriction the utility model.To one of ordinary skill in the art, many adjustment and variation are apparent.
Claims (25)
1. a memory device comprises a plurality of storage unit, storage unit interface circuit, address mapping circuit and processor,
Described processor will send to for the logical address of memory device described address mapping circuit;
Described address mapping circuit is mapped as physical address for storage unit with described logical address, and described physical address is sent to described storage unit interface circuit;
Described storage unit interface circuit is accessed described storage unit based on described physical address.
2. memory device according to claim 1, wherein said address mapping circuit is lut circuits.
3. memory device according to claim 1 and 2 also comprises testing circuit, host interface, first circuit board and second circuit board; Described a plurality of storage unit is arranged on described first circuit board and the described second circuit board;
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses.
4. memory device according to claim 3, wherein said processor is based on described the first quantity and described the second quantity, set up look-up table, and with the described address of described look-up table initialization mapping circuit, described look-up table is used for each logical address in the described ranges of logical addresses is mapped to physical address for the storage unit on first circuit board or the second circuit board.
5. memory device according to claim 3, wherein said the first quantity is different from described the second quantity.
6. memory device according to claim 1 and 2 also comprises testing circuit, host interface, first circuit board; Described a plurality of storage unit is arranged on the described first circuit board;
Described testing circuit obtains the first quantity of the storage element on the described first circuit board;
Described host interface will send to main frame based on the ranges of logical addresses that described the first quantity obtains, and the value of wherein said logical address is within described ranges of logical addresses.
7. described memory device one of according to claim 1 and 2, wherein said storage unit is logical block, tube core or the plane in the memory chip.
8. memory device according to claim 7 comprises a plurality of storage blocks in the wherein said storage unit, and when the storage block in the described storage unit was damaged, the mapping relations that described logical address is mapped as for the physical address of storage unit remained unchanged.
9. described memory device one of according to claim 1 and 2 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
10. memory device according to claim 3 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
11. memory device according to claim 4 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
12. memory device according to claim 5 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
13. memory device according to claim 6 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
14. memory device according to claim 7 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
15. memory device according to claim 8 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
16. memory device according to claim 9 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
17. memory device according to claim 10 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
18. memory device according to claim 11 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
19. memory device according to claim 12 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
20. memory device according to claim 13 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
21. memory device according to claim 14 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
22. memory device according to claim 15 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
23. memory device according to claim 4, wherein said the first quantity is different from described the second quantity.
24. memory device according to claim 23 also comprises the second address mapping circuit, wherein
Described storage unit interface circuit will send to described the second address mapping circuit from the physical address that is used for described storage unit of storage unit;
Described the second address mapping circuit is logical address with described physical address map, and described logical address is sent to described processor.
25. memory device according to claim 24 also comprises testing circuit,
Described testing circuit obtains the first quantity of the storage element on the described first circuit board, obtains the second quantity of the storage unit on the second circuit board;
Described host interface will obtain ranges of logical addresses based on described the first quantity and described the second quantity and send to main frame, and the value of wherein said logical address is within described ranges of logical addresses; And
Described processor is based on described the first quantity and described the second quantity, set up second look-up table, and with described the second address mapping circuit of described second look-up table initialization, described second look-up table is used for being used for the physical address map of the storage unit on first circuit board or the second circuit board to the interior logical address of described ranges of logical addresses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320005176 CN203241990U (en) | 2013-01-06 | 2013-01-06 | Storage device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320005176 CN203241990U (en) | 2013-01-06 | 2013-01-06 | Storage device |
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| CN203241990U true CN203241990U (en) | 2013-10-16 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914390B (en) * | 2013-01-06 | 2016-08-17 | 北京忆恒创源科技有限公司 | Storage device |
| CN108735263A (en) * | 2017-04-19 | 2018-11-02 | 北京兆易创新科技股份有限公司 | A kind of method and apparatus improving operating efficiency |
-
2013
- 2013-01-06 CN CN 201320005176 patent/CN203241990U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914390B (en) * | 2013-01-06 | 2016-08-17 | 北京忆恒创源科技有限公司 | Storage device |
| CN108735263A (en) * | 2017-04-19 | 2018-11-02 | 北京兆易创新科技股份有限公司 | A kind of method and apparatus improving operating efficiency |
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Address after: 100192 room A302, building B-2, Dongsheng Science Park, Zhongguancun, 66 xixiaokou Road, Haidian District, Beijing Patentee after: Beijing yihengchuangyuan Technology Co.,Ltd. Address before: 312, building D, entrepreneurship Park, No. 2, Shangdi Information Road, Haidian District, Beijing 100085 Patentee before: BEIJING MEMBLAZE TECHNOLOGY Co.,Ltd. |
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Granted publication date: 20131016 |