CN203102262U - Memory device with multiple processors - Google Patents
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- CN203102262U CN203102262U CN2013200052346U CN201320005234U CN203102262U CN 203102262 U CN203102262 U CN 203102262U CN 2013200052346 U CN2013200052346 U CN 2013200052346U CN 201320005234 U CN201320005234 U CN 201320005234U CN 203102262 U CN203102262 U CN 203102262U
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Abstract
The utility model provides a memory device with multiple processors. The memory device with the multiple processors comprises a main machine interface and multiple memory chips, wherein each memory chip comprises multiple first memory cells and storage unit sets which are formed by multiple second storage cells, and the storage cells inside each storage unit set can be accessed in a parallel mode. The memory device with the multiple processors further comprises a storage cell group address generation circuit used for generating a first storage cell group address according to a first address received from the main machine interface, wherein the first storage cell group address is used for accessing the first storage cells.
Description
Technical field
The utility model relates to solid storage device, and (Solid Storage Device, SSD), more specifically, scheduling and address that the utility model relates to a plurality of processors of memory device generate.
Background technology
Similar with the mechanical type hard disk, solid storage device (SSD) also is high capacity, the non-volatile memory device that is used for computer system.Solid storage device generally with flash memory (Flash) as storage medium.High performance solid storage device is used to high-performance computer.High-performance computer has a plurality of central processing units (CPU, Central Process Unit) usually, and each CPU can comprise a plurality of CPU nuclears.
Memory capacity increase along with solid storage device, the quantity of included flash chip and/or memory capacity also increase thereupon in the solid storage device, exist the probability of defective also to increase in the flash chip thereupon, and wrong probability in the process of system's visit flash chip, occurs also in increase.Referring to Fig. 1, be in the U.S. Patent application of US20100268985A1 at publication number, data reconstruction method and equipment in solid-state memory system are disclosed.Among Fig. 1, memory device comprises memory target (target) group 510-513 and 520.Memory target is one or more logical blocks (Logic Unit) of shared chip enable (CE, the Chip Enable) signal in the nand flash memory encapsulation.Each logical block has logical unit number (LUN, Logic Unit Number).Can comprise one or more tube cores (Die) in the nand flash memory encapsulation.Typically, logical block is corresponding to single tube core.Logical block can comprise a plurality of planes (Plane).A plurality of planes in the logical block can parallel access, and a plurality of logical blocks in the nand flash memory chip fill order and report condition independently of one another.Can from http://www.micron.com/ ~/ " Open NAND Flash Interface Specification(Revision3.0) " that media/Documents/Products/Other%20Documents/ONFI3_0Gold.a shx obtains, implication about target (target), logical block, LUN, plane (Plane) is provided, and it is the part of prior art.
Among Fig. 1, data register (0-n) (501-504) is coupled to memory target group 510-513 respectively.Data register R500 is coupled to memory target group 520.Memory target group 520 storage redundancy data.Data from memory target group 510-513 and 520 are carried out xor operation by data reconstruction circuit 650, thereby exist under the wrong situation in data, can correct a mistake by data reconstruction circuit 650.Thereby, utilize RAID(Redundant Array of Inexpensive Disks) technology, improved the reliability of solid storage device.
In Fig. 2, publication number be US20080209116A1 U.S. Patent Application Publication have a flash memory device of multiprocessor.Memory device 200 comprises host interface controller 204.Memory device 200 also comprises a plurality of processor unit 202(1-n).Each processor unit has special-purpose RAM.Special-purpose RAM is used for data cached and other data management functions.RAM also comprises flash-memory management data (FMD, Flash Management Data) table, and it comprises the state of LBA (Logical Block Addressing) (LBA, Logic Block Address) and flash memory.Processor unit 202(1-n) is the low-cost processes device.Each processor unit has special-purpose bus 205(1-n) be coupled to flash memory 201(1-n).Processor unit is used to handle the order from main frame.In Fig. 2, processor unit 202(1-n) and flash memory 201(1-n) be one-to-one relationship, in other embodiments, can otherwise be coupled between processor unit and the flash memory.Data flow control 203 is connected to host interface controller 204 by bus, and data flow control 203 determines to use which flash memory passage,, use which processor unit that is.But data flow control 203 sequential processes request of access, first request of being about to sends to processor 202(1), next one request is sent to processor 202(2).Data flow control 203 also can select to handle requesting processor 202(1-n at random).In other embodiments, also can be a certain processor unit and distribute specific flash memory space.For example, be processor 202(1) divide the flash memory part be used in the storage routine data, and with processor 202(2) divide the flash memory part that is used in store backup data.By a plurality of processors are provided, memory device I O Request Processing ability and extendability have been improved in memory device.
Yet, in the prior art at random or order give the mode of processor allocation request, need each processor all to handle the request of access in whole flash memory address space, this will cause big resource to use expense or conflict.And, then will cause in system run duration for the mode of the data space of giving each processor distribution special-purpose, the utilization factor of each processor is unbalanced.
Summary of the invention
According to first aspect of the present utility model, a kind of memory device is provided, comprise host interface, a plurality of memory chips; Comprise more than first storage unit in each memory chip, form cell group by more than second storage unit, but the storage unit concurrent access in each cell group; Described data storage device also comprises the cell group address generating circuit, is used for generating the first storage unit group address according to first address that receives from host interface, and the wherein said first storage unit group address is used to visit first cell group.
According to the memory device of first aspect of the present utility model, wherein each of a plurality of storage unit in each storage chip is logical block, tube core or plane.
Memory device according to first aspect of the present utility model, wherein said cell group address generating circuit is with the quantity of described first address divided by the cell group in the data storage device, obtain first merchant and first remainder, described first merchant is as the first storage unit group address.
Memory device according to first aspect of the present utility model, also comprise a plurality of processors, first processor in described a plurality of processor receives the described first storage unit group address, and the described first storage unit group address is used for visit to described first cell group.
According to the described memory device of first aspect of the present utility model, wherein described first remainder is asked mould with respect to the quantity of described a plurality of processors, obtain first mould, select described first processor based on described first mould.
According to the memory device of first aspect of the present utility model, wherein select described first processor with round robin or random fashion.
Memory device according to first aspect of the present utility model, also comprise the cell group counting circuit, be used for obtaining first quantity of the storage unit of described data storage device, and determine the quantity of the cell group in the described data storage device based on described first quantity.
According to the memory device of first aspect of the present utility model, also comprise first circuit board, be furnished with a plurality of storage chips on the described first circuit board; Wherein said cell group counting circuit obtains described first quantity of the storage unit on the described first circuit board.
According to the memory device of first aspect of the present utility model, also comprise first circuit board and second circuit board, be furnished with a plurality of storage chips on the described first circuit board, be furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
According to the memory device of first aspect of the present utility model, wherein each cell group comprises N storage unit, and wherein said first quantity obtains the quantity of the cell group in the described data storage device divided by N.
According to the memory device of first aspect of the present utility model, a plurality of storage unit of wherein said first cell group are contained in the first memory chip.
According to the memory device of first aspect of the present utility model, wherein said visit to described first cell group comprises a plurality of or whole storage unit in described first cell group.
According to second aspect of the present utility model, a kind of server is provided, comprise memory device according to first aspect of the present utility model, described memory device and described server are coupled by described host interface.
According to the third aspect of the present utility model, a kind of method that is used for memory device is provided, described memory device comprises a plurality of host interface and a plurality of memory chip, described method comprises: receive first address from main frame; Generate the first storage unit group address based on described first address, the wherein said first storage unit group address is used to visit first cell group, and wherein comprise more than first storage unit in each memory chip, form cell group by more than second storage unit, but the storage unit concurrent access in each cell group.
According to the method for the third aspect of the present utility model, wherein each of a plurality of storage unit in each storage chip is tube core, logical block or plane.
Method according to the third aspect of the present utility model, wherein generate the described first storage unit group address and be by with the quantity of described first address divided by the cell group in the data storage device, obtain first merchant and first remainder, described first merchant is as the first storage unit group address.
Method according to the third aspect of the present utility model, wherein said memory device also comprises a plurality of processors, described method also comprises: receive the described first storage unit group address by the first processor in described a plurality of processors, and the described first storage unit group address is used for visit to described first cell group.
According to the method for the third aspect of the present utility model, wherein described first remainder is asked mould with respect to the quantity of described a plurality of processors, obtain first mould, select described first processor based on described first mould.
According to the method for the third aspect of the present utility model, wherein select described first processor with round robin or random fashion.
According to the method for the third aspect of the present utility model, also comprise first quantity of the storage unit of obtaining in the described data storage device, and determine the quantity of the cell group in the described data storage device based on described first quantity.
According to the method for the third aspect of the present utility model, wherein said memory device also comprises first circuit board, is furnished with a plurality of storage chips on the described first circuit board; And first quantity of wherein obtaining the storage unit in the described data storage device is described first quantity that obtains the storage unit on the described first circuit board.
According to the method for the third aspect of the present utility model, wherein said memory device also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board; And first quantity of wherein obtaining the storage unit in the described data storage device is described first quantity that obtains the storage unit on described first circuit board and the described second circuit board.
According to the method for the third aspect of the present utility model, wherein each cell group comprises N storage unit, and wherein said first quantity obtains the quantity of the cell group in the described data storage device divided by N.
According to the method for the third aspect of the present utility model, a plurality of storage unit of wherein said first cell group are contained in the first memory chip.
According to the method for the method of the third aspect of the present utility model, wherein said visit to described first cell group comprises a plurality of or whole storage unit in described first cell group.
Description of drawings
When reading together with accompanying drawing, by the detailed description of reference back, will understand the utility model best and preferably use pattern and its further purpose and advantage the embodiment of illustrating property, wherein accompanying drawing comprises:
Fig. 1 is the structured flowchart according to the memory device of prior art;
Fig. 2 is the structured flowchart according to another memory device of prior art;
Fig. 3 is the front elevation according to the memory device of embodiment of the present utility model;
Fig. 4 A-4E is the schematic diagram according to the connected mode of the flash chip of the circuit daughter board of the memory device of embodiment of the present utility model and control circuit;
Fig. 5 shows the schematic diagram according to the organizational form of the storage unit of the memory device of embodiment of the present utility model;
Fig. 6 shows the figure of the address mapping relation of implementing embodiment of the present utility model;
Fig. 7 shows the figure of the mapping relations of the storage unit group address of implementing embodiment of the present utility model and processor;
Fig. 8 is the theory diagram according to the utility model memory device;
Fig. 9 is the block diagram according to the storage system of embodiment of the present utility model; And
Figure 10 A, 10B are the process flow diagrams according to the disposal route of embodiment of the present utility model.
Embodiment
Fig. 3 is the front elevation according to the memory device of embodiment of the present utility model.Memory device shown in Figure 3 comprises circuit motherboard 400.Circuit motherboard 400 is the circuit boards with PCIE half high card form, and it can be connected to computing machine by the PCIE slot.Be furnished with circuit daughter board 410,420,430 and 440 on the circuit motherboard 400.In one embodiment, be furnished with flash chip 411-413,421-423,431-433 and 441-443 respectively on the circuit daughter board 410,420,430 and 440, make circuit daughter board 410,420,430 and 440 provide memory capacity to memory device.Though figure 3 illustrates and on each of circuit daughter board 410-440, place three flash chips, one of ordinary skill in the art will recognize also can place the flash chip of other quantity on circuit daughter board 410-440, for example, placing flash chip on the circuit daughter board 410 with on the surperficial facing surfaces at flash chip 411-413 place.One of ordinary skill in the art also will recognize and the circuit daughter board of varying number can be connected to circuit motherboard 400.
Though figure 3 illustrates the memory device that comprises flash chip with PCIE interface, but one of ordinary skill in the art will recognize, it only is a kind of giving an example, the utility model is applicable to the various electronic with other functions, and can be coupled to computing machine by the multiple interfaces mode, multiple interfaces includes but not limited to SATA(Serial Advanced Technology Attachment, Serial Advanced Technology Attachment), USB(Universal Serial Bus, USB (universal serial bus)), PCIE(Peripheral Component Interconnect Express, quick peripheral assembly interconnecting), SCSI(Small Computer System Interface, small computer system interface), IDE(Integrated Drive Electronics, the integrated drive electronics) etc.And the utility model also is applicable to the storage chip that comprises flash memory other types in addition, for example, and phase transition storage, Memister, ferroelectric memory etc.
Also be furnished with control circuit 660 on circuit motherboard 400, in order to the visit of control to the flash chip on circuit daughter board 410,420,430 and 440, and processing is from the interface command of computing machine.Also be furnished with Memory on the circuit motherboard 400, dynamic RAM such as DRAM(Dynamic Random Access) storer 662,664,666 and 668.Storer 662,664,666 and 668 can be coupled to control circuit 660.Control circuit 660 can be FPGA(Field-programmable gate array, field programmable gate array), ASIC(Application Specific Integrated Circuit, the application specific integrated circuit) or the form of its combination.Control circuit 660 also can comprise processor or controller.Can comprise one, two or more processor core in the control circuit 660, each processor core is used to control or visit the part or all of of a plurality of circuit subcards.Each processor core also can be used for visiting or the control circuit subcard on a plurality of flash chips partly or entirely.
Also be furnished with connector 628 and 629 on the circuit motherboard 400 as shown in Figure 3.Can also will respectively the circuit daughter board be connected to circuit motherboard 400 by connector 628 and 629.Thereby, on circuit motherboard 400 as shown in Figure 3, can connect nearly 6 circuit daughter boards with PCIE half high card form.Circuit daughter board 410 is connected to circuit motherboard 400 by flexible PCB 640.Circuit daughter board 420 is connected to circuit motherboard 400 by flexible PCB 642.Circuit daughter board 430 is connected to circuit motherboard 400 by flexible PCB 644.Circuit daughter board 440 is connected to circuit motherboard 400 by flexible PCB 646.In a similar fashion, the circuit daughter board also is connected to circuit motherboard 400 by flexible PCB via connector 628 or 629.
A plurality of circuit daughter boards placement parallel to each other on the circuit motherboard 400.The minor face of the long edge circuit motherboard 400 of a plurality of circuit subcards is placed, and the minor face of a plurality of circuit daughter boards is placed along the long limit of circuit motherboard 400.The minor face of a plurality of circuit daughter boards is placed along same straight line substantially.Circuit daughter board 410 is relative with 420 head and the tail, and the space of shared flexible PCB 640,642 formation, thereby forms circuit daughter board group.Circuit daughter board 430 is relative with 440 head and the tail, and the space of shared flexible PCB 644,646 formation, thereby forms circuit daughter board group.Similarly, it is relative with 629 circuit daughter board also head and the tail to be connected to connector 628, and formation circuit daughter board group.Can have the space between a plurality of circuit daughter boards and the circuit motherboard, in this space, can arrange other electronic components.
In a preferred embodiment, also provide heat abstractor, be used for the flash chip on a plurality of circuit daughter boards and/or control circuit 660 and/or storer 662,664,666 and 668 heat transferred that produced to the memory device outside.
Fig. 4 A-5E is the schematic diagram according to the connected mode of the flash chip of the circuit daughter board 410 of the memory device of embodiment of the present utility model and control circuit 660.Circuit daughter board 420-440 can be connected to control circuit 660 by the same manner.For the concurrency of the operation that promotes a plurality of flash chips, and the IO resource of saving the needed control circuit 660 of a plurality of flash chips of control, a plurality of flash chips on the circuit daughter board 410 are arranged in a plurality of passages.Be furnished with one or more flash chips in each passage, a plurality of flash chip shared datas and/or control bus in each passage, and in order to visit each flash chip, chip enable (the Chip Enable of a plurality of flash chips in each passage, CE) port can be controlled individually by control circuit 660.
Referring to Fig. 4 A, be furnished with 3 passages on the circuit daughter board 410.Flash chip 411,414 is included in the first passage, and is coupled to control circuit 660 by shared bus 490.Control circuit 660 can be controlled the CE port of flash chip 411,414 independently.Flash chip 412,415 is included in the second channel, and is coupled to control circuit 660 by shared bus 492.Control circuit 660 can be controlled the CE port of flash chip 412,415 independently.Flash chip 413,416 is included in the third channel, and is coupled to control circuit 660 by shared bus 494.Control circuit 660 can be controlled the CE port of flash chip 413,416 independently.
The flash chip that other quantity can be arranged on each passage alternatively.Referring to Fig. 4 B, flash chip 411,412 and 413 is included in the first passage, and is coupled to control circuit 660 by shared bus 490.Control circuit 660 can be controlled the CE port of flash chip 411,412 and 413 independently.Flash chip 414,415 and 416 is included in the second channel, and is coupled to control circuit 660 by shared bus 494.Control circuit 660 can be controlled the CE port of flash chip 414,415 and 416 independently.
The flash chip that can have still alternatively, varying number on each passage.Referring to Fig. 4 C, flash chip 411,414 is included in the first passage, and is coupled to control circuit 660 by shared bus 490.Control circuit 660 can be controlled the CE port of flash chip 411,414 independently.Flash chip 412,415 is included in the second channel, and is coupled to control circuit 660 by shared bus 492.Control circuit 660 can be controlled the CE port of flash chip 412,415 independently.Flash chip 413 is included in the third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can be controlled the CE port of flash chip 413.Notice and in Fig. 4 C, do not provide flash chip 416.Notice, in Fig. 4 C, in first passage and the second channel, be furnished with 2 flash chips, and in third channel, only be furnished with 1 flash chip promptly, have the flash chip of varying number on each passage equally.Though it is pointed out that the flash chip that has varying number on each passage, the memory capacity on each passage can be the same or different.When the flash chip 411-415 among Fig. 4 C had identical memory capacity, the memory capacity on the third channel was half of memory capacity of first passage.Also can provide flash chip 413, make that its memory capacity is two times of flash chip 411,412,414 or 415, thereby make that the memory capacity on each passage is identical.
Though still it is pointed out that in the embodiment of Fig. 4 C, not comprise flash chip 416,, in corresponding circuit daughter board with it, preferably, provide and the identical interface arrangement of circuit daughter board that comprises 6 flash chips.Promptly, though comprise the circuit daughter board of 6 flash chips, the lead-in wire of the CE port that is coupled to flash chip 416 need be provided in interface, but for multiple different circuit daughter board provides identical interface arrangement is favourable, this will allow the different circuit daughter board of coupling on the connector of circuit motherboard 400, thereby improve the dirigibility of memory device, and simplified the installation process of memory device 400, be not limited to be installed on the specific motherboard connector because have the circuit daughter board 410 of particular memory capacity or flash chip quantity.
In one embodiment, in the interface of circuit daughter board 410, provide 3 lead-in wires, every lead-in wire is by being furnished with 1 flash chip or 2 flash chips on the passage in electric signal indication first passage, second channel and the third channel of its transmission.One of ordinary skill in the art also can recognize the mode of the configuration of other indicating circuit daughter boards 410.For example, in the interface of circuit daughter board 410, provide 2 lead-in wires, it can transmit " 00 ", " 01 ", " 10 " and " 11 " four kinds of different states, a kind of customized configuration of each condition indication circuit daughter board 410.Service wire is indicated, can also be the quantity of the storage chip on the circuit daughter board 410, the perhaps memory capacity that provides on the circuit daughter board 410, perhaps included number of channels and the configuration of the flash chip in each passage (quantity and/or memory capacity) on the circuit daughter board 410.
Referring to Fig. 4 D, flash chip 411,414 is included in the first passage, and is coupled to control circuit 660 by shared bus 490.Control circuit 660 can be controlled the CE port of flash chip 411,414 independently.Flash chip 412 is included in the second channel, and is coupled to control circuit 660 by bus 492.Control circuit 660 can be controlled the CE port of flash chip 412.Flash chip 413 is included in the third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can be controlled the CE port of flash chip 413.
Referring to Fig. 4 E, flash chip 411 is included in the first passage, and is coupled to control circuit 660 by bus 490.Control circuit 660 can be controlled the CE port of flash chip 411 independently.Flash chip 412 is included in the second channel, and is coupled to control circuit 660 by bus 492.Control circuit 660 can be controlled the CE port of flash chip 412 independently.Flash chip 413 is included in the third channel, and is coupled to control circuit 660 by bus 494.Control circuit 660 can be controlled the CE port of flash chip 413 independently.
Fig. 5 shows the schematic diagram according to the organizational form of the storage unit of the memory device of embodiment of the present utility model.Logical block 460-472 in the memory device is organized as cell group.Logical block be in the flash chip can independent fill order and the storage unit of report condition.For example, logical block can be a tube core in the flash chip.In other configurations, logical block also can comprise a plurality of tube cores.Comprise N logical block in each cell group, wherein L logical block is used for storaging user data, and M logical block is used for redundant data, and N=L+M, N, L and M are natural number.One of ordinary skill in the art will recognize by adjusting the quantity of L and M, different fault-tolerant abilitys can be provided.For example, when L=M=1, in each cell group, 1 logical block is used for storaging user data, and 1 logical block is used for store backup data in addition, when mistake appears in user data, can utilize Backup Data to recover to occur wrong user data.In another example, L=7, and M=1, adopt parity checking mode provide protection for user data.Also can adopt other fault-tolerant encoding mode to improve the reliability of memory device.Control circuit 660 control is to cell group and the wherein operation of each logical block, and the EDC error detection and correction of the data of cell group is also implemented by control circuit 660.
In a preferred embodiment, N logical block of formation cell group is positioned at same flash chip.Make when cell group generation irrecoverable error, can less cost remove or replace the flash chip that mistake occurs.In another embodiment, N the logical block that forms cell group is from a plurality of or N circuit daughter board (410-440), make in cell group some logical block faults or will use up serviceable life the time, can realize reparation by changing circuit daughter board (410-440).
By logical block is organized as cell group, and be unit storaging user data and redundant data, can improve the reliability of memory device with the cell group.And, but a plurality of logical block concurrent access, thereby, be the unit writes can not influence memory device with sense data readwrite performance with the cell group.One of ordinary skill in the art will recognize, also a plurality of planes or die groupings can be woven to cell group.
Yet main frame is with continuous linear address space accessing storage device 400, thereby needs and will be mapped to each cell group from the linear address (logical address) of main frame, is about to logical address and is converted to the storage unit group address.Fig. 6 shows the schematic diagram according to the address mapping relation of embodiment of the present utility model.In the disclosed embodiment, memory device 400 comprises m cell group, and each cell group comprises n data block.Memory device 400 presents the logical address space with 0 ~ (nm-1) (being unit with the 4KB/8KB/16KB data block) address realm to the main frame that uses this memory device 400.Logical block can comprise a plurality of storage blocks, and each storage block can comprise a plurality of pages or leaves, and typically, one page is 4KB or 8KB or 16KB size.For clear, be indifferent to the data organization mode of logical block inside here.In one embodiment, logical address is LBA(Logic BlockAddress, LBA (Logical Block Addressing))
Table 540 shows memory device 400 and presents to main frame that to have with the data block be 0 ~ (nm-1) address realm of unit.Table 550 then shows with each logical address of table 540 corresponding, is presented as the address pattern of storage unit group address and cell group bias internal.In the table 550, the lateral attitude is corresponding to each cell group, and lengthwise position is corresponding to each cell group bias internal in the cell group.When each cell group comprised n data block, the lengthwise position of table 550 comprised n different cell group bias internal.For example, for the logical address in the table 540 0, be mapped as No. 0 cell group and No. 0 cell group bias internal in the table 550.And the logical address 1 in the table 540 is mapped as No. 1 cell group and No. 0 cell group bias internal in the table 550.Logical address m in the table 540 is mapped as No. 0 cell group and No. 1 cell group bias internal in the table 550.Logical address nm-1 in the table 540 is mapped as m-1 cell group and n-1 cell group bias internal in the table 550.Table 540 can be expressed as with the mapping relations of table 550, and with the number of logical address divided by cell group in the memory device 400, the remainder of gained is as the storage unit group address, and the merchant of gained is as the cell group bias internal.The storage unit group address is corresponding to specific a plurality of logical blocks (or tube core) of the specific flash memory chip of a cell group of formation of the circuit daughter board (410-440) of memory device 400.And the cell group bias internal has been indicated the linear address space in cell group.
Can use divider that the logical address in the table 540 is mapped as storage unit group address and cell group bias internal in the table 550.Also can use the mode of look-up table to realize mapping.And when using look-up table, can in the mapping of storage unit group address and cell group bias internal, adopt other mapping relations in logical address.Can memory device 400 start or the configuration of memory device 400 change the time quantity of the quantity by enumerating of the configuration of circuit daughter board (410-440) found cell group and the logical block that is used for storaging user data in the cell group determine the size of the logical address space that memory device 400 presents to main frame, and set up the mapping relations of logical address to storage unit group address and cell group bias internal.
In embodiment of the present utility model, logical block is organized as cell group, and with the cell group is unit storaging user data and redundant data, and control circuit 660 uses storage unit group address and cell group bias internal to visit corresponding cell group.In one embodiment, control circuit 660 comprises two processors.To give two processors with approximately equalised probability assignments to the request of access of cell group is favourable so that cell group is conducted interviews.And the cell group of distributing to two processors separate be favourable, can reduce resource like this and use expense or conflict.One of ordinary skill in the art will recognize that control circuit 660 can comprise the processor of other quantity, and will give the processor of other quantity with approximately equalised probability assignments to the request of access of cell group also is favourable so that cell group is conducted interviews.
Fig. 7 shows the figure of the mapping relations of the storage unit group address of implementing embodiment of the present utility model and processor.As an example, control circuit 660 comprises two processors among the embodiment of Fig. 7, and its processor numbering is respectively 0 and 1.Row 562 at the table 560 of Fig. 7 has provided and has been numbered the allocation scheme of 0 or 1 processor with respect to a plurality of cell group.Particularly, sending the request of storage unit access group address 0 to processor 0 handles, sending the request of storage unit access group address 1 to processor 1 handles, send the request of storage unit access group address 2 to processor 0 processing, and send the request of storage unit access group m-1 to processor 1 and handle (m is an even number) here.In other words, the storage unit group address is asked mould (or the storage unit group address is divided by remainder of the quantity gained of processor) to the quantity of processor, the result is as the numbering of handling requesting processor that should the cell group address.One of ordinary skill in the art will recognize, can adopt other modes to distribute to one of a plurality of processors corresponding to the request of cell group.For example, with a plurality of requests in order or the mode of poll send to one of a plurality of processors, perhaps a plurality of requests are sent to one of a plurality of processors at random.
Fig. 8 is the theory diagram according to memory device of the present utility model.The control circuit 660 of memory device is coupled to circuit daughter board 410,420.Circuit daughter board 410,420 is coupled to control circuit 660 by private bus separately.Can also comprise more circuit daughter board in the memory device.Control circuit 660 also is coupled to main frame 720 by host interface 720.Control circuit 660 also comprises processor 726,728, storage unit count circuit 724 and cell group address generating circuit 722.
The configuration of memory unit address generative circuit 724 acquisition cuicuit daughter boards 410,420.Particularly, the quantity of the logical block of each of memory unit address generative circuit 724 acquisition circuit daughter boards 410,420, and calculate all the circuit daughter boards 410 on the memory device, the total amount of 420 logical blocks that had, be designated as S.And then storage unit count circuit 724 calculates the scope in linear address (logical address) space that memory device presents to main frame 710.In an example, each cell group comprises N=L+M logical block, and wherein L logical block is used for storaging user data, and M logical block is used for the storage redundancy data.So, comprise in every logical block under the situation of b data block, the linear address that memory device presents to main frame 710 (logical address) spatial dimension is that 0 ~ S*L*b/N(is unit with the data block).Storage unit count circuit 724 also calculates the quantity of the cell group of memory device, for example by calculating S/N, obtains the quantity of the cell group of memory device, and this quantity S/N is sent to cell group address generating circuit 722.
When the request of access that receives from main frame, extract wherein included logical address, this logical address is sent to cell group address generating circuit 722.The cell group address calculating circuit is with the quantity S/N of this logical address divided by cell group, and resulting remainder Q is the storage unit group address, and promptly the pairing data block of this logical address is arranged in the cell group that the storage unit group address is Q.And then, with this logical address divided by the resulting merchant of S/N as the cell group bias internal, and finish request of access.The cell group bias internal has been indicated the linear address space in the cell group.In an example, by being used for the address mapping table of cell group, the cell group bias internal that will be used for this cell group is mapped as the physical address of the data block that is used for this cell group.
In one embodiment, the pairing data block size of the logical address of the request of access of main frame is different from the data block size in the cell group.For example, data block from the LBA correspondence of main frame is 4KB, and the data block of the cell group of memory device (for example, page or leaf) be 8KB, so, cell group address generating circuit 722 moves to right one with this LBA, to give up the lowest order of this LBA, LBA after will moving to right again is divided by the quantity S/N of cell group, with result's remainder Q as the storage unit group address, with result's merchant as the cell group bias internal.Similarly, when the data block of LBA correspondence is 4KB, and the data block of the cell group of memory device is when being 16KB, and cell group address generating circuit 722 moves to right two with this LBA, and the LBA after will moving to right again is divided by the quantity S/N of cell group.
Cell group address generating circuit 722 sends to processor 726 or processor 728 with the storage unit group address that generates.In a preferred embodiment, will send to processor 726 for the storage unit group address of even number, and will send to processor 728 for the storage unit group address of odd number.Make processor 726 and 728 request of access of handling respectively different cell group, and the probability that processor 726 and 728 is handled request of access is identical substantially.Can there be other modes that request of access is sent to processor 726 and 728.For example, be 0 o'clock at the lowest order of the storage unit group address that calculates, this storage unit group address is sent to processor 726, and be 1 o'clock at the lowest order of the storage unit group address that calculates, this storage unit group address is sent to processor 728.Can also be with the quantity of storage unit group address divided by processor, remainder according to gained, the storage unit group address is sent to corresponding processor, for example, at remainder is 0 o'clock, cell group is sent to processor 726(0 processor), and be 1 o'clock at remainder, the storage unit group address is sent to processor 728(1 processor).In another embodiment, can also be according to the sequencing of request of access, order assignment is given processor 726 or 728, perhaps gives processor 726 or 728 with the Random assignment of storage unit group address.
In another embodiment, control circuit 410 comprises three or more processors.One of ordinary skill in the art will recognize to adopt the storage unit group address will be asked mould with respect to processor quantity, and based on the remainder of gained, the storage unit group address be sent to and the corresponding processor of this remainder.Also can adopt modes such as Random assignment or order assignment, select to handle the processor of request of access.
In another embodiment still, be not based on the processor that the cell group address computation receives this storage unit group address, calculate the processor that receives the respective memory unit group address and be based on from the logical address (or LBA) of host interface 720.
Fig. 9 is the block diagram according to the storage system of embodiment of the present utility model.Storage system according to the utility model embodiment comprises main frame 710 and memory device 400.One or more memory devices 400 can be connected to main frame 710.In an example, memory device 400 is connected to main frame 710 by the PCIE interface.Can also memory device 400 be coupled to main frame 710 with multiple other interface, multiple interfaces includes but not limited to SATA, USB, PCIE, SCSI, IDE, FC etc.
Figure 10 A, 10B are the process flow diagrams according to the disposal route of embodiment of the present utility model.At the memory device run duration, receive request of access (1010) from main frame.The cell group address generating circuit 722 of memory device generates storage unit group address (1020) based on the logical address in the request of access (for example LBA).In an example, by with logical address divided by the quantity of the cell group of memory device, with the remainder of gained as the storage unit group address.(obtaining cell group quantity) can also adopt for example mode of look-up table, and logical address is mapped as the storage unit group address.Select one of a plurality of processors in the memory device, the storage unit group address is sent to selected processor (1030).In an example, ask mould to come selection processor to processor quantity based on the storage unit group address.In another example, will or send to one of a plurality of processors randomly corresponding to the cell group sequence of addresses of request of access.In another example still, ask mould to come selection processor to processor quantity based on the logical address in the request of access.Next, selecteed processor is used for visit (1040) to corresponding cell group with the storage unit group address that receives.
For obtaining the quantity of cell group in the memory device, after power at memory device (1050), obtain the quantity (1050) of the storage unit (for example, logical block) in the memory device.In an example, control circuit 660 detects the configuration of a plurality of circuit daughter boards that are coupled to memory device, and obtain the quantity of the storage unit of each circuit daughter board, to the quantity summation of the storage unit of each circuit daughter board, obtain the number of memory cells of memory device.Next, calculate the quantity (1070) of the cell group in the memory device.When comprising N=M+L storage unit in each cell group, divided by N, the merchant of gained is the quantity of the cell group of memory device with the quantity S of the storage unit in the memory device.And the quantity (1080) of preserving resulting cell group.The quantity of the cell group that calculates can be saved in the nonvolatile memory of memory device, make that memory device powers on next time after, need not again execution in step 1050 to step 1080.After the number of memory cells of memory device changes (for example, the circuit subcard that is coupled to memory device changes, perhaps the memory chip on the circuit subcard breaks down), re-execute step 1050-step 1080, the quantity of the cell group in the memory device after changing with acquisition.
Represented description of the present utility model, and be not intended to disclosed form limit or restriction the utility model in order to illustrate with purpose of description.To one of ordinary skill in the art, many adjustment and variation are conspicuous.
Claims (26)
1. a memory device comprises host interface, a plurality of memory chips;
Comprise more than first storage unit in each memory chip, form cell group by more than second storage unit, but the storage unit concurrent access in each cell group;
Described memory device also comprises the cell group address generating circuit, is used for generating the first storage unit group address according to first address that receives from host interface, and the wherein said first storage unit group address is used to visit first cell group.
2. memory device according to claim 1, wherein each of a plurality of storage unit in each storage chip is logical block, tube core or plane.
3. according to a described memory device among the claim 1-2, wherein
Described cell group address generating circuit obtains first merchant and first remainder with the quantity of described first address divided by the cell group in the memory device, and described first merchant is as the first storage unit group address.
4. memory device according to claim 3, also comprise a plurality of processors, first processor in described a plurality of processor receives the described first storage unit group address, and the described first storage unit group address is used for visit to described first cell group.
5. according to the described memory device in the claim 4, wherein
Described first remainder is asked mould with respect to the quantity of described a plurality of processors, obtain first mould, select described first processor based on described first mould.
6. according to the described memory device of claim 4, wherein select described first processor with round robin or random fashion.
7. according to the described memory device in one of claim 1 or 2, also comprise the cell group counting circuit, be used for obtaining first quantity of the storage unit of described memory device, and determine the quantity of the cell group in the described memory device based on described first quantity.
8. memory device according to claim 3 also comprises the cell group counting circuit, is used for obtaining first quantity of the storage unit of described memory device, and determines the quantity of the cell group in the described memory device based on described first quantity.
9. memory device according to claim 4 also comprises the cell group counting circuit, is used for obtaining first quantity of the storage unit of described memory device, and determines the quantity of the cell group in the described memory device based on described first quantity.
10. memory device according to claim 5 also comprises the cell group counting circuit, is used for obtaining first quantity of the storage unit of described memory device, and determines the quantity of the cell group in the described memory device based on described first quantity.
11. memory device according to claim 6 also comprises the cell group counting circuit, is used for obtaining first quantity of the storage unit of described memory device, and determines the quantity of the cell group in the described memory device based on described first quantity.
12. memory device according to claim 7 also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
13. memory device according to claim 8 also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
14. memory device according to claim 9 also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
15. memory device according to claim 10 also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
16. memory device according to claim 11 also comprises first circuit board and second circuit board, is furnished with a plurality of storage chips on the described first circuit board, is furnished with a plurality of storage chips on the described second circuit board;
Wherein said cell group counting circuit obtains described first quantity of the storage unit on described first circuit board and the described second circuit board.
17. according to the described memory device in one of claim 1 or 2, a plurality of storage unit of wherein said first cell group are contained in the first memory chip.
18. a server comprises that as the described memory device in one of claim 1 or 2, described memory device and described server are coupled by described host interface.
19. a server comprises memory device as claimed in claim 3, described memory device and described server are coupled by described host interface.
20. a server comprises memory device as claimed in claim 4, described memory device and described server are coupled by described host interface.
21. a server comprises memory device as claimed in claim 5, described memory device and described server are coupled by described host interface.
22. a server comprises memory device as claimed in claim 6, described memory device and described server are coupled by described host interface.
23. a server comprises memory device as claimed in claim 7, described memory device and described server are coupled by described host interface.
24. a server comprises memory device as claimed in claim 12, described memory device and described server are coupled by described host interface.
25. a server comprises memory device as claimed in claim 16, described memory device and described server are coupled by described host interface.
26. a server comprises memory device as claimed in claim 17, described memory device and described server are coupled by described host interface.
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|---|---|---|---|
| CN2013200052346U CN203102262U (en) | 2013-01-06 | 2013-01-06 | Memory device with multiple processors |
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| CN2013200052346U CN203102262U (en) | 2013-01-06 | 2013-01-06 | Memory device with multiple processors |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914401A (en) * | 2013-01-06 | 2014-07-09 | 北京忆恒创源科技有限公司 | Storage device with multiple processors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103914401A (en) * | 2013-01-06 | 2014-07-09 | 北京忆恒创源科技有限公司 | Storage device with multiple processors |
| CN103914401B (en) * | 2013-01-06 | 2017-05-10 | 北京忆恒创源科技有限公司 | Storage device with multiple processors |
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