CN203179888U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203179888U CN203179888U CN 201320228616 CN201320228616U CN203179888U CN 203179888 U CN203179888 U CN 203179888U CN 201320228616 CN201320228616 CN 201320228616 CN 201320228616 U CN201320228616 U CN 201320228616U CN 203179888 U CN203179888 U CN 203179888U
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- active layer
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- layer
- drain electrode
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Abstract
The utility model relates to the display technical field and provides an array substrate and a display device. The using frequency of a lithography mask layer technology required for making the array substrate can be lowered. The research and development time and the large-scale batch production time can be shortened. The manufacturing cost can be further lowered. The array substrate comprises a substrate, and an active layer and a first transparent electrode both arranged on the substrate. The array substrate further comprises an etching barrier layer arranged on the active layer and protecting an active layer zone between a subsequent source electrode and a subsequent drain electrode. The active layer, the first transparent electrode and the etching barrier layer are formed by adopting a one-time composition technology and a one-time doping technology. The active layer has a doped zone which is made of the same materials as the first transparent electrode. The source electrode and the drain electrode are arranged on the active layer. Transparent conductive materials same to the materials of subsequent second transparent electrodes are arranged among the active layer, the source electrode and the drain electrode. The source electrode and the drain electrode are connected with the doped zone of the active layer through the transparent conductive materials.
Description
Technical field
The utility model relates to the Display Technique field, relates in particular to array base palte and display unit.
Background technology
Continuous progress along with Display Technique, the user constantly increases the demand of display unit, TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor (TFT) LCD) has also obtained using widely in products such as mobile phone, LCD, panel computer.In addition, along with constantly popularizing of display unit, people are also growing for the demand of the chromaticity of display unit, contrast, visible angle, response speed, low-power consumption, so, OLED (Organic Light-Emitting Diode, Thin Film Transistor (TFT) Organic Light Emitting Diode) display also begins to have progressed into user's the visual field.
Prior art need be carried out 6-8 photo etched mask technology this array base palte that just can complete usually when making array base palte, therefore, research and develop and scale of mass production on the time consuming time long, cost of manufacture is higher.
The utility model content
Embodiment of the present utility model provides a kind of array base palte and display unit, can reduce the number of times of making the required photo etched mask technology of array base palte, shortens the time of research and development and scale of mass production, reduces cost of manufacture.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
The utility model embodiment provides a kind of array base palte, comprising:
Substrate;
Be arranged at active layer, first transparency electrode on the described substrate, and on the described active layer, for the protection of the etching barrier layer in active layer zone between follow-up source, the drain electrode, described active layer, first transparency electrode and described etching barrier layer are for adopting a composition technology and a doping process formed, and the doped region of described active layer is identical with the material of described first transparency electrode;
Be arranged at source, drain electrode on the described active layer, be provided with the transparent conductive material with the second follow-up transparency electrode same material between described active layer and described source, the drain electrode, and described source, drain electrode are connected with the doped region of described active layer by described transparent conductive material.
Described array base palte also comprises:
Be arranged at the resilient coating between described substrate and the described active layer.
Described array base palte also comprises:
Be arranged at the gate insulation layer on described active layer, etching barrier layer and first transparency electrode.
Described array base palte also comprises:
Be arranged at the grid on the described gate insulation layer, described grid is arranged at the top of described active layer;
Be arranged at the protective layer on described grid and the described gate insulation layer;
Be arranged at the top of described active layer, corresponding to the source electrode of follow-up formation and the via hole of drain electrode, described source, drain electrode are electrically connected with the doped region of described active layer by described via hole;
Be arranged at second transparency electrode on the described protective layer, described second transparency electrode is the slit-shaped electrode.
The thickness of described second transparency electrode is in the scope of 30nm to 50nm.
The thickness of described active layer and described first transparency electrode is in the scope of 30nm to 50nm, and the thickness of described etching barrier layer is in the scope of 100nm to 200nm.
The utility model embodiment also provides a kind of display unit, comprises the array base palte with above-mentioned arbitrary feature.
The array base palte that the utility model embodiment provides and display unit; array base palte comprises substrate; be arranged at the active layer on the substrate; first transparency electrode; and on the active layer; for the protection of follow-up source; the etching barrier layer in the active layer zone between the drain electrode; active layer; first transparency electrode and etching barrier layer are for adopting a composition technology and a doping process formed; the doped region of active layer is identical with the material of first transparency electrode; be arranged at the source on the active layer; drain electrode; active layer and source; be provided with the transparent conductive material with the second follow-up transparency electrode same material between the drain electrode, and the source; drain electrode is connected with the doped region of active layer by transparent conductive material.By this scheme, because active layer, first transparency electrode and etching barrier layer are for adopting a composition technology and a doping process formed, compared with prior art reduced the number of times of making the required composition technology of array base palte, shorten the time of research and development and scale of mass production, reduced cost of manufacture.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The structural representation one of the array base palte that Fig. 1 provides for the utility model embodiment;
The manufacture method flow chart one of the array base palte that Fig. 2 provides for the utility model embodiment;
The structural representation two of the array base palte that Fig. 3 provides for the utility model embodiment;
The manufacture method flowchart 2 of the array base palte that Fig. 4 provides for the utility model embodiment;
The structural representation three of the array base palte that Fig. 5 provides for the utility model embodiment;
The structural representation four of the array base palte that Fig. 6 provides for the utility model embodiment;
The structural representation five of the array base palte that Fig. 7 provides for the utility model embodiment;
The structural representation six of the array base palte that Fig. 8 provides for the utility model embodiment;
The structural representation seven of the array base palte that Fig. 9 provides for the utility model embodiment;
The structural representation eight of the array base palte that Figure 10 provides for the utility model embodiment;
The structural representation nine of the array base palte that Figure 11 provides for the utility model embodiment;
The structural representation ten of the array base palte that Figure 12 provides for the utility model embodiment;
The manufacture method flow chart 3 of the array base palte that Figure 13 provides for the utility model embodiment;
The structural representation 11 of the array base palte that Figure 14 provides for the utility model embodiment;
The structural representation 12 of the array base palte that Figure 15 provides for the utility model embodiment;
The structural representation 13 of the array base palte that Figure 16 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Need to prove: of the present invention " on " just the present invention will be described with reference to the accompanying drawings for D score, not as limiting term.
The embodiment of the invention provides a kind of array base palte, comprising:
Substrate;
Be arranged at active layer, first transparency electrode on the described substrate, and on the described active layer, for the protection of the etching barrier layer in active layer zone between follow-up source, the drain electrode, described active layer, first transparency electrode and described etching barrier layer are for adopting a composition technology and a doping process formed, and the doped region of described active layer is identical with the material of described first transparency electrode;
Be arranged at source, drain electrode on the described active layer, be provided with the transparent conductive material with the second follow-up transparency electrode same material between described active layer and described source, the drain electrode, and described source, drain electrode are connected with the doped region of described active layer by described transparent conductive material.
The embodiment of the invention provides a kind of array base palte 1, as shown in Figure 1, comprising:
Be arranged at the resilient coating 101 on the described substrate 100;
Be arranged at active layer 102 and first transparency electrode 103 on the described cache layer 101;
Be arranged at the etching barrier layer 108 on the described active layer 102, described etching barrier layer 108 is corresponding on the described active layer 102, for the protection of the active layer zone between follow-up source, the drain electrode;
Be arranged at the gate insulation layer 109 on described active layer 102, etching barrier layer 108 and first transparency electrode 103;
Be arranged at the grid 110 on the described gate insulation layer 109, described grid 110 is arranged at the top of described active layer 102;
Be arranged at the protective layer 111 on described grid 110 and the described gate insulation layer 109;
Be arranged at the top of described active layer 102, corresponding to the source electrode 116 of follow-up formation and 117 the via hole 112 of draining, described source, drain electrode are electrically connected with the doped region of described active layer by described via hole;
Be arranged at source electrode 116 and drain electrode 117 in the described via hole 112, and be arranged at second transparency electrode 118 on the described protective layer 111, described second transparency electrode 118 is the slit-shaped electrode.
In the present embodiment, be public electrode with the one the first transparency electrodes, the two the first transparency electrodes are that second transparency electrode is that example describes.
On substrate, optionally form resilient coating, for avoiding the impurity effect active layer in the glass substrate, preferably form resilient coating at substrate in the present embodiment.
Further, the thickness of described second transparency electrode is in the scope of 30nm to 50nm.
Further, the thickness of described active layer and described first transparency electrode is in the scope of 30nm to 50nm, and the thickness of described etching barrier layer is in the scope of 100nm to 200nm.
The array base palte that the embodiment of the invention provides; comprise substrate; be arranged at the active layer on the substrate; first transparency electrode; and on the active layer; source for the protection of follow-up formation; the etching barrier layer in the active layer zone between the drain electrode; active layer; first transparency electrode and etching barrier layer are for adopting a composition technology and a doping process formed; the doped region of active layer is identical with the material of first transparency electrode; be arranged at the source on the active layer; drain electrode; active layer and source; be provided with the transparent conductive material with the second follow-up transparency electrode same material between the drain electrode, and the source; drain electrode is connected with the doped region of active layer by transparent conductive material.By this scheme, because active layer, first transparency electrode and etching barrier layer are for adopting a composition technology and a doping process formed, compared with prior art reduced the number of times of making the required composition technology of TFT, shorten the time of research and development and scale of mass production, reduced cost of manufacture.
The embodiment of the invention provides a kind of manufacture method of array base palte, comprising:
Form oxide semiconductor thin-film and insulation film at substrate;
Adopt a composition technology and a doping process to handle described oxide semiconductor thin-film and insulation film; to form active layer, first transparency electrode; and be formed on the active layer, for the protection of the source of follow-up formation, the etching barrier layer in active layer zone between the drain electrode; wherein, it is identical to form the material of described active layer and described first transparency electrode.
Composition technology of described employing and a doping process are handled described oxide semiconductor thin-film and insulation film; to form active layer, first transparency electrode; and be formed on the active layer, for the protection of the source of follow-up formation, the etching barrier layer in active layer zone between the drain electrode, specifically comprise:
Form first photoresist at described insulation film;
First photoresist is carried out half exposure, form the complete reserve area of first photoresist, the first photoresist part reserve area and first photoresist after developing and remove the zone fully, the complete reserve area of described first photoresist is corresponding on the described active layer, for the protection of the source of follow-up formation, active layer zone between the drain electrode, and the described first photoresist part reserve area is corresponding to described source electrode, drain electrode and described first transparency electrode;
Described first photoresist of etching is removed zone corresponding insulation film and oxide semiconductor thin-film fully;
Remove first photoresist of the described first photoresist part reserve area;
The insulation film of the described first photoresist part reserve area correspondence of etching, the photoresist of the complete reserve area of removal photoresist is to form described etching barrier layer;
Adopt doping process, the oxide semiconductor thin-film of the described first photoresist part reserve area correspondence is separately converted to doped region and first transparency electrode of described active layer.
As shown in Figure 2, the manufacture method of a kind of array base palte that the embodiment of the invention provides, this method comprises:
S101, deposit resilient coating at substrate.
As shown in Figure 3, on through the substrate 100 that cleans in advance, with PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), LPCVD (Low Pressure Chemical Vapor Deposition, low-pressure chemical vapor deposition), APCVD (Atmospheric Pressure Chemical Vapor Deposition, the atmospheric pressure chemical vapour deposition), ECR-CVD (Electron Cyclotron Resonance-Chemical Vapor Deposition, the electron cyclotron resonance chemical vapour deposition (CVD)) or method such as sputter form resilient coating 101, to stop that impurity contained in the substrate 100 diffuses in the active layer, prevent from characteristics such as the threshold voltage of TFT element and leakage current are exerted an influence.
What need to replenish is, the material of resilient coating 101 is silica and/or silicon nitride, and namely resilient coating 101 can be silica, silicon nitride or the lamination of the two of individual layer.
Further, resilient coating 101 thickness can be in the scope of 100nm to 300nm.
What need replenish is, because the content of metal impurities such as aluminium, barium, sodium is higher in traditional alkali glass, the diffusion of metal impurities takes place easily in high-temperature processing technology, and therefore, substrate 101 can be preferably alkali-free glass substrate.
Need to prove, on substrate, optionally form resilient coating, for avoiding the impurity effect active layer in the glass substrate, preferably form resilient coating at substrate in the present embodiment.
S102, form active layer, first transparency electrode at resilient coating, and be formed on the active layer, for the protection of the source of follow-up formation, the etching barrier layer in active layer zone between the drain electrode.
Wherein, it is identical to form the basis material of described active layer and described first transparency electrode.
Exemplary; as shown in Figure 4; form active layer, first transparency electrode at resilient coating, and be formed on the active layer, specifically can comprise S201 to S208 for the protection of the source of follow-up formation, the method for etching barrier layer in active layer zone between the drain electrode:
S201, form oxide semiconductor thin-film at resilient coating.
Wherein, form the basis material of described active layer and described first transparency electrode, namely oxide semiconductor thin-film is specifically as follows IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), In
2O
3(indium oxide), ZnO (zinc oxide) or ITZO (Indium Tin Zinc Oxide, indium tin zinc oxide) etc.
S202, form insulation film at oxide semiconductor thin-film.
As shown in Figure 5, at resilient coating 101 deposition oxide semiconductive thin film and insulation films, the method for deposition non-oxidized substance semiconductive thin film and insulation film can be methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, and the present invention does not limit.
Wherein, the thickness of described oxide semiconductor thin-film can be in the scope of 30nm to 50nm, and the thickness of described insulating layer of thin-film can be in the scope of 100nm to 200nm.
S203, form first photoresist at described insulation film.
S204, first photoresist is carried out half exposure; form the complete reserve area of first photoresist, the first photoresist part reserve area and first photoresist after developing and remove the zone fully; the complete reserve area of described first photoresist corresponding to describedly be formed on the active layer, for the protection of the source of follow-up formation, active layer zone between the drain electrode, the described first photoresist part reserve area is corresponding to source electrode, drain electrode and described first transparency electrode.
As shown in Figure 6, first photoresist that is formed on the insulation film is carried out half exposure, the back of developing forms the complete reserve area 105 of first photoresist, the first photoresist part reserve area 106 and first photoresist and removes zone 107 fully.
S205, described first photoresist of etching are removed zone corresponding insulation film and oxide semiconductor thin-film fully.
Particularly, adopt one time dry etching, described first photoresist of etching is removed the corresponding insulation film in zone fully, adopts one time wet etching, described first photoresist of etching is removed the corresponding oxide semiconductor thin-film in zone fully, to form structure as shown in Figure 7.
First photoresist of S206, the described first photoresist part reserve area of removal.
Particularly, adopt cineration technics, remove first photoresist of the described first photoresist part reserve area, simultaneously, first photoresist of the complete reserve area of described first photoresist is thinned.
The insulation film of S207, the described first photoresist part reserve area correspondence of etching, the photoresist of the complete reserve area of removal photoresist is to form described etching barrier layer.
As shown in Figure 8, adopt one time dry etching, the insulation film of the described first photoresist part reserve area correspondence of etching, the photoresist of the complete reserve area of removal photoresist is to form described etching barrier layer 108.
S208, adopt doping process, the oxide semiconductor thin-film of the described first photoresist part reserve area correspondence is separately converted to doped region and first transparency electrode of described active layer.
Wherein, the method that adopts described doping process to handle described oxide semiconductor thin-film comprises: adopt hydrogen H, aluminium Al, tin Sn or titanium Ti ion, described oxide semiconductor thin-film is handled.
Particularly, S208 can carry out simultaneously with S207, namely when forming etching barrier layer, utilize the plasma of dry etching method, oxide semiconductor thin-film to the described first photoresist part reserve area correspondence carries out doping treatment, the oxide semiconductor thin-film of the described first photoresist part reserve area correspondence is separately converted to doped region and first transparency electrode of described active layer;
Perhaps, S208 also can carry out after S207, at this moment, can utilize independent H plasma the oxide semiconductor thin-film of the described first photoresist part reserve area correspondence to be separately converted to doped region and first transparency electrode of described active layer, the mode that perhaps can utilize ion to inject, select Al, Sn, Ti plasma for use, the oxide semiconductor thin-film of the described first photoresist part reserve area correspondence is separately converted to doped region and first transparency electrode of described active layer.
Wherein, adopting doping process to handle the subregion of active layer, is for when forming source electrode and drain electrode, and this zone can contact with drain electrode well with source electrode, has reduced contact resistance.
S103, form gate insulation layer at the substrate of finishing above-mentioned technology.
As shown in Figure 9, adopt methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, form gate insulation layer 109 at the substrate of finishing above-mentioned technology.
Wherein, the thickness of gate insulation layer 109 can carry out adaptive change according to the specific design of array base palte, and preferably, the thickness of gate insulation layer 109 can be in the scope of 50nm to 200nm.The material of gate insulation layer 109 can be silica and/or silicon nitride, and namely gate insulation layer 109 can be silica, silicon nitride or the lamination of the two of individual layer.
S104, form the grid film at described gate insulation layer.
Particularly, adopt methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, form the grid film at described gate insulation layer.The thickness of grid film can be in the scope of 200nm to 300nm.
S105, described grid film of composition PROCESS FOR TREATMENT of employing are to form grid above described active layer.
As shown in figure 10, adopt composition PROCESS FOR TREATMENT grid film after, above corresponding to active layer 102, form grid 110.Wherein, composition technology specifically comprises steps such as photoresist coating, exposure, development, the removal of etching photoresist, etching technics can be dry etching methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, and etching gas can be gas fluorine-containing, chlorine, as CF
4, CHF
3, SF
6, CCl
2F
2Gas also can be above-mentioned gas and O
2Mist.
S106, form protective layer at the substrate of finishing above-mentioned technology.
As shown in figure 11, adopt methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, form protective layer 111 at the substrate of finishing above-mentioned technology.
Wherein, the thickness of protective layer 111 can carry out adaptive change according to the specific design of array base palte, and preferably, the thickness of protective layer 111 can be in the scope of 200nm to 400nm.
S107, adopt a composition technology, form via hole at described active layer above corresponding to source electrode, drain electrode.
As shown in figure 12, after forming protective layer 111, (being that active layer is corresponding to the top of source electrode, drain electrode) forms via hole 112 in gate insulation layer 109 and protective layer 111.The method that forms via hole can be dry etching methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, and etching gas can be gas fluorine-containing, chlorine, as CF
4, CHF
3, SF
6, CCl
2F
2Gas also can be above-mentioned gas and O
2Mist.
S108, form transparent conductive film at the substrate of finishing above-mentioned technology.
Particularly, adopt methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, form described transparent conductive film at the substrate of finishing above-mentioned technology.Wherein, the thickness of described transparent conductive film can be in the scope of 30nm to 50nm.
S109, form metallic film at transparent conductive film.
Particularly, adopt methods such as PECVD, LPCVD, APCVD, ECR-CVD or sputter, form described metallic film at the substrate of finishing above-mentioned technology.Wherein, the thickness of described metallic film is in the scope of 200nm to 300nm.
S110, described transparent conductive film of composition PROCESS FOR TREATMENT of employing and metallic film are to form source electrode, drain electrode and second transparency electrode.
Exemplary, as shown in figure 13, the method that forms source electrode, drain electrode and second transparency electrode specifically can comprise S301 to S305:
S301, form second photoresist at metallic film.
S302, described second photoresist is carried out half exposure, form the complete reserve area of second photoresist, the second photoresist part reserve area and second photoresist after developing and remove the zone fully, the complete reserve area of described second photoresist is corresponding to the zone of the described source electrode of follow-up formation and drain electrode, and the described second photoresist part reserve area is corresponding to the zone of described second transparency electrode of follow-up formation.
As shown in figure 14, second photoresist that is formed on the metallic film is carried out half exposure, the back of developing forms the complete reserve area 113 of second photoresist, the second photoresist part reserve area 114 and second photoresist and removes zone 115 fully.
S303, described second photoresist of etching are removed zone corresponding metallic film and transparent conductive film fully.
Particularly, as shown in figure 15, adopt one time wet etching, corresponding metallic film and the transparent conductive film in described first photoresist of etching zone, complete place to go is to form source electrode 116, drain electrode 117.
Second photoresist of S304, the described second photoresist part reserve area of removal.
Particularly, adopt cineration technics, remove second photoresist of the described second photoresist part reserve area, simultaneously, second photoresist of the complete reserve area of described second photoresist is thinned.
The metallic film of S305, the described second photoresist part reserve area correspondence of etching is to form described second transparency electrode.
As shown in figure 16, adopt one time wet etching, the metallic film of the described second photoresist part reserve area correspondence of etching is to form second transparency electrode 118.
The photoresist of S306, the complete reserve area of removal second photoresist, formation source, drain electrode, described source, drain electrode are by being connected with the doped region of described active layer with the transparent conductive film of the described second transparency electrode same material.
Further, the thickness of described active layer and described first transparency electrode is in the scope of 30nm to 50nm, and the thickness of described etching barrier layer is in the scope of 100nm to 200nm.
Further, the thickness of described second transparency electrode is in the scope of 30nm to 50nm.
The manufacture method of the array base palte that the embodiment of the invention provides; be included in and form oxide semiconductor thin-film and insulation film on the substrate; adopt a composition technology and a doping process to handle described oxide semiconductor thin-film and insulation film; forming active layer, first transparency electrode, and be formed on the active layer, for the protection of the source of follow-up formation, the etching barrier layer in active layer zone between the drain electrode.By this scheme; owing to adopt a composition technology and a doping process to form active layer, first transparency electrode; and be formed on the active layer, for the protection of the source of follow-up formation, the etching barrier layer in active layer zone between the drain electrode; compared with prior art reduced the number of times of making the required composition technology of array base palte; shorten the time of research and development and scale of mass production, reduced cost of manufacture.
The embodiment of the invention provides a kind of display unit, comprises having the described array base palte of above-described embodiment.This display unit can be liquid crystal indicator, comprises the color membrane substrates of opposing parallel setting and the array base palte that above-described embodiment proposes, and is filled in the liquid crystal between color membrane substrates and the array base palte; This display unit also can be the OLED display unit, comprises the array base palte that above-described embodiment proposes, and luminous organic material and the encapsulation cover plate of evaporation on this array base palte.
The liquid crystal indicator that the embodiment of the invention provides, liquid crystal indicator can not limit for product or the present invention of portion that LCD, LCD TV, DPF, mobile phone, panel computer etc. have a Presentation Function.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (7)
1. an array base palte is characterized in that, comprising:
Substrate;
Be arranged at active layer, first transparency electrode on the described substrate, and on the described active layer, for the protection of the etching barrier layer in active layer zone between follow-up source, the drain electrode, described active layer, first transparency electrode and described etching barrier layer are for adopting a composition technology and a doping process formed, and the doped region of described active layer is identical with the material of described first transparency electrode;
Be arranged at source, drain electrode on the described active layer, be provided with the transparent conductive material with the second follow-up transparency electrode same material between described active layer and described source, the drain electrode, and described source, drain electrode are connected with the doped region of described active layer by described transparent conductive material.
2. array base palte according to claim 1 is characterized in that, also comprises:
Be arranged at the resilient coating between described substrate and the described active layer.
3. array base palte according to claim 1 is characterized in that, also comprises:
Be arranged at the gate insulation layer on described active layer, etching barrier layer and first transparency electrode.
4. array base palte according to claim 3 is characterized in that, also comprises:
Be arranged at the grid on the described gate insulation layer, described grid is arranged at the top of described active layer;
Be arranged at the protective layer on described grid and the described gate insulation layer;
Be arranged at the top of described active layer, corresponding to the source electrode of follow-up formation and the via hole of drain electrode, described source, drain electrode are electrically connected with the doped region of described active layer by described via hole;
Be arranged at second transparency electrode on the described protective layer, described second transparency electrode is the slit-shaped electrode.
5. array base palte according to claim 4 is characterized in that, the thickness of described second transparency electrode is in the scope of 30nm to 50nm.
6. according to each described array base palte among the claim 1-5, it is characterized in that the thickness of described active layer and described first transparency electrode is in the scope of 30nm to 50nm, the thickness of described etching barrier layer is in the scope of 100nm to 200nm.
7. a display unit is characterized in that, comprises as each described array base palte among the claim 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320228616 CN203179888U (en) | 2013-04-28 | 2013-04-28 | Array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320228616 CN203179888U (en) | 2013-04-28 | 2013-04-28 | Array substrate and display device |
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| CN203179888U true CN203179888U (en) | 2013-09-04 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258827A (en) * | 2013-04-28 | 2013-08-21 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device of array substrate |
| WO2015081650A1 (en) * | 2013-12-02 | 2015-06-11 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, and preparation method and display device thereof |
-
2013
- 2013-04-28 CN CN 201320228616 patent/CN203179888U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103258827A (en) * | 2013-04-28 | 2013-08-21 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device of array substrate |
| WO2014176877A1 (en) * | 2013-04-28 | 2014-11-06 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, and display device comprising array substrate |
| CN103258827B (en) * | 2013-04-28 | 2016-03-23 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display unit |
| US9698165B2 (en) | 2013-04-28 | 2017-07-04 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same, and display device comprising array substrate |
| WO2015081650A1 (en) * | 2013-12-02 | 2015-06-11 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate, and preparation method and display device thereof |
| US9502436B2 (en) | 2013-12-02 | 2016-11-22 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and method for fabricating the same, and display device |
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