CN203179883U - Circuit packaging structure - Google Patents
Circuit packaging structure Download PDFInfo
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- CN203179883U CN203179883U CN 201320097406 CN201320097406U CN203179883U CN 203179883 U CN203179883 U CN 203179883U CN 201320097406 CN201320097406 CN 201320097406 CN 201320097406 U CN201320097406 U CN 201320097406U CN 203179883 U CN203179883 U CN 203179883U
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- package structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Abstract
A circuit packaging structure comprises the following components: a substrate, a first chip and a second chip; wherein the substrate is provided with a first dent tank and a second dent tank. The first dent tank is provided with a recess opening part and a first platform part. The second dent tank is provided with a second platform part. The bottoms of the two dent tanks are provided with chip configuration areas for configuring a first chip and a second chip. The groove and the platform are provided with a plurality of electrical connecting ends. Additionally metal leads are provided for electrically connecting the chips with a plurality of electric connecting ends, so that little time and cost are consumed for packaging in packaging process.
Description
Technical field
The utility model relates to a kind of circuit package structure, particularly a kind of circuit package structure with Photoinduction device and luminescence component.
Background technology
In semiconductor packages, if two different chips (as: luminescence component and a light sensing component) are configured to same substrate, can form multiple different encapsulating structure (as: Photoinduction device).During light path as between object blocking luminescence component and optical sensing subassembly, optical sensing subassembly just can be judged the existence of object, otherwise if optical sensing subassembly can receive the light of luminescence component emission smoothly, optical sensing subassembly can judge that just object does not exist.Whether the reflecting light induction installation is luminescence component and optical sensing subassembly is installed on the same side, against whether object being arranged with the light reflected light sensing component of luminescence component, exist to judge object.
Accuracy in order to ensure Photoinduction device; in general known technology; can add a plurality of assemblies at encapsulating structure; guarantee that luminescence component whole flow process luminous and the optical sensing subassembly sensing can not be subjected to extraneous interference; thus; the technology of Photoinduction device usually can be very complicated, and semiconductor industry is being pursued always product size is dwindled, and therefore complicated structure and assembly all can cause Production Time and cost to increase.
The utility model content
The purpose of this utility model is to provide a kind of circuit package structure, by the design to structure and technology, makes when making, and can finish circuit package with less step.
For achieving the above object, the circuit package structure that the utility model provides comprises:
One substrate has one first and reaches one second relative with this first, has one first groove and one second groove on this first, isolates mutually with a barricade between this first groove and this second groove, and wherein this circuit package structure is characterised in that:
This first groove comprises:
One first chip configuration district is arranged in this first groove, and disposes one first metallic contact on the bottom of this first groove;
One notch portion, disposed adjacent are by this first chip configuration district, and this notch portion has one first platform part that is higher than this first chip configuration district; And
One first electricity connection end is disposed on this first platform part, and one first pad is arranged;
This second groove comprises:
One second chip configuration district is arranged in this second groove;
One second platform part be disposed at the periphery in this second chip configuration district, and this second platform part is higher than this second chip configuration district;
A plurality of second electricity connection ends are disposed on this second platform part, and each those electricity connection end all has one second pad;
One first chip, have one first upper end and one first lower end, and respectively at configuration one first weld pad and one second weld pad on this first upper end and this first lower end, this first chip electrically connects via this first metallic contact in this second weld pad and this first chip configuration district, and first weld pad of this first chip is via this first first pad electric connection that electrically connects on the point of one first plain conductor and this notch portion;
One second chip, have one second upper end and one second lower end, this second chip is fixed in this second chip configuration district via this second lower end, and this second upper end of this second chip disposes a plurality of the 3rd weld pads, and those the 3rd weld pads electrically connect via those second electricity connection ends on a plurality of second plain conductors and this second platform part; And
A plurality of outside connection end points, be disposed on this second of this substrate, and each should the outside connection end point be through to metal material in this through hole of first and those second pads on those second electricity connection ends in this first metallic contact in this first groove and this first electricity connection end and this second groove electrically connect via a plurality of by this second face.
Described circuit package structure wherein disposes one first transparent adhesive layer in this first groove, and this first chip, this first plain conductor, this first electricity connection end and this first pad are covered.
Described circuit package structure, wherein this first transparent adhesive layer top has an opaque adhesive layer, and this opaque adhesive layer also leaves an irradiation hole in the relevant position of this first chip.
Described circuit package structure wherein disposes one second transparent adhesive layer in this second groove, and this second chip, those second plain conductors and those second electricity connection ends are covered.
Described circuit package structure, wherein this second transparent adhesive layer top has an opaque adhesive layer, and this opaque adhesive layer also leaves a receiver hole in the relevant position of this second chip.
Described circuit package structure, wherein this first transparent adhesive layer and this second transparent adhesive layer are transparent epoxy resin.
Described circuit package structure, wherein this circuit package structure has one first diffuser, be positioned at this first chip top, and this first diffuser has a transmittance section.
Described circuit package structure, wherein this transmittance section is lens or diffusion mould.
Described circuit package structure, wherein this circuit package structure has one second diffuser, be positioned at this second chip top, and this second diffuser has a light receiver.
Described circuit package structure, wherein this light receiver is lens.
Described circuit package structure, wherein outermost in those outside connection end points should have a breach by the outside connection end point.
The circuit package structure that the utility model provides also comprises:
One substrate has one first and reaches one second relative with this first, has one first groove and one second groove on this first, isolates mutually with a barricade between this first groove and this second groove, and wherein this circuit package structure is characterised in that:
This first groove comprises:
One first chip configuration district is arranged in this first groove;
One first notch portion, disposed adjacent are by this first chip configuration district, and this first notch portion has one first platform part that is higher than this first chip configuration district;
One first electricity connection end is disposed on this first platform part, and one first pad is arranged;
One second notch portion, disposed adjacent is other and relative with this first notch portion in this first chip configuration district, and this second notch portion has one second platform part that is higher than this first chip configuration district; And
One second electricity connection end is disposed on this second platform part, and one second pad is arranged;
This second groove comprises:
One second chip configuration district is arranged in this second groove;
One the 3rd platform part be disposed at the periphery in this second chip configuration district, and the 3rd platform part is higher than this second chip configuration district;
A plurality of the 3rd electricity connection ends are disposed on the 3rd platform part, and each those the 3rd electricity connection end all has one the 3rd pad;
One first chip, have one first upper end and one first lower end, this first chip is fixed in this first chip configuration district by this first lower end, and have a plurality of first weld pads in this first upper end, this first chip electrically connects via this second pad on this second electricity connection end of this first pad on this first electricity connection end of those first weld pads and this first notch portion and this second notch portion;
One second chip, have one second upper end and one second lower end, this second chip is fixed in this second chip configuration district via this second lower end, and this second upper end of this second chip disposes a plurality of second weld pads, and those second weld pads electrically connect via those the 3rd pads on those the 3rd electricity connection ends on a plurality of second plain conductors and this second platform part; And
A plurality of outside connection end points, be disposed on this second of this substrate, and each should electrically connect via those the 3rd electricity connection ends in this first electricity connection end in the metal material in a plurality of through holes and this first groove and this second electricity connection end and this second groove by the outside connection end point.
The circuit package structure that the utility model provides forms board structure by the mode with ejection formation, and carves the position of a plurality of weld pads with laser, cost and the time that just can effectively reduce the circuit package reality, further can improve the reliability of product.
Description of drawings
Fig. 1 is substrate schematic top plan view of the present utility model;
Fig. 2 is the utility model circuit package structure schematic top plan view;
Fig. 3 is the utility model circuit package structure cross-sectional schematic;
Fig. 4 is the utility model circuit package structure elevational schematic view;
Fig. 5 is the utility model circuit package structure second embodiment schematic top plan view;
Fig. 6 is the utility model circuit package structure the 3rd embodiment schematic top plan view;
Fig. 7 is that the utility model circuit package structure the 4th embodiment encapsulates the back schematic top plan view;
Fig. 8 the utility model circuit package structure the 5th embodiment cross-sectional schematic.
Label symbol explanation in the accompanying drawing:
11, the first 11a of substrate, second 11b;
First groove, 12, the first chip configuration districts, 122, the first metallic contacts, 1220, the first electricity connection ends, 124, the first pads 1240, notch portion 126, the first platform part 1260, through hole 1280, metal material 1282;
Barricade 13;
Second groove, 14, the second platform part, 140, the second chip configuration districts, 142, the second electricity connection ends, 144, the second pads 1440, through hole 1480, metal material 1482;
Opaque adhesive layer 15, the first diffusers 151, transmittance section 1510, the second diffusers 152, light receiver 1520;
160, the first lower ends, first chip, 16, the first upper ends, 162, the first weld pads, 164, the second weld pads 166, irradiation hole 168;
Outside connection end point 17, breach 172;
180, the second lower ends, second chip, 18, the second upper ends, 182, the three weld pads 184, receiver hole 188;
21, the first 21a of substrate;
First groove, 22, the first chip configuration districts, 222, the first electricity connection ends, 224, the first pads, 2240, the second electricity connection ends, 225, the second pads, 2250, the first notch portion, 226, the first platform part, 2260, the second notch portion, 227, the second platform part 2270;
Second groove, 24, the three platform part, 240, the second chip configuration districts, 242, the three electricity connection ends, 244, the three pads 2440;
Opaque adhesive layer 25;
First chip, 26, the first upper ends, 260, the first weld pads, 264, the second weld pads 266, irradiation hole 268;
Second chip, 28, the second upper ends, 280, the three weld pads 284, receiver hole 288;
Online XX '.
Embodiment
A kind of circuit package structure that the utility model proposes, comprise: a substrate, have one first and reach one second relative with first, on first, have one first groove and one second groove, isolate mutually with a barricade between first groove and second groove, wherein the circuit package structure is characterised in that: first groove comprises: one first chip configuration district is arranged in first groove, and disposes one first metallic contact on the bottom of first groove; One notch portion, disposed adjacent are by the first chip configuration district, and notch portion has one first platform part that is higher than the first chip configuration district; And one first electricity connection end, be disposed on first platform part, and one first pad is arranged; Second groove comprises: one second chip configuration district is arranged in second groove; One second platform part be disposed at the periphery in the second chip configuration district, and second platform part is higher than the second chip configuration district; A plurality of second electricity connection ends are disposed on second platform part, and each electricity connection end all has one second pad; One first chip, have one first upper end and one first lower end, and respectively at configuration one first weld pad and one second weld pad on first upper end and first lower end, first chip electrically connects via first metallic contact in second weld pad and the first chip configuration district, and first weld pad of first chip electrically connects via first pad on the first electric connection point of one first plain conductor and notch portion; One second chip, have one second upper end and one second lower end, second chip is fixed in the second chip configuration district via second lower end, and second upper end of second chip disposes a plurality of the 3rd weld pads, and the 3rd weld pad electrically connects via second electricity connection end on a plurality of second plain conductors and second platform part; And a plurality of outside connection end points, be disposed on second of substrate, and each outside connection end point electrically connects via a plurality of metal material and second pads on second electricity connection end in first metallic contact in first groove and first electricity connection end and second groove that are through to by second face in first the through hole.
The utility model also proposes a kind of circuit package structure, comprise: a substrate, have one first and reach one second relative with first, on first, have one first groove and one second groove, isolate mutually with a barricade between first groove and second groove, wherein the circuit package structure is characterised in that: first groove comprises: one first chip configuration district is arranged in first groove; One first notch portion, disposed adjacent are by the first chip configuration district, and first notch portion has one first platform part that is higher than the first chip configuration district; One first electricity connection end is disposed on first platform part, and one first pad is arranged; One second notch portion, disposed adjacent are other and relative with first notch portion in the first chip configuration district, and second notch portion has one second platform part that is higher than the first chip configuration district; And one second electricity connection end, be disposed on second platform part, and one second pad is arranged; Second groove comprises: one second chip is put configuring area, is arranged in second groove; One the 3rd platform part be disposed at the periphery in the second chip configuration district, and the 3rd platform part is higher than the second chip configuration district; A plurality of the 3rd electricity connection ends are disposed on the 3rd platform part, and each the 3rd electricity connection end all has one the 3rd pad; One first chip, have one first upper end and one first lower end, first chip is fixed in the first chip configuration district by first lower end, and have a plurality of first weld pads in first upper end, first chip electrically connects via second pad on second electricity connection end of first pad on first electricity connection end of first weld pad and first notch portion and second notch portion; One second chip, have one second upper end and one second lower end, second chip is fixed in the second chip configuration district via second lower end, and second upper end of second chip disposes a plurality of second weld pads, and second weld pad electrically connects via the 3rd pad on the 3rd electricity connection end on a plurality of second plain conductors and second platform part; And a plurality of outside connection end points, be disposed on second of substrate, and each outside connection end point electrically connects via the 3rd electricity connection end in first electricity connection end in the metal material in a plurality of through holes and first groove and second electricity connection end and second groove.
The circuit package structure that is proposed by the utility model, owing to substrate and structure thereof can be made in addition in advance, make semiconductor factory only need chip configuration just can be finished packaging technology in substrate, significantly reduce the required time of encapsulation, further reduced the reliability that encapsulates required cost and improved the encapsulation finished product.
Circuit package structure of the present utility model, particularly a kind of structure that packaging technology is simplified further can reduce time and cost required when encapsulating, and carries out the required technology of packaging technology for known, so in following explanation, and need imperfect description.In addition, accompanying drawing in the literary composition in following, not according to the actual complete drafting of relative dimensions, its effect is only being expressed the schematic diagram relevant with the utility model feature.
At first, please consult Fig. 1 earlier, be substrate schematic top plan view of the present utility model.As shown in Figure 1, substrate 11 is made of macromolecular material, has one first 11a, has on first 11a between one first groove 12 and one second groove, 14, the first grooves 12 and second groove 14 to isolate mutually with a barricade 13; Wherein, one first chip configuration district 122 is arranged at first groove, 12 bottoms, dispose one first metallic contact 1220 in the first chip configuration district 122, there is a notch portion 126 on 122 sides, the first chip configuration district, notch portion 126 has one than on high first platform part, 1260, the first platform part 1260 in the first chip configuration district 122 and one first electricity connection end 124 arranged; Simultaneously, one second chip configuration district 142 is arranged at second groove, 14 bottoms, form one second platform part 140 around the second chip configuration district 142, and second platform part 140 is higher than the second chip configuration district 142, second platform part 140 disposes a plurality of second electricity connection end, 144, the second electricity connection ends 144 and centers on the second chip configuration district 142.In embodiment of the present utility model, substrate 11 is made of in the injection molding mode macromolecular material, and right the utility model is the generation type of restricting substrate 11 in addition not; Simultaneously, first metallic contact 1220 on the substrate 11 and the generation type of a plurality of second electricity connection ends 144 will elaborate in the back.
Then, please consult Fig. 2 and Fig. 3 simultaneously, be respectively the utility model circuit package structure schematic top plan view and the utility model circuit package structure cross-sectional schematic, wherein, the online XX ' at Fig. 3 two ends, corresponding diagram 2 online XX '.As shown in Figures 2 and 3, circuit package structure 1 of the present utility model, for in the first chip configuration district 122 of aforesaid substrate 11, dispose first chip 16, first chip 16 has first upper end 160 and the first relative lower end 162, there is first weld pad 164 first upper end 160, there is one second weld pad 166 first lower end 162, wherein, the end of first weld pad 164 and a plain conductor 19a electrically connects, first pad 1240 on the other end of plain conductor 19a and first electricity connection end 124 electrically connects, and first metallic contact 1220 in second weld pad 166 and the first chip configuration district 122 electrically connects.Then, provide second chip 18, this second chip 18 has on second upper end 180 and relative 182, the second upper ends 180, second lower end and is formed with a plurality of the 3rd weld pads 184; Then, will be fixed in the second chip configuration district 142 with an adhesion layer (not being shown among the figure) in second lower end 182 of second chip 18; Follow again, each the 3rd weld pad 184 all electrically connected with the end of a plain conductor 19b, the other end of plain conductor 19b all respectively with second electricity connection end 144 on second pad 1440 electrically connect.Be stressed that, in the present embodiment, plain conductor 19a and plain conductor 19b form with routing technology (wirebonding), order as for routing technology, for example, be after second weld pad 166 of first chip 16 and first metallic contact, 1220 electric connections in the first chip configuration district 122, namely carry out the routing first time, then, after second lower end 182 for the treatment of second chip 18 is fixed in the second chip configuration district 142, again with the second time routing with many strip metals lead 19b second pad 1440 on each the 3rd weld pad 184 and second electricity connection end 144 is electrically connected; Or, treat that first chip 16 and second chip 18 all are disposed in the first chip configuration district 122 and the second chip configuration district 142, once finish the electric connection of plain conductor 19a and many strip metals lead 19b again with routing technology; For the order of above-mentioned routing technology, the utility model is not limited.
Then, please consult Fig. 3 and Fig. 4 simultaneously, Fig. 4 is the utility model circuit package structure elevational schematic view.As shown in Figure 4, substrate 11 have one with first second 11b that 11a is relative, dispose a plurality of outside connection end points 17 on second 11b, one of them is positioned on the outside connection end point 17 in the outside a breach 172, with as the identification pin; As shown in Figure 3, a plurality of through holes 1280,1480 are arranged on the substrate 11, there is metal material 1282,1482 through hole 1280,1480 inside, wherein, first metallic contact 1220 and first electricity connection end 124 electrically connect with outside tie point 17 by through hole 1280 and metal material 1282, simultaneously, each second electricity connection end 144 electrically connects with outside link 17 by through hole 1480 and metal material 1482 respectively.
Then, see also Fig. 5, be the utility model circuit package structure second embodiment schematic top plan view.As shown in Figure 5, first groove, 12 configurations, the first transparent adhesive layer (not being shown among the figure) of circuit package structure 1 ', first chip 16, plain conductor 19a, first electricity connection end 124 and first pad 1240 are covered, and the configuration second transparent adhesive layer (not being shown among the figure) covers second chip 18, plain conductor 19b, second electricity connection end 144 and second pad 1440 in second groove 14; Wherein, the first transparent adhesive layer (not being shown among the figure) and the second transparent adhesive layer (not being shown among the figure) are transparent epoxy resin; The first transparent adhesive layer (not being shown among the figure) and the second transparent adhesive layer (not being shown among the figure) top scribble opaque adhesive layer 15, and leave irradiation hole 168 and receiver hole 188 respectively in the relevant position of first chip 16 and second chip 18, wherein, opaque adhesive layer 15 is black epoxy.
Above-mentioned circuit package structure 1 and circuit package structure 1 ', its formation method is as described below, earlier with injection molding with macromolecular material form as shown in Figure 1 comprise first groove 12, second groove 14, notch portion 126, first platform part 1260 and second platform part, 140 isostructural substrates 11, then, undercut the allocation position of first metallic contact 1220, first electricity connection end 124 and second electricity connection end 144 at substrate 11 with laser; Then, carry out the engraving second time with laser at second 11b of substrate 11 again, form the outside electrically allocation position of tie point 17; Follow again, carve for the third time with laser, between the interface sites of first metallic contact 1220, first electricity connection end 124 and second electricity connection end 144 and outside electrically tie point 17, form a plurality of through holes 1280,1480 (shown in the dotted line among Fig. 1), form metal material 1282,1482 in first metallic contact 1220, first electricity connection end 124, second electricity connection end 144, outside electrically tie point 17 and the through hole 1280,1480 with plating mode then; The substrate 11 of circuit package structure 1 and the structure of metal line have so just been finished.
After having finished the structure as the described substrate 11 of epimere and metal line, first chip 16 and second chip 18 are configured to respectively in first groove 12 and second groove 14, stamp plain conductor 19a and 19b by routing technology again, finish the electrically connect between first chip 16, second chip 18 and first substrate 11, just can finish circuit package structure 1 as shown in Figure 3, in preamble, describe as for the detailed situation that connects, so repeat no more; At last, in first groove 12 and second groove 14, fill transparent epoxy resin in a glue mode, coat opaque paint again, just can finish circuit package structure 1 ' as shown in Figure 5.
In the above-described embodiments, first chip 16 is the light-emitting diode of upper/lower electrode, for example: red light-emitting diode (Red-LED) or infrared light light-emitting diode (IR-LED); Yet the utility model also can use light-emitting diode (as: blue light, green light LED) with lateral electrode as first chip 16, and detailed construction is as described below.
See also Fig. 6, be the utility model circuit package structure the 3rd embodiment schematic top plan view.As shown in Figure 6, substrate 21 has one first 21a, has on first 21a between one first groove 22 and one second groove, 24, the first grooves 22 and second groove 24 to isolate mutually with a barricade 23.Wherein, one first chip configuration district 222 is arranged at first groove, 22 bottoms, there is one first notch portion 226 on 222 sides, the first chip configuration district, first notch portion 226 has first platform part 2260 high than the first chip configuration district 222, on first platform part 2260 and one first electricity connection end 224 arranged, there is one second notch portion 227 on 222 sides, the first chip configuration district, second notch portion 227 is relative with first notch portion 226, second notch portion 227 has one than on high second platform part, 2270, the second platform part 2270 in the first chip configuration district 222 and one second electricity connection end 225 arranged; One second chip configuration district 242 is arranged at second groove, 24 bottoms, form one the 3rd platform part 240 around the second chip configuration district 242, and the 3rd platform part 240 is higher than the second chip configuration district 242, second platform part 240 disposes a plurality of the 3rd electricity connection end 244, the three electricity connection ends 244 and centers on the second chip configuration district 242.
In the first chip configuration district 222 of substrate 21, dispose first chip 26, first chip 26 has one first upper end 260 and relative first lower end (not being shown among the figure), there are one first weld pad 264 and one second weld pad 266 in first upper end 260, first lower end (not being shown among the figure) is fixed in the first chip configuration district 222 with an adhesion layer (not being shown among the figure), wherein, first weld pad 264 and second weld pad 266 respectively with plain conductor 29a, the end of 29c electrically connects, one first pad 2240 on the other end of plain conductor 29a and first electricity connection end 224 electrically connects, and one second pad 2250 on the other end of plain conductor 29c and second electricity connection end 225 electrically connects; In the second chip configuration district 242, dispose second chip 28, second chip 28 has one second upper end 280 and relative second lower end (not being shown among the figure), a plurality of the 3rd weld pads 284 are arranged on second upper end 280, each the 3rd weld pad 284 all electrically connects with the end of a plain conductor 29b, the other end of plain conductor 29b all respectively with the 3rd electricity connection end 244 on the 3rd pad 2440 electrically connect, second lower end (not being shown among the figure) is fixed in the second chip configuration district 242 with an adhesion layer (not being shown among the figure); Generalized section and Fig. 3 as for circuit package structure 2 are similar, and elevational schematic view and Fig. 4 of circuit package structure 2 are similar simultaneously, so repeat no more.
Follow again, see also Fig. 7, be the utility model circuit package structure the 4th embodiment schematic top plan view.As shown in Figure 7, first groove, 22 configurations, the first transparent adhesive layer (not being shown among the figure) of circuit package structure 2 ' covers first chip 26, plain conductor 29a, 29c, first electricity connection end 224, second electricity connection end 225, first pad 2240 and second pad 2250, form the second transparent adhesive layer (not being shown among the figure) at second groove 14 simultaneously, second chip 28, plain conductor 29b, the 3rd electricity connection end 244 and the 3rd pad 2440 are covered; Wherein, the first transparent adhesive layer (not being shown among the figure) and the second transparent adhesive layer (not being shown among the figure) can be transparent epoxy resin; The first transparent adhesive layer (not being shown among the figure) and the second transparent adhesive layer (not being shown among the figure) top scribble opaque adhesive layer 25, and leave irradiation hole 268 and receiver hole 288 respectively in the relevant position of first chip 26 and second chip 28, wherein, opaque adhesive layer 25 is black epoxy.
The making flow process of circuit package structure 2 is as follows; At first, make substrate 21 by injection molding, then, carve the position that respectively electrically connects end points with laser repeatedly, follow again, form with plating mode and respectively electrically connect end points 224,225,244, place first chip 26, second chip 28 and make first chip 26, second chip 28 and substrate 21 finish electric connection in the routing mode, more than form the flow process of circuit package structure 2, similar to the flow process of previous paragraph 0013 described formation circuit package structure 1, so no longer describe in detail.
Follow again, see also Fig. 8, be the utility model circuit package structure the 5th embodiment cross-sectional schematic.As shown in Figure 8, the circuit package structure 1 " have first diffuser 151 and second diffuser 152; First diffuser 151 is positioned at first chip, 16 tops, and disposes a transmittance section 1510 on first diffuser 151, passes this transmittance section 1510 in order to light to be provided; Wherein, when transmittance section 1510 is a convex configuration, namely can be used as the lens (Lens) with spotlight effect, the light that first chip 16 is sent can pass through transmittance section 1510, to produce the effect of optically focused; In addition, when transmittance section 1510 is diffusion barrier (Diffuser) structure on plane, can have the effect with the light diffusion, make light through after having the transmittance section 1510 of diffusion barrier effect, the light that transmittance section 1510 can make first chip 16 send produces the phenomenon of scattering, to increase illuminating area; Second diffuser 152 is positioned at second chip, 18 tops, and a light receiver 1520 is arranged on second diffuser 152, and light receiver 1520 can be a concave structure, when light is injected through second diffuser 152, the phenomenon of focusing can take place, to increase the light sensing efficient of second chip 18; Wherein, first diffuser 151 and second diffuser 152 except irradiation portion 1510 and light receiver 1520 be the transparent material (for example: lens), all the other partly are all transparent materials, to avoid circuit package structure 1 " be subjected to extra light and disturb; After first diffuser 151 and second diffuser 152 can pass through mode moulding such as molding, polishing, place respectively again first chip 16 and second chip 18 on; And the top of first diffuser 151 can be higher than, be equal to or less than the top of first groove 12, and the top of second diffuser 152 can be higher than, be equal to or less than the top of second groove 14; And the utility model is not limited material, technology and the juncture of first diffuser 151 and second diffuser 152; As for circuit package structure 1 " other assemblies and structure all identical with circuit package structure 1, so repeat no more.
The circuit package structure 1,1 ', 1 that the utility model proposes ", 2,2 '; by with substrate 12,22 and structural module; when semiconductor factory is encapsulated; only first chip 16,26, second chip 18,28 need be placed substrate 12,22; form plain conductor 19a, 19b, 29a, 29b, 29c with routing again and just can finish circuit package structure structure 1,1 ', 1 ", 2,2 ', can effectively reduce the required step of packaging technology and time, further reduce cost, also can improve the reliability of encapsulation finished product because of the minimizing of step.
Though the utility model discloses as above with aforesaid preferred embodiment; so it is not in order to limit the utility model; those skilled in the art are not in breaking away from spirit and scope of the present utility model; when can doing a little change and retouching, therefore the protection range of the present utility model content that should be defined with the claim scope of application is as the criterion.
Claims (12)
1. circuit package structure comprises:
One substrate has one first and reaches one second relative with this first, has one first groove and one second groove on this first, isolates mutually with a barricade between this first groove and this second groove, and wherein this circuit package structure is characterised in that:
This first groove comprises:
One first chip configuration district is arranged in this first groove, and disposes one first metallic contact on the bottom of this first groove;
One notch portion, disposed adjacent are by this first chip configuration district, and this notch portion has one first platform part that is higher than this first chip configuration district; And
One first electricity connection end is disposed on this first platform part, and one first pad is arranged;
This second groove comprises:
One second chip configuration district is arranged in this second groove;
One second platform part be disposed at the periphery in this second chip configuration district, and this second platform part is higher than this second chip configuration district;
A plurality of second electricity connection ends are disposed on this second platform part, and each those electricity connection end all has one second pad;
One first chip, have one first upper end and one first lower end, and respectively at configuration one first weld pad and one second weld pad on this first upper end and this first lower end, this first chip electrically connects via this first metallic contact in this second weld pad and this first chip configuration district, and first weld pad of this first chip is via this first first pad electric connection that electrically connects on the point of one first plain conductor and this notch portion;
One second chip, have one second upper end and one second lower end, this second chip is fixed in this second chip configuration district via this second lower end, and this second upper end of this second chip disposes a plurality of the 3rd weld pads, and those the 3rd weld pads electrically connect via those second electricity connection ends on a plurality of second plain conductors and this second platform part; And
A plurality of outside connection end points, be disposed on this second of this substrate, and each should the outside connection end point be through to metal material in this through hole of first and those second pads on those second electricity connection ends in this first metallic contact in this first groove and this first electricity connection end and this second groove electrically connect via a plurality of by this second face.
2. circuit package structure according to claim 1 is characterized in that, wherein disposes one first transparent adhesive layer in this first groove, and this first chip, this first plain conductor, this first electricity connection end and this first pad are covered.
3. circuit package structure according to claim 2 is characterized in that, wherein this first transparent adhesive layer top has an opaque adhesive layer, and this opaque adhesive layer also leaves an irradiation hole in the relevant position of this first chip.
4. circuit package structure according to claim 1 is characterized in that, wherein disposes one second transparent adhesive layer in this second groove, and this second chip, those second plain conductors and those second electricity connection ends are covered.
5. circuit package structure according to claim 4 is characterized in that, wherein this second transparent adhesive layer top has an opaque adhesive layer, and this opaque adhesive layer also leaves a receiver hole in the relevant position of this second chip.
6. according to claim 2 or 4 described circuit package structures, it is characterized in that wherein this first transparent adhesive layer and this second transparent adhesive layer are transparent epoxy resin.
7. circuit package structure according to claim 1 is characterized in that, wherein this circuit package structure has one first diffuser, be positioned at this first chip top, and this first diffuser has a transmittance section.
8. circuit package structure according to claim 7 is characterized in that, wherein this transmittance section is lens or diffusion mould.
9. circuit package structure according to claim 1 is characterized in that, wherein this circuit package structure has one second diffuser, be positioned at this second chip top, and this second diffuser has a light receiver.
10. circuit package structure according to claim 9 is characterized in that, wherein this light receiver is lens.
11. circuit package structure according to claim 1 is characterized in that, wherein outermost in those outside connection end points should have a breach by the outside connection end point.
12. a circuit package structure comprises:
One substrate has one first and reaches one second relative with this first, has one first groove and one second groove on this first, isolates mutually with a barricade between this first groove and this second groove, and wherein this circuit package structure is characterised in that:
This first groove comprises:
One first chip configuration district is arranged in this first groove;
One first notch portion, disposed adjacent are by this first chip configuration district, and this first notch portion has one first platform part that is higher than this first chip configuration district;
One first electricity connection end is disposed on this first platform part, and one first pad is arranged;
One second notch portion, disposed adjacent is other and relative with this first notch portion in this first chip configuration district, and this second notch portion has one second platform part that is higher than this first chip configuration district; And
One second electricity connection end is disposed on this second platform part, and one second pad is arranged;
This second groove comprises:
One second chip configuration district is arranged in this second groove;
One the 3rd platform part be disposed at the periphery in this second chip configuration district, and the 3rd platform part is higher than this second chip configuration district;
A plurality of the 3rd electricity connection ends are disposed on the 3rd platform part, and each those the 3rd electricity connection end all has one the 3rd pad;
One first chip, have one first upper end and one first lower end, this first chip is fixed in this first chip configuration district by this first lower end, and have a plurality of first weld pads in this first upper end, this first chip electrically connects via this second pad on this second electricity connection end of this first pad on this first electricity connection end of those first weld pads and this first notch portion and this second notch portion;
One second chip, have one second upper end and one second lower end, this second chip is fixed in this second chip configuration district via this second lower end, and this second upper end of this second chip disposes a plurality of second weld pads, and those second weld pads electrically connect via those the 3rd pads on those the 3rd electricity connection ends on a plurality of second plain conductors and this second platform part; And
A plurality of outside connection end points, be disposed on this second of this substrate, and each should electrically connect via those the 3rd electricity connection ends in this first electricity connection end in the metal material in a plurality of through holes and this first groove and this second electricity connection end and this second groove by the outside connection end point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320097406 CN203179883U (en) | 2013-03-04 | 2013-03-04 | Circuit packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320097406 CN203179883U (en) | 2013-03-04 | 2013-03-04 | Circuit packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN203179883U true CN203179883U (en) | 2013-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320097406 Expired - Fee Related CN203179883U (en) | 2013-03-04 | 2013-03-04 | Circuit packaging structure |
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| Country | Link |
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| CN (1) | CN203179883U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576543A (en) * | 2013-10-24 | 2015-04-29 | 标准科技股份有限公司 | Module with multiple package component stacks |
-
2013
- 2013-03-04 CN CN 201320097406 patent/CN203179883U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576543A (en) * | 2013-10-24 | 2015-04-29 | 标准科技股份有限公司 | Module with multiple package component stacks |
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