CN203134322U - AMOLED panel gate drive circuit - Google Patents
AMOLED panel gate drive circuit Download PDFInfo
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- CN203134322U CN203134322U CN2012207062698U CN201220706269U CN203134322U CN 203134322 U CN203134322 U CN 203134322U CN 2012207062698 U CN2012207062698 U CN 2012207062698U CN 201220706269 U CN201220706269 U CN 201220706269U CN 203134322 U CN203134322 U CN 203134322U
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Abstract
The utility model provides a partition method and an addressing method of AMOLED panel gate drive and an AMOLED panel gate drive circuit. The object of the utility model is to compress a space occupied by an AMOLED panel gate addressing circuit portion, simplify a line addressing circuit structure, and increase the number of panels cut by a single substrate. The partition method comprises the steps that each pixel line to be addressed is identified and distinguished by an N dimension coordinate; coordinate values of dimensions for identifying different pixel lines are elements of a set of positive integers from 1 to the integer when all the pixel lines are numbered in sequence; a set of the lines with the same coordinate value in the same dimension serves as a partition; and N is a positive integer that is not greater than a prime factor of the number of the pixel lines. The line addressing circuit allows a shift-register circuit with a complicated structure to be substituted by a combinatory logic unit and a decoder unit, so that the circuit scale of line addressing of the AMOLED is reduced effectively, the number of CELLs cut by the single substrate is increased; and meanwhile, due to the reduction of the circuit scale of the gate drive, the probability of defects of products is also reduced.
Description
Technical field
The utility model belongs to the display technique field, the addressing method and the addressing circuit that relate to the matrix type display panel, be specifically related to a kind of active matrix organic light-emitting diode (AMOLED) panel (Active Matrix/Organic Light Emitting Diode, AMOLED) partition method, addressing method and the addressing circuit of row driving.
Background technology
Existing AMOLED panel row drives (Gate Drive) circuit and adopts TFT technology to be produced on the periphery of array (ARRAY) more.As shown in Figure 1, described horizontal drive circuit mainly comprises shift register (Shift register), logical circuit (Logic), level shifting circuit (Level shifter) and digital buffer circuit (Digital buffer) four parts.Described logical circuit is used for adjusting the output of line scan signals, the influence of signal overlap between two adjacent scanning lines avoiding postponing to bring because of line scan signals, the common employing of described logical block or door and the structure of connecting with door are usually used in the existing TFT-LCD horizontal drive circuit; Described shift register is connected with pixel column after connecting logical circuit, level shifting circuit and digital buffer circuit successively, with the corresponding relation of maintenance with pixel column.
Wherein shift register is finished row and is driven addressing under the control of first synchronizing signal (STV) of clock signal (CPV) and sweep trace.Be example to scan a two field picture, the addressing process of existing addressing circuit as shown in Figure 2: step 1, row drives synchronizing signal STV and is input to first order shift register, represents that a frame scan begins; Step 2, shift register are expert at and are carried out carry operation under the common control that drives clock signal C PV and upper level shift register output signal, change the output state of current shift register; Step 3, all shift registers with the mode of step 2 export successively horizontal-drive signal to the last delegation be strobed, thereby realize addressing to all row of AMOLED panel.
Above-mentioned AMOLED panel row of the prior art drives addressing mode following characteristics: 1, realize addressing function by shift register; 2, by (or from top to bottom) order addressing line by line from top to bottom, the concept of no subregion or piece.
Yet the shift-register circuit of using in the prior art is complicated, makes horizontal drive circuit (being distributed in the panel periphery horizontal direction) can take more panel space, influences individual substrate cut panel quantity; Simultaneously, along with the complexity increase of circuit, the difficulty that panel is made also can increase, thereby causes product reliability and produce the yield reduction.
The utility model content
The purpose of this utility model is in order to compress AMOLED panel row addressing circuit part occupation space, simplify row addressing circuit structure, to increase individual substrate cut panel quantity, having proposed subregion, addressing method and circuit thereof that a kind of AMOLED panel row drives.
The technical solution of the utility model is: a kind of AMOLED panel row driving circuit, comprise,
Some groups of logical circuits, level shifting circuit and digital buffer circuits, one group of logical circuit, level shifter and digital buffer circuit are corresponding to a pixel column,
It is characterized in that,
The corresponding combinatorial logic unit of any one pixel column, any one combinatorial logic unit also comprises N input end, each input end of any one combinatorial logic unit is distinguished with each dimension coordinate figure label of the N dimension coordinate of respective rows of pixels, and the input end of described combinatorial logic unit is to the action of output terminal actuating logic and inclusive NAND;
Described combinatorial logic unit by connect successively behind logical circuit, level shifting circuit and the digital buffer circuit be connected with pixel column realize corresponding with pixel column;
Also comprise,
Decoding unit, comprise N group demoder, wherein arbitrary group of demoder comprises an address input end and a plurality of output gating end, described output gating end with the coordinate figure of a certain dimension of pixel column coordinate one by one corresponding sign distinguished, the dimension difference of the pixel column coordinate figure of different demoder correspondences, described output gating terminal number is consistent with the corresponding dimension coordinate maximal value that is used for described decoder identification;
Control module, described control module comprises address output end, and described address output end is connected with described decoding unit and is used for to decoding unit Input Address information, and described control module is used for generating described address information;
Each input end of described combinatorial logic unit is corresponding with the demoder output terminal of corresponding coordinate, and described correspondence comprises the condition that the coordinate figure of the coordinate figure of the identical and combinatorial logic unit input end of the corresponding dimension values of the dimension values that satisfies combinatorial logic unit input end coordinate simultaneously and demoder and demoder is identical.
The beneficial effects of the utility model are: capable addressing circuit of the present utility model makes originally be combined logical block and decoder element of baroque shift-register circuit substitute, and use subregion of the present utility model and addressing method that the drive circuit unit that addressing is used on the panel is reduced, can effectively reduce the circuit scale of panel row addressing, the panel space that compressor circuit takies increases the quantity of individual substrate cut CELL; Dwindling of horizontal drive circuit scale also can be reduced the probability that defective appears in product simultaneously, improves reliability of products and yield, further reaches the purpose that promotes properties of product and reduce cost of products.
Description of drawings
Fig. 1 is existing horizontal drive circuit block diagram;
Fig. 2 is the synoptic diagram of existing capable addressing mode principle of work;
Fig. 3 is the capable subregion synoptic diagram of an embodiment of the present utility model;
Fig. 4 is the addressing circuit block diagram that the row of an embodiment of the present utility model drives;
Fig. 5 is part row and the decoder element corresponding relation synoptic diagram of an embodiment of the present utility model.
Description of reference numerals: controller 1, decoder element 2, demoder 21, demoder output terminal coordinate 22, logical block 3, pixel column 4, pixel column coordinate 41, the first pixel column coordinate 411, the second pixel column coordinate 412, the 3rd pixel column coordinate 413, a are that set, the b of integer 1 to 8 is that whole 1 to 8 manifold is closed, the set of c integer 1 to 12.
Embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
As Fig. 3 and shown in Figure 5, the partition method that the described a kind of AMOLED panel row of present embodiment drives, each pixel column 4 that is addressed is identified in order to distinguish by a N dimension coordinate 41, described each dimension coordinate figure for sign different pixels row 4 is each element of the set of the positive integer of all being numbered with 1 beginning serial number to all pixel columns, wherein the set of the pixel column that the coordinate figure of same dimension is identical is as a subregion, and N is the positive integer that is not more than the prime factor number of number of lines of pixels.
As Fig. 1, Fig. 3, Fig. 4 and shown in Figure 5, the corresponding addressing circuit of partition method that a kind of and described row of present embodiment drives comprises,
Logical circuit, level shifting circuit and digital buffer circuit, one group of logical circuit, level shifting circuit and digital buffer circuit be corresponding to one-row pixels row 4,
Any one pixel column 4 corresponding combinatorial logic unit 3, any one combinatorial logic unit 3 also comprises N input end, each input end of any one combinatorial logic unit is distinguished with each dimension coordinate figure label of the N dimension coordinate 41 of respective rows of pixels 4, and the input end of described combinatorial logic unit is to the action of output terminal actuating logic and inclusive NAND;
Described combinatorial logic unit 3 by connect successively behind logical circuit, level shifting circuit and the digital buffer circuit be connected with pixel column realize corresponding with pixel column;
Also comprise,
Decoding unit 2, comprise N group demoder 21, wherein arbitrary group of demoder 21 comprises an address input end and a plurality of output gating end, described output gating end with the coordinate figure of a certain dimension of pixel column coordinate 41 one by one correspondence identify into demoder output terminal coordinate 22 and distinguished, the dimension difference of the pixel column coordinate figure of different demoder 21 correspondences wherein, described output gating terminal number are not less than the corresponding dimension coordinate maximal value for described decoding unit sign;
Described combinatorial logic unit 3 each input end are corresponding with demoder 21 output terminals of corresponding coordinate, and described correspondence comprises the condition that the coordinate figure of the coordinate figure of identical and combinatorial logic unit 3 input ends of the corresponding dimension values of the dimension values that satisfies combinatorial logic unit 3 input end coordinates simultaneously and demoder 21 and demoder 21 is identical.
The described combinatorial logic unit 3 concrete logical AND gate inclusive NAND doors that pass through are realized.
The described decoding unit 2 concrete demoders and/or code translator and/or shift register of passing through are realized.
The corresponding addressing method of partition method that the described a kind of and described row of present embodiment drives, described control module 1 generates addressing information, described addressing information input decoding unit 2, export to combinatorial logic unit 3 behind 2 pairs of address information decodings of described decoding unit, combinatorial logic unit 3 is according to the corresponding pixel column 4 of information gating of decoding unit 2 outputs;
Described address information comprises the N dimension coordinate information corresponding with N group demoder, and the coordinate information of described a certain dimension is transfused to the one group demoder corresponding with this dimension 21 and is used for the corresponding output gating end of gating corresponding coordinate information.
Exporting to combinatorial logic unit 3 behind 2 pairs of address information decodings of described decoding unit specifically realizes by address bus.
Described control module selectively changes generation and output addressing information in proper order or at random, to realize the addressing to other pixel columns.
As Fig. 3, Fig. 4 and shown in Figure 5, the AMOLED panel of going with pixel behavior 768 is example,
A kind of partition method that drives of going, the value of described coordinate dimensions N for pixel column sign is 3, the one dimension coordinate figure is that a(a is 1 to 8 positive integer set), the two-dimensional coordinate value is that b(b is 1 to 8 positive integer set), D coordinates value is that c(c is 1 to 12 positive integer set).
Figure 3 shows that the pixel column subregion synoptic diagram of present embodiment, one of desirable positive integer of 1 to 8 of one dimension coordinate figure a wherein, identical each pixel column of one dimension coordinate is as a subregion, one dimension coordinate figure such as the pixel column coordinate of the subregion shown in the second pixel column coordinate 412 among Fig. 3 and the 3rd pixel column coordinate 413 is 1, namely the one dimension coordinate figure a=1 of the first pixel column coordinate 411 belongs to same subregion.
As shown in Figure 3, according to the difference of one dimension coordinate figure, described pixel column 768 row are equally divided into 8 subregions, each subregion 96 row; In like manner, according to the difference of two-dimensional coordinate value, described pixel column 768 row are equally divided into 8 subregions, each subregion 96 row; According to the difference of D coordinates value, described pixel column 768 row are equally divided into 12 subregions, each subregion 64 row.Find that easily described arbitrary pixel column all belongs to three subregions simultaneously.
Will be understood by those skilled in the art that above-mentioned partition method only is the specific embodiment of enumerating for the ease of understanding principle of the present utility model, according to the technical solution of the utility model, described partition method is not limited to this specific embodiment.Each pixel column of panel such as pixel behavior 768 row can also be distinguished by a four-dimensional coordinate; Also can be three-dimensional coordinate: wherein, a gets and is not more than the set of 16 positive integer, and b gets the set that is not more than 8 positive integer, and c gets the set that is not more than 6 positive integer; Described partition method can be that average mark is accompanied pixel column, can not be average mark also.
A group addressing signal that is applied to above-described embodiment comprises three road signal SCANi, SCANj and SCAN k, and described three road signals are cyclic pulse signal, and the cycle of SCANi is that 16.667ms is identical with the frame period, and pulse width is 2083.3us, SCANi
1-0To SCAN i
1-7Postpone 2083.3us successively; The cycle of SCANj is 2083.3us, and pulse width is 260.4us, SCANj
2-0To SCANj
2-7Postpone 260.4us successively; The cycle of SCANk is 260.4us, and pulse width is 21.7us, SCANk
3-0To SCAN k
3-11Postpone 21.7us successively.
Three road signals are exported the AND circuit of address signal to three input respectively, a total 8*8*12=768 combination, and a unique scan line is selected in each combination, thereby realizes the addressing to 768 row.
Those of ordinary skill in the art will appreciate that embodiment described here is in order to help reader understanding's principle of the present utility model, should to be understood that protection domain of the present utility model is not limited to such special statement and embodiment.Those of ordinary skill in the art can make various other various concrete distortion and combinations that do not break away from the utility model essence according to disclosed these technology enlightenments of the utility model, and these distortion and combination are still in protection domain of the present utility model.
Claims (1)
1. an AMOLED panel row driving circuit comprises,
Some groups of logical circuits, level shifting circuit and digital buffer circuits, one group of logical circuit, level shifter and digital buffer circuit are corresponding to a pixel column,
It is characterized in that,
The corresponding combinatorial logic unit of any one pixel column, any one combinatorial logic unit also comprises N input end, each input end of any one combinatorial logic unit is distinguished with each dimension coordinate figure label of the N dimension coordinate of respective rows of pixels, and the input end of described combinatorial logic unit is to the action of output terminal actuating logic and inclusive NAND;
Described combinatorial logic unit by connect successively behind logical circuit, level shifting circuit and the digital buffer circuit be connected with pixel column realize corresponding with pixel column;
Also comprise,
Decoding unit, comprise N group demoder, wherein arbitrary group of demoder comprises an address input end and a plurality of output gating end, described output gating end with the coordinate figure of a certain dimension of pixel column coordinate one by one corresponding sign distinguished, the dimension difference of the pixel column coordinate figure of different demoder correspondences, described output gating terminal number is consistent with the corresponding dimension coordinate maximal value that is used for described decoder identification;
Control module, described control module comprises address output end, and described address output end is connected with described decoding unit and is used for to decoding unit Input Address information, and described control module is used for generating described address information;
Each input end of described combinatorial logic unit is corresponding with the demoder output terminal of corresponding coordinate, and described correspondence comprises the condition that the coordinate figure of the coordinate figure of the identical and combinatorial logic unit input end of the corresponding dimension values of the dimension values that satisfies combinatorial logic unit input end coordinate simultaneously and demoder and demoder is identical.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012207062698U CN203134322U (en) | 2012-12-19 | 2012-12-19 | AMOLED panel gate drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012207062698U CN203134322U (en) | 2012-12-19 | 2012-12-19 | AMOLED panel gate drive circuit |
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| CN203134322U true CN203134322U (en) | 2013-08-14 |
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| CN2012207062698U Expired - Fee Related CN203134322U (en) | 2012-12-19 | 2012-12-19 | AMOLED panel gate drive circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982768A (en) * | 2012-12-19 | 2013-03-20 | 四川虹视显示技术有限公司 | Partition method, addressing method and circuit of gate drive of AMOLED |
| CN103646631A (en) * | 2013-12-25 | 2014-03-19 | 开源集成电路(苏州)有限公司 | Decoder, decoder system and LED (light-emitting diode) display screen control system |
| CN106297639A (en) * | 2016-09-27 | 2017-01-04 | 上海天马微电子有限公司 | Shifting deposit unit and the gate driver circuit comprising it can be cut |
-
2012
- 2012-12-19 CN CN2012207062698U patent/CN203134322U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102982768A (en) * | 2012-12-19 | 2013-03-20 | 四川虹视显示技术有限公司 | Partition method, addressing method and circuit of gate drive of AMOLED |
| CN103646631A (en) * | 2013-12-25 | 2014-03-19 | 开源集成电路(苏州)有限公司 | Decoder, decoder system and LED (light-emitting diode) display screen control system |
| CN106297639A (en) * | 2016-09-27 | 2017-01-04 | 上海天马微电子有限公司 | Shifting deposit unit and the gate driver circuit comprising it can be cut |
| CN106297639B (en) * | 2016-09-27 | 2019-05-21 | 上海天马微电子有限公司 | Cleavable shifting deposit unit and gate driving circuit comprising it |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130814 Termination date: 20201219 |