CN203103292U - Package substrate structure - Google Patents
Package substrate structure Download PDFInfo
- Publication number
- CN203103292U CN203103292U CN 201220710748 CN201220710748U CN203103292U CN 203103292 U CN203103292 U CN 203103292U CN 201220710748 CN201220710748 CN 201220710748 CN 201220710748 U CN201220710748 U CN 201220710748U CN 203103292 U CN203103292 U CN 203103292U
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- China
- Prior art keywords
- dielectric layer
- inductance body
- base plate
- packaging structure
- inductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The utility model discloses a package substrate structure, which has an upper surface and a lower surface, and is characterized by comprising an inductor body arranged between the upper surface and the lower surface, at least one dielectric layer arranged between the upper surface and the lower surface, at least one first connecting pad exposed on the upper surface and electrically connected to one position of the inductor body, and at least two second connecting pads exposed on the upper surface or the lower surface and electrically connected with at least other two different positions of the inductor body.
Description
Technical field
The utility model relates to a kind of base plate for packaging structure, particularly has an available base plate for packaging structure with the modulation inductance value of a plurality of link positions relevant for a kind of.
Background technology
The assembling of the electronics of known technology is that the various electronic component with for example passive component (passive element) utilizes the surface engagement technology (surface mount technology SMT) is attached on substrate or the printed circuit board (PCB).Because electronic component is to expose on the surface of substrate, this causes many problems, for example take the table of joint area of substrate, in addition, the surface engagement passive component is to utilize elements such as tin cream, lead foot, bonding wire electrically to be passed to substrate, and the length of its electrical path is long also to be disturbed HF link easily and produce ghost effect.
Moreover the combination of all kinds of surface engagement passive components can improve the packaging and testing expense, influences the mould stream of sealing (molding) process; Also have the thermal stress that produces because of sealing can cause the warpage of passive component or stick unreliable.So, the flush type passive component (Embedded Passives) of employing is arranged in the known technology, be to utilize multiple-plate inner plating manufacturing process, utilize etching or mode of printing, directly be produced on passive component on the inner plating, after being pressed into multi-layer sheet, scattered (Discrete) passive component that is welded when assembling on the substrate surface be can replace again, active member and wiring thereof given to save substrate surface area.
And flush type, implanted or hide formula passive component technology and be applied in now the Mulitilayer circuit board base plate for packaging structure, just can be in internal layer circuit with the passive component design, but but how can adjust at the needs elasticity of passive component, do not need to change in addition the passive component design, to avoid increasing the cost and the time of testing cost or redesign, be of the present utility model one important research and development design consideration.
So, be necessary to provide a kind of base plate for packaging structure, to solve the existing in prior technology problem.
The utility model content
In view of this, the utility model provides a kind of base plate for packaging structure, to solve the design flexibility and the not high problem of repeated availability of passive component in the existing in prior technology base plate for packaging structure.
Main purpose of the present utility model is to provide a kind of base plate for packaging structure, and it can utilize the internal layer that the passive component inductance is embedded in the multilayer circuit base plate for packaging to reach easily and save substrate surface area and give active member and wiring thereof with it.
Secondary objective of the present utility model is to provide a kind of base plate for packaging structure, selects when it can utilize at least three diverse locations on the inductance body to be external to connection gasket for the active/passive element wire bonds on chip and substrate and the circuit board with control modulation inductance value.
For reaching aforementioned purpose of the present utility model, the utility model one embodiment provides a kind of base plate for packaging structure, have a upper surface and a lower surface, wherein said base plate for packaging structure comprises: at least one dielectric layer, a described inductance body, at least one first connection gasket and at least two second connection gaskets.Described dielectric layer is arranged between described upper surface and the described lower surface.Described inductance body is arranged between described upper surface and the described lower surface.Described first connection gasket is exposed to described upper surface, and electrically connects a position of described inductance body.Described at least two second connection gaskets are exposed to described upper surface or described lower surface, and electrically connect at least two different positions in addition of described inductance body.
Compared with prior art, base plate for packaging structure of the present utility model, so not only can adjust to the required inductance value design flexibility of the electronic component on the circuit board, can also be because do not need to change in addition passive component design, and then reduce the cost and the time of testing cost and redesign.
Description of drawings
Fig. 1 is the perspective view of the utility model one embodiment base plate for packaging structure.
Fig. 2 is the perspective view of another embodiment base plate for packaging structure of the utility model.
Fig. 3 is the perspective view of the another embodiment base plate for packaging structure of the utility model.
Fig. 4 is the application stereogram of the utility model one embodiment base plate for packaging structure.
Fig. 5 is the application side sectional view of another embodiment base plate for packaging structure of the utility model.
Embodiment
For allowing the utility model above-mentioned purpose, feature and advantage become apparent, the utility model preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.Moreover, the direction term that the utility model is mentioned, for example upper and lower, top, the end, front, rear, left and right, inside and outside, side, on every side, central authorities, level, laterally, vertically, vertically, axially, radially, the superiors or orlop etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the utility model, but not in order to restriction the utility model.
Please refer to shown in Figure 1, the base plate for packaging structure of the utility model one embodiment, have a upper surface and a lower surface, mainly comprise: at least one dielectric layer 10a, an inductance body 20a, at least one first connection gasket 30a and at least two second connection gasket 30b (being exposed to described upper surface), 30b ' (being exposed to described lower surface).Described dielectric layer 10a is arranged between described upper surface and the described lower surface.Described inductance body 20a is arranged between described upper surface and the described lower surface.The described first connection gasket 30a is exposed to described upper surface, and electrically connects the position of described inductance body 20a.Described at least two second connection gasket 30b are exposed to described upper surface or described at least two second connection gasket 30b ' are exposed to described lower surface, and electrically connect at least two different positions in addition of described inductance body 20a.The described first connection gasket 30a and one of them described second connection gasket 30b electrically connect the two ends of described inductance body 20a respectively, in simple terms, described connection gasket has three at least, thereby reach the purpose of controllable impedance, at least three connection gaskets can be on the same surface of base plate for packaging structure, also can be respectively on the different surfaces of base plate for packaging structure.
Please refer to shown in Figure 1, embodiment at the utility model one single layer substrate, described dielectric layer 10a is an individual layer dielectric layer, described inductance body 20a is made of an inductance body unit that is positioned at one deck, and described inductance body 20a is spiral helicine to be formed on the outer surface s1 of described individual layer dielectric layer; And the described first connection gasket 30a can directly be formed on the end of described inductance body 20a or be formed on the outer surface s1 of described dielectric layer 10a, if the described first connection gasket 30a is formed directly on the end or a position of described inductance body 20a, the connection pad width of the then described first connection gasket 30a is greater than the line width at all the other inductance positions of described inductance body 20a; If the described first connection gasket 30a is formed on the last part (not illustrating) except that the inductance position of the outer surface s1 of described dielectric layer 10a, it must electrically connect an end or a position of described inductance body 20a by a circuit (trace).Described at least two second connection gasket 30b are if be formed on the outer surface s1 of described dielectric layer 10a, also the connected mode with described first connection gasket 30a and described inductance body 20a is the same, comprises being set directly at the mode that described inductance body 20a went up or be electrically connected to by circuit described inductance body 20a.If described at least two second connection gasket 30b ' are formed on the outer surface s2 of described dielectric layer 10a, then the end by a via (via) 50 electrically connects described inductance body 20a, at this moment, at least two second connection gasket 30b ' both can be set directly at the other end of described via (via) 50, and the outer surface S2 that also can be arranged on described dielectric layer 10a goes up and electrically connect by a circuit other end (not illustrating) of described via 50.
Refer again to Fig. 1, two solder mask 40a, the 40b of described base plate for packaging structure, be covered in described dielectric layer 10a and described inductance body 20a respectively and upward form described upper surface and described lower surface, and described two solder mask 40a, 40b have at least three solder mask perforate 41a, 40b and (do not illustrate, please refer to Fig. 5), with the exposed described first connection gasket 30a and described at least two second connection gasket 30b, 30b '.
In the present embodiment, the material of described dielectric layer 10a can be organic material, fibre strengthening (Fiber-reinforced) organic material or particle strengthening (particle-reinforced) organic material etc. constitute, epoxy resin (Epoxy resin) for example, polyimides (Polyimide), along two rare diacid acid imides of fourth/triazine resin (Bismaleimide Triazine, BT), ABF (Ajinomoto Build-up Film), benzocyclobutene (Benzocyclo-buthene, BCB), FR4, FR5 or aramid fiber (Aramide) etc., and the thickness of described dielectric layer 10a can be between 50 to 80 microns, but is not limited thereto.Described dielectric layer 10a is in order to bearing described inductance body 20a and other electronic component etc.
In the present embodiment; the described inductance body 20a that belongs to passive component is not embedded into the dielectric layer internal layer in base plate for packaging; and be arranged on the outer surface s1 of described dielectric layer 10a, and utilize described solder mask 40a to protect the described first inductance body 20a, the only exposed described first connection gasket 30a.In the present embodiment, the described first connection gasket 30a can be defined by described solder mask perforate 41a and be formed, and/or is defined greater than the line width at all the other inductance positions by design connection pad width and to form.Described inductance body 20a for example can select the surface engagement technology with on the surface that is fixedly held to described dielectric layer 10a, each other can be by one deck adhesion coating gluing in addition; Or can also directly form described inductance body 20a on described dielectric layer 10a with available circuit layer forming technique.For example, when desire forms described inductance body 20a and goes up to described dielectric layer 10a, can be after on the surface of described dielectric layer 10a, by forming such as coating photoresist, exposure imaging, chemical etching or laser reconditioning Patternized techniques such as (Lasser trimming) by coating one deck inductive material.
In the present embodiment, described inductance body 20a can be by forming soft magnetic film spiral coil on the surface of a conductive foil layer earlier, and described soft magnetic film can utilize modes such as sputter, spin coating (spin coating) or printing to be shaped.Described soft magnetic film material can be manganese-zinc-iron oxygen magnet (Mn-Zn ferrite), nickel-manganese-zinc-iron oxygen magnet (Ni-Mn-Zn ferrite) or tri-iron tetroxide (Magnetite) etc., can be by sputter-deposited (sputter-deposited); Adding then can the mode of printing deposition with Ferrite-resin plaster material (Ferrite-resin paste).Wherein Ferrite-resin plaster material can be manganese-zinc-iron oxygen magnet (Mn-Zn ferrite) powder and is dispersed in person in the resin, can form with modes such as sputter, spin coating (spin coating) or printings.
More than, going up the technology that forms an inductance in described dielectric layer 10a is the known technology person, so no longer excessively describe in this.
Described two solder mask 40a, 40b can be the green lacquer of welding resistance or pitch-dark (solder mask) the photosensitive polymer material wherein one or other equivalent materials; And the formation method of a plurality of solder mask perforate 41a, the 41b of described two solder mask 40a, 40b can be exposure and develops or other equivalent methods.
Moreover, described inductance body 20a also is made of a plurality of inductance body unit that are positioned at different layers, when for example the first inductance body unit and the second inductance body unit constitute, described a plurality of inductance body unit can electrically connect the one end separately by via, in the embodiment of another single layer substrate of the utility model, described dielectric layer is similarly an individual layer dielectric layer, yet described a plurality of inductance body unit lay respectively on the outer surface s1 and another outer surface s2 of described individual layer dielectric layer.
Please refer to shown in Figure 2, the base plate for packaging structure of another embodiment of the utility model is similar in appearance to the utility model one embodiment, and roughly continue to use similar elements title and figure number, but the difference characteristic of another embodiment is: the inductance that described base plate for packaging structure is comprised is configured to three-dimensional multilayer inductor structure, and described base plate for packaging is configured to have at least the base plate for packaging structure of the dielectric layer more than two layers, is example at this with the base plate for packaging with two layers of dielectric layer, and it comprises one first dielectric layer 10a and one second dielectric layer 10b; Described inductance body is to be made of a plurality of inductance body unit that are positioned at different layers, it comprises one first inductance body unit 20a and one second inductance body unit 20b, the end that described a plurality of inductance body unit 20a, 20b electrically connect separately by described via 50.The described first inductance body unit 20a position is on the outer surface s2 of the outer surface s1 of the described first dielectric layer 10a or the described second dielectric layer 10b, and the described second inductance body unit 20b is embedded between described first dielectric layer 10a and the described second dielectric layer 10b, if three layers or three layers during with the base plate for packaging structure of upper dielectric layer, described inductance body unit can be chosen in second layer dielectric layer or other internal layers, do not exceed with this example, in the present embodiment, the promptly described second inductance body unit 20b is arranged between a described 10a and the second dielectric layer 10b.Described via 50 runs through the described first dielectric layer 10a, with the end that electrically connects the described second inductance body unit 20b end to the described first inductance body unit 20a.The described second connection gasket 30b is formed on the other end that the described first dielectric layer 10a went up and electrically connected the described second via 50b.
In the present embodiment, and the situation of described first connection gasket 30a such as same embodiment can directly be formed on the end of described inductance body 20a or the position or the outer surface s1 (part except that inductance body position) that is formed on the described first dielectric layer 10a is connected on the end or a position of described inductance body 20a by circuit again; Described at least two second connection gasket 30b are if be exposed on the described upper surface, and also the connected mode with described first connection gasket 30a and inductance body 20a is the same, comprises the mode that is set directly on the inductance body or is electrically connected to inductance body 20a by circuit.Wherein described second a connection gasket 30b ' is if be positioned on the outer surface s2 of the described second dielectric layer 10b, then electrically connect an end or the diverse location of the described second inductance body unit 20b by an end of described via 50, also can run through described first by described two vias 50, the second dielectric layer 10a, 10b electrically connects the diverse location of the described first inductance body unit 20a, at this moment, at least two second connection gasket 30b ' both can be set directly at the other end of described via (via) 50, also can be arranged on the dielectric layer and electrically connect by a circuit (trace) other end (not illustrating) of described via 50.
In the present embodiment, the material of the described second dielectric layer 10b is selected to select identical with the material of the described first dielectric layer 10a; And the shape of described via 50 such as can be at the straight cylinder of path length, the photoresist layer that can utilize a patterning forms a plurality of conductive poles after with electroplating deposition one metal material, through covering described a plurality of conductive poles behind the described first dielectric layer 10a of pressing to form described via 50, described metal material can be copper, and the surface roughness of described a plurality of conductive poles (Ra) can be less than 1 micron, but not subject to the limits.
Please refer to shown in Figure 3, the base plate for packaging structure of the another embodiment of the utility model is similar in appearance to another embodiment of the utility model, as shown in Figure 2, and roughly continue to use similar elements title and figure number, but the difference characteristic of another embodiment is: described dielectric layer 10a is a multilayer dielectric layer, described inductance body 20a all is positioned at the inside of described multilayer dielectric layer, it is an internal embedded type inductive, wherein said inductance body 20a is made of a plurality of inductance body unit that are positioned at different layers, described a plurality of inductance body unit electrically connects by via, or constitute by an inductance body unit that is positioned at one deck, but all be to be embedded on arbitrary internal layer surface of described multilayer dielectric layer, be not arranged on the outermost layer dielectric layer of described base plate for packaging structure.In the present embodiment, be example with two layer package substrates, described dielectric layer 10 is a multilayer dielectric layer, it comprises one first dielectric layer 10a and one second dielectric layer 10b; And described inductance body 20a is embedded in the internal layer of the dielectric layer of described base plate for packaging structure, if three layers or three layers during with the base plate for packaging structure of upper dielectric layer, described inductance body unit can be chosen in the second layer or other internal layers, do not exceed with this example, in the present embodiment, promptly described inductance body 20a is arranged between described first, second dielectric layer 10a, the 10b.Described via 50 runs through the described first dielectric layer 10a, with the end that electrically connects the described second inductance body unit 20b end to the described first inductance body unit 20a.The described first connection gasket 30a is exposed to described upper surface, and electrically connects an end or a position of described inductance body 20a by a conduction column 50; And the described second connection gasket 30b is exposed to described upper surface or the described second connection gasket 30b ' is exposed to described lower surface, and electrically connect in addition at least two different positions of described inductance body 20a, wherein, the described first connection gasket 30a and one of them described second connection gasket 30b electrically connect the two ends of described inductance body 20a respectively.In the present embodiment, the advantage of embedded inductor design is arranged, the external surface area that can abdicate more described substrate is with the electronic component that offers outer surface (as chip etc.) and wiring.
Please refer to shown in Figure 4, the application stereogram of the base plate for packaging of the utility model one embodiment structure.On the described first dielectric layer 10a, put a chip 60 in addition, described chip 60 has several weld pads 601, described weld pad 601 is electrically connected to the described first connection gasket 30a by a lead 70, and other described second connection gasket 30b, 30b ' can for substrate on other chips, active element or passive component select to be connected, the perhaps described second connection gasket 30b, when 30b ' is connected to circuit board in semiconductor package body, electrically connect with circuit board.
Please refer to shown in Figure 5, the application side sectional view of another embodiment base plate for packaging of the utility model structure.On the described first dielectric layer 10a, a chip 60 is set in addition equally, described chip 60 has several weld pads 601, described weld pad 601 is electrically connected to the described first connection gasket 30a by a lead 70, and other described second connection gasket 30b, 30b ' can for substrate on other chips, active element or passive component select to be connected, the perhaps described second connection gasket 30b, when 30b ' is connected to circuit board in semiconductor package body, electrically connect with circuit board.
In the embodiment of Fig. 4 and Fig. 5, described chip 60 can be electrically connected to the described first connection gasket 30a by a described lead 70 earlier; And other described second connection gasket 30b can for substrate on other chips, active element or passive component select to be connected, the perhaps described second connection gasket 30b, when 30b ' is connected to circuit board in semiconductor package body, electrically connect with circuit board.By process so, can the required inductance value of flexible modulation and do not need again bonding wire or change inductor design etc. to save the inductance redesign and to need the cost and the time cost of test again.
As mentioned above, though among being embedded in substrate compared to existing base plate for packaging structure, but can resilient modulation with respect to inductance value, but can't effectively reach, though known technology is also arranged by the inductance of a plurality of different induction values is set on the substrate, and with the modulation of some switches with the control inductance value, but need shortcomings such as more design cost and material cost, the utility model base plate for packaging structure can be external to a plurality of connection gaskets by a plurality of positions are set on the inductance body, it can effectively provide the inductance value of the more flexible degree of active/passive element on chip and substrate or the circuit board to select really, and then the elasticity of raising circuit design, and the application elasticity of raising base plate for packaging, and save the cost of inductance redesign and test.
The utility model is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present utility model.Must be pointed out that disclosed embodiment does not limit scope of the present utility model.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope is included in the scope of the present utility model.
Claims (10)
1. a base plate for packaging structure has a upper surface and a lower surface, it is characterized in that: described base plate for packaging structure comprises:
At least one dielectric layer is arranged between described upper surface and the described lower surface;
One inductance body is arranged between described upper surface and the described lower surface;
At least one first connection gasket is exposed to described upper surface, and electrically connects a position of described inductance body; And
At least two second connection gaskets are exposed to described upper surface or described lower surface, and electrically connect at least two different positions in addition of described inductance body.
2. base plate for packaging structure as claimed in claim 1, it is characterized in that: described first connection gasket and one of them described second connection gasket electrically connect the two ends of described inductance body respectively.
3. base plate for packaging structure as claimed in claim 1, it is characterized in that: described inductance body is to be made of an inductance body unit that is positioned at one deck.
4. base plate for packaging structure as claimed in claim 1, it is characterized in that: described inductance body is to be made of a plurality of inductance body unit that are positioned at different layers, and described a plurality of inductance body unit electrically connect by via.
5. base plate for packaging structure as claimed in claim 3, it is characterized in that: described dielectric layer is an individual layer dielectric layer, and described inductance body is positioned at an outer surface of described individual layer dielectric layer.
6. base plate for packaging structure as claimed in claim 3, it is characterized in that: described dielectric layer is a multilayer dielectric layer, described inductance body is arranged in an outer surface of an outermost layer dielectric layer of described multilayer dielectric layer.
7. base plate for packaging structure as claimed in claim 3, it is characterized in that: described dielectric layer is a multilayer dielectric layer, and described inductance body is positioned at the inside of described multilayer dielectric layer.
8. base plate for packaging structure as claimed in claim 4, it is characterized in that: described dielectric layer is an individual layer dielectric layer, described a plurality of inductance body unit lay respectively on the outer surface and another outer surface of described individual layer dielectric layer.
9. base plate for packaging structure as claimed in claim 4, it is characterized in that: described dielectric layer is a multilayer dielectric layer, the part of described inductance body is arranged in an outer surface of an outermost layer dielectric layer of described multilayer dielectric layer.
10. base plate for packaging structure as claimed in claim 4, it is characterized in that: described dielectric layer is a multilayer dielectric layer, and described inductance body is positioned at the inside of described multilayer dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220710748 CN203103292U (en) | 2012-12-21 | 2012-12-21 | Package substrate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220710748 CN203103292U (en) | 2012-12-21 | 2012-12-21 | Package substrate structure |
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| Publication Number | Publication Date |
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| CN203103292U true CN203103292U (en) | 2013-07-31 |
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| CN 201220710748 Expired - Fee Related CN203103292U (en) | 2012-12-21 | 2012-12-21 | Package substrate structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050485A (en) * | 2012-12-21 | 2013-04-17 | 苏州日月新半导体有限公司 | Package substrate structure |
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2012
- 2012-12-21 CN CN 201220710748 patent/CN203103292U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050485A (en) * | 2012-12-21 | 2013-04-17 | 苏州日月新半导体有限公司 | Package substrate structure |
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