US20060261462A1 - Semiconductior package substrate with embedded resistors and method for fabricating same - Google Patents

Semiconductior package substrate with embedded resistors and method for fabricating same Download PDF

Info

Publication number
US20060261462A1
US20060261462A1 US11133278 US13327805A US2006261462A1 US 20060261462 A1 US20060261462 A1 US 20060261462A1 US 11133278 US11133278 US 11133278 US 13327805 A US13327805 A US 13327805A US 2006261462 A1 US2006261462 A1 US 2006261462A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
resistive material
layer
circuit board
patterned
resistor electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11133278
Other versions
US7135377B1 (en )
Inventor
Zao-Kuo Lai
Lin-Yin Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Phoenix Precision Technology Corp
Original Assignee
Phoenix Precision Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/167Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/04944th Group
    • H01L2924/04941TiN
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1453Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Abstract

A semiconductor package substrate with embedded resistors and a method for fabricating the same are proposed. Firstly, an inner circuit board having a first circuit layer thereon is provided, and a plurality of resistor electrodes are formed in the fist circuit layer. Then, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to accurately define a resistance value of resistors. Subsequently, at least one insulating layer is coated on a surface of the circuit board having the patterned resistive material. At least one patterned second circuit layer is formed on the insulating layer and electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer or plated through holes formed through the circuit board.

Description

    FIELD OF THE INVENTION
  • The present invention relates to semiconductor package substrates with embedded resistors and methods for fabricating the same, and more particularly, to a semiconductor package substrate having resistors embedded in a multi-layer circuit board and a method for fabricating the substrate, so as to provide good electrical performances for a semiconductor device using the substrate.
  • BACKGROUND OF THE INVENTION
  • Owing to the progress of semiconductor packaging technology and improvements in electrical performances for semiconductor chips, semiconductor devices are developed toward high integration. For example, a ball grid array (BGA) semiconductor device is characterized in that a plurality of array-arranged solder balls are formed on a bottom surface of a substrate and used as input/output (I/O) connections for electrically connecting a semiconductor chip mounted on the substrate to an external device such as printed circuit board (PCB). Compared to a conventional lead-frame based semiconductor device, the BGA semiconductor device advantageously provides more I/O connections on the same unit area of a chip carrier such as the substrate, and thus can accommodate more electronic circuits and semiconductor chips therein.
  • In accordance with high integration of the semiconductor device, more leads or contacts are required and also more noise is caused. Generally, for solving the noise problem, passive components such as resistors, capacitors and inductors are incorporated in the semiconductor device so as to eliminate the noise and stabilize the circuits, making a semiconductor chip packaged in the device have specific current characteristics.
  • FIG. 1 is a cross-sectional view showing a conventional passive component being mounted on a surface of a substrate. At least one pair of separate bond pads 11 are formed at predetermined positions on the surface of the substrate 10 and are exposed to a solder mask layer 12 that covers the substrate 10. Then, a solder paste 13 is applied on the bond pads 11, and two ends 140 of at least one passive component 14 are respectively attached to the bond pads 11 via the solder paste 13. A reflow process is performed to allow the passive component 14 to be bonded and electrically connected to the bond pads 11 on the substrate 10 via the solder paste 13. However, it is difficult to accurately control an applied amount of the solder paste 13, and the height of the solder paste 13 after being reflowed, as well as the surface flatness of the solder mask layer 12. Thereby, a gap 15 is usually left between the passive component 14 and the solder mask layer 12. In a high-temperature environment during subsequent fabrication processes, the solder paste 13 would melt or become softened and leaks to the gap 15 due to capillary attraction, which causes bridging of the solder paste 13 applied on the two bond pads 11 and short-circuiting of the passive components 14, and thus adversely affects the production yield.
  • Referring to FIG. 2 disclosed in U.S. Pat. No. 6,108,212, a bond pad 21 and at least one electrode 22 are formed on a surface of a substrate 20, and an electrically resistive volume 23 is disposed between the bond pad 21 and the electrode 22 to form a passive component comprising the bond pad 21, the electrode 22 and the electrically resistive volume 23. This allows the substrate 20 to be electrically connected to an external electronic device 25 such as printed circuit board by means of a metal bump 24 bonded to the bond pad 21. Also, the passive component formed by the bond pad 21, the electrode 22 and the electrically resistive volume 23 provides improved electrical performances for the semiconductor device. A pitch distance between the bond pad and the electrode on the surface of the substrate should be sufficiently large for successfully forming the electrically resistive volume having resistor effects. However, since the substrate has a limited surface area, a relatively large area occupied by the resistor would affect a layout of other circuits arranged on the substrate surface. This thus reduces flexibility of circuit routability on the substrate, sets a limitation on the number of passive components that can be incorporated on the substrate, and does not facilitate the high integration development for the semiconductor device. Furthermore, by the fact that the number of passive components to be incorporated is dramatically increased along with the requirement of high performances for the semiconductor device, if the foregoing method in which a semiconductor chip and a large number of passive components are simultaneously mounted on the substrate surface is employed, the size miniaturization for the semiconductor device can hardly be achieved.
  • In order to solve the above problem, U.S. Pat. No. 6,278,356 discloses a substrate 30 having a built-in layer passive component. Referring to FIG. 3, a copper layer 32 is formed respectively on an upper surface and a lower surface of an insulating layer 31, and the copper layer 32 is provided with an etching pattern 320. Then, a dielectric layer 33 is printed on the copper layer 32 and fills openings in the etching pattern 320. Subsequently, a resistive layer 34 is formed over the copper layer 32 and the dielectric layer 33 by the printing technique, wherein the resistive layer 34 serves as a resistor, and the dielectric layer 33 filling the openings in the etching patter 320 serves as a capacitor, so as to integrate a plurality of passive components on the substrate 30.
  • However, in the foregoing structure, only the printing technique is used to form the dielectric layer 33 and the resistive layer 34 on the substrate 30, such that it is difficult to accurately control the capacitance and resistance thereof respectively. Additionally, since the resistive layer 34 covers both the copper layer 32 and the dielectric layer 33 that are made of different materials, a reliability issue may be generated in a high-temperature and high-moisture environment during subsequent fabricating processes or tests, and thus electrical connection between the resistive layer and electrodes may also be affected.
  • Moreover, along with the blooming development of electronic industry, electronic products are gradually becoming more multi-functional and high efficient. In order to satisfy the requirements of high integration and size miniaturization for semiconductor packages, a circuit board for carrying active/passive components and circuits has been developed from a single-layer structure to a multi-layer board that employs the interlayer connection technique to enlarge usable circuit area on the circuit board, so as to incorporate a high circuit density in the circuit board. However, the foregoing prior art only discloses that passive components can be mounted on the surface of the substrate but does not provide a strategy to apply passive components to a multi-layer package substrate in accordance with the requirements of high integration and size miniaturization for the semiconductor package.
  • Therefore, the problem to be solved here is to incorporate an effective number of electronic elements such as passive components and semiconductor chips in a semiconductor package substrate with multiple layers of circuits, which can assure the fabrication reliability and accuracy and improve electrical performance of electronic products, without affecting circuit routability of the substrate and increasing the overall thickness of the semiconductor package, so as to meet the requirements of compact size, multiple functions and high electrical performances of the electronic products.
  • SUMMARY OF THE INVENTION
  • In light of the above drawbacks in the prior art, a primary objective of the present invention is to provide a semiconductor package substrate with embedded resistors and a method for fabricating the same, by which a multi-layer package substrate integrated with resistors is formed to meet the requirements of high integration and size miniaturization for semiconductor packages.
  • Another objective of the present invention is to provide a semiconductor package substrate with embedded resistors and a method for fabricating the same, by which a surface area being used on the substrate is reduced to make a semiconductor device compact in size.
  • Still another objective of the present invention is to provide a semiconductor package substrate with embedded resistors and a method for fabricating the same, which can improve the fabrication reliability and accuracy in resistance of the resistors.
  • A further objective of the present invention is to provide a semiconductor package substrate with embedded resistors and a method for fabricating the same, which can increase the number of passive components incorporated in a semiconductor device and improve flexibility of circuit routability of the substrate.
  • In accordance with the above and other objectives, the present invention proposes a semiconductor package substrate with embedded resistors. The resistors embedded in the substrate can thus be incorporated in a semiconductor device using the substrate without influencing circuit routability on the surface of the substrate.
  • The present invention also proposes a method for fabricating the above semiconductor package substrate with embedded resistors, which comprises the following steps. First, an inner circuit board having a first circuit layer thereon is provided and a plurality of resistor electrodes are formed in the first circuit layer. Subsequently, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to define a resistance value of resistors. At least one insulating layer is formed on a surface of the circuit board having the patterned resistive material, and a plurality of vias are formed in the insulating layer to expose the resistor electrodes. Then, at least one second circuit layer is formed on the surface of the insulating layer, such that the second circuit layer is electrically connected to the resistor electrodes by the plurality of vias formed in the insulating layer.
  • A semiconductor package substrate with embedded resistors fabricated by the foregoing method in the present invention comprises: an inner circuit board having a first circuit layer thereon, the first circuit layer having a plurality of resistor electrodes; at least one patterned resistive material formed on the inner circuit board and electrically connected to the resistor electrodes to define a resistance value of resistors; at least one patterned second circuit layer formed on a surface of the circuit board having the patterned resistive material and spaced from the patterned resistive material by an insulating layer; and a plurality of conductive vias formed in the insulating layer, for electrically connecting the second circuit layer to the resistor electrodes.
  • In another embodiment, the method for fabricating a semiconductor package substrate with embedded resistors in the present invention comprises the following steps. First, an inner circuit board having a first circuit layer thereon is provided and a plurality of resistor electrodes are formed in the first circuit layer. Subsequently, a patterned resistive material is formed on the inner circuit board and electrically connected to the resistor electrodes to define a resistance value of resistors. At least one insulating layer is formed on a surface of the circuit board having the patterned resistive material, and at least one patterned second circuit layer is formed on the insulating layer. A plurality of plated through holes (PTH) are formed through the circuit board. And a plurality of conductive vias are formed in the insulating layer and electrically connect the second circuit layer to the resistor electrodes.
  • By the above fabrication method, a semiconductor package substrate with embedded resistors proposed in the present invention is obtained comprising: an inner circuit board having a first circuit layer thereon, the first circuit layer having a plurality of resistor electrodes; at least one patterned resistive material formed on the inner circuit board and electrically connected to the resistor electrodes; at least one patterned second circuit layer formed on a surface of the circuit board having the patterned resistive material and spaced from the patterned resistive material by an insulating layer; a plurality of plated through holes formed through the insulating layer and the circuit layers, and electrically connected to the circuit layers and the resistor electrodes; and a plurality of conductive vias formed in the insulating layer, for electrically connecting the second circuit layer to the resistor electrodes.
  • For the semiconductor package substrate with embedded resistors and the method for fabricating the same proposed in the present invention, a patterned first circuit layer is first formed on an inner circuit board and is provided with a plurality of resistor electrodes. Then, a patterned resistive material is applied on the inner circuit board and electrically connected to the resistor electrodes to define a resistance value of resistors. That is, the resistance value can be accurately determined according to the type of resistive material being used and the size such as length and area of the effective resistive material formed between the resistor electrodes, so as to improve accuracy in the resistance value of the resistors and reliability of the fabrication processes. Furthermore, the circuit layers can be electrically connected to the resistor electrodes by means of a plurality of plated through holes or conductive vias, so as to form a multi-layer package substrate with embedded resistors. This thus increases the number of passive components incorporated in the semiconductor device and improves flexibility of the circuit routability of the substrate, to meet the requirements of high integration and size miniaturization for the semiconductor package.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:
  • FIG. 1 (PRIOR ART) is a cross-sectional view showing a conventional passive component being mounted on a surface of a substrate;
  • FIG. 2 (PRIOR ART) is a cross-sectional view of a substrate integrated with passive components according to U.S. Pat. No. 6,108,212;
  • FIG. 3 (PRIOR ART) is a cross-sectional view of a substrate integrated with passive components according to U.S. Pat. No. 6,278,356;
  • FIGS. 4A to 4G are cross-sectional views showing procedural steps of a method for fabricating a semiconductor package substrate with embedded resistors according to a preferred embodiment of the present invention; and
  • FIGS. 5A to 5H are cross-sectional views showing procedural steps of a method for fabricating a semiconductor package substrate with embedded resistors according to another preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIGS. 4A to 4G show the procedural steps of a method for fabricating a semiconductor package substrate with embedded resistors according to a preferred embodiment of the present invention.
  • First, referring to FIG. 4A, an inner circuit board 41 is provided and a conductive metal layer 42 is formed on a surface of the inner circuit board 41. The conductive metal layer 42 can be made of copper metal or any other conductive metal. The inner circuit board 41 may be a double-layer circuit board or a multi-layer circuit board.
  • Referring to FIG. 4B, the conductive metal layer 42 is patterned to form a first circuit layer 43 by an etching process. Alternatively, the inner circuit board 41 can be a multi-layer circuit board and the first circuit layer 43 is formed on a superficial insulating layer of the multi-layer circuit board. The first circuit layer 43 comprises a plurality of resistor electrodes 430 for being subsequently electrically connected to resistors.
  • Referring to FIG. 4C, a resistive material 44 is applied on the inner circuit board 41. The resistive material 44 can be a thick film resistive material or a thin film resistive material. The thick film resistive material may be made of silver powders or carbon particles dispersed in a resin, or ruthenium oxide (RuO2) and glass powders dispersed in a binder to be applied and cured. As shown in FIG. 4C, the thick film resistive material 44 on the inner circuit board 41 is patterned by a laser or etching technique, allowing the resistive material 44 to be electrically connected to the resistor electrodes 430 and partially or completely cover the electrodes 430, such that the resistance of resistors can be accurately defined and the reliability thereof can also be improved (as shown in FIG. 4D). Alternatively, the thick film resistive material 44 can be directly deposited on the resistor electrodes 430 by a screen-printing technique. Subsequently, the thick film resistive material 44 can be patterned by the laser or etching technique to be electrically connected to the resistor electrodes 430 and accurately define the resistance of the resistive material 44.
  • Alternatively, referring to FIGS. 4C′ and 4D′, if the resistive material 44 is the thin film resistive material such as nickel-chromium (Ni—Cr) alloy, nickel-phosphorus (Ni—P) alloy, nickel-tin (Ni—Sn) alloy, chromium-aluminum (Cr—Al) alloy or titanium nitride (TaN) alloy, a patterned thin film resist layer 440 is first formed on the substrate to define an area for depositing the thin film resistive material. Then, the thin film resistive material 44 is deposited in openings of the resist layer 440 by a sputtering, electroplating or electroless plating technique, so as to allow the resistive material 44 to partially or completely cover the resistor electrodes 430 and be electrically connected to the resistor electrodes 430. Subsequently, the resist layer 440 is removed. In this embodiment, the subsequent fabrication processes are described primarily for fabricating build-up layers on the thick film resistive material.
  • The selection of either the thick film resistive material or the thin film resistive material depends on the fabrication cost of a multi-layer package substrate and the electrical accuracy of passive components being fabricated. Further, a desirable resistance value required for the semiconductor package substrate can be determined according to the type of resistive material being used and the size of the resistive material formed between the resistor electrodes. The resistive material may partially or completely cover the electrodes, so as to prevent a reliability issue caused in a high-temperature and high-moisture environment during subsequent fabrication processes and tests, and not to influence the electrical connection between the resistive material and the electrodes.
  • Referring to FIG. 4E, at least one insulating layer 45 is formed over the patterned resistive material 44 on the surface of the circuit board 41. The insulating layer 45 can be made of an insulating organic material or a ceramic material, such as epoxy resin, polyimide, bismaleimide triazine-based resin, photoimagable resin, or a composite material thereof with glass fibers. A roller coating, printing or lamination technique can be applied to form the insulating layer 45. It should be understood that the insulating layer 45 is not limited to being made of a single organic material, but can also be laminated by different insulating material layers.
  • Referring to FIG. 4F, a plurality of vias 450 are formed in the insulating layer 45 by one of a mechanical drilling, laser drilling technique, or photolithographic technique, wherein at least one of the vias 450 exposes at least one of resistor electrodes 430.
  • Referring to FIG. 4G, a patterned second circuit layer 46 and a plurality of conductive vias 451 are respectively formed on a surface of the insulating layer 45 and in the vias 450, such that the second circuit layer 46 is electrically connected to the resistor electrodes 430 by the conductive vias 451. This thereby completely fabricates a multi-layer package substrate with embedded resistors. The second circuit layer can be formed by a build-up or lamination technique; for example, an electroplating process may be used together with the build-up technique to form such patterned circuit layer, or alternatively, a copper foil can be pressed and etched to form the patterned circuit layer. Certainly, more insulating layers and circuit layers can be further built up on a surface of the substrate to fabricate a package substrate with more circuit layers. The substrate can be a flip-chip package substrate or a wire-bonding package substrate.
  • FIGS. 5A to 5H show the procedural steps of a method for fabricating a semiconductor package substrate with embedded resistors according to another preferred embodiment of the present invention, wherein the fabrication processes shown in FIGS. 5A to 5E are the same as those in FIGS. 4A to 4E and therefore not to be further repeated here.
  • Referring to FIG. 5F, after the resistive material 44 on the first circuit layer 43 is patterned by the laser or etching technique and the resistors corresponding to the resistor electrodes 430 of the first circuit layer 43 are embedded, a plurality of through holes 47 are formed through the substrate by the mechanical drilling or laser drilling technique.
  • Referring to FIG. 5G, a conductive metal layer 48 such as copper layer is plated on surfaces of the substrate and inner walls of the through holes 47. Then, a filling material such as an insulating material e.g. epoxy resin or a conductive material e.g. solder paste is used to fill the through holes 47, so as to form plated through holes (PTHs) 470 that are electrically connected to the resistor electrodes 430.
  • Referring to FIG. 5H, a plurality of conductive vias 451 are formed in the insulating layer 45 and at least one patterned second circuit layer 49 is formed on the insulating layer 45, such that the second circuit layer 49 is electrically connected to the resistor electrodes 430 by the conductive vias 451. This thereby completely fabricates a multi-layer package substrate with embedded resistors. Certainly, more insulating layers and circuit layers can be further built up on a surface of the substrate to fabricate a package substrate with more circuit layers. The substrate can be a flip-chip package substrate or a wire-bonding package substrate.
  • FIGS. 4G and 5H respectively show a semiconductor package substrate with embedded resistors according to the present invention.
  • This package substrate comprises an inner circuit board 41, at least one insulating layer 45, a circuit layer 46, 49 formed on the insulating layer 45, at least one resistive material 44, a plurality of resistor electrodes 430 electrically connected to the resistive material, a plurality of plated through holes 470 for electrically connecting the circuit layer to the resistor electrodes, and a plurality of conductive vias 451 formed through the insulating layer and for electrically connecting the circuit layer to the resistor electrodes.
  • The insulating layer 45 can be made of an organic materials, a fiber-reinforced organic material, a particle-reinforced organic material, such as epoxy resin, polyimide, bismaleimide triazine-based resin, or cyanate. The circuit layer 46, 49 can be a patterned copper layer formed by etching or electroplating technique.
  • The resistive material 44 comprise thick film resistive passive components or thin film resistive passive components. The thick film resistive material is made of silver powders or carbon particles dispersed in a resin, and ruthenium oxide (RuO2) and glass powders dispersed in a binder to be applied and cured. The thin film resistive material is made of nickel-chromium (Ni—Cr) alloy, nickel-phosphorus (Ni—P) alloy, nickel-tin (Ni—Sn) alloy, chromium-aluminum (Cr—Al) alloy, or titanium nitride (TaN) alloy, etc., which can be formed by the sputtering, electroplating or electroless plating technique. The selection of either the thick film resistive material or the thin film resistive material depends on the fabrication cost of the multi-layer substrate and the electrical accuracy of the resistors being fabricated. Further, a desirable resistance value required for the semiconductor package substrate can be determined according to the type of resistive material being used and the size of the resistive material formed between the resistor electrodes.
  • The plated through holes 470 are fabricated by forming through holes in the substrate using the mechanical drilling or laser drilling technique, then coating a conductive metal layer such as copper layer over surfaces of the substrate and inner walls of the through holes, and finally applying a filling material such as an insulating material e.g. epoxy resin or a conductive material e.g. solder paste for filling the through holes. The fabricated plated through holes 470 are electrically connected to the resistor electrodes.
  • By the semiconductor package substrate with embedded resistors and the method for fabricating the same proposed in the present invention, the resistors are embedded in the substrate and can be incorporated in a semiconductor device using the substrate, such that the number and electrical performances of passive components provided in the semiconductor device can both be increased, and flexibility of circuit routability of the substrate can also be improved, as well as the area being used on the substrate can be reduced, which favors the size miniaturization of the semiconductor device.
  • For the semiconductor package substrate with embedded resistors and the method for fabricating the same proposed in the present invention, a patterned first circuit layer is first formed on an inner circuit board and is provided with a plurality of resistor electrodes. At least one resistive material is applied on a surface of the inner circuit board and patterned according to a desirable resistance value required by actual electrical performances, allowing the resistive material to partially or completely cover the resistor electrodes. That is, the desirable resistance value can be accurately determined according to the type of resistive material being used and the size such as length and area of the effective resistive material formed between the resistor electrodes, so as to prevent a reliability issue caused in a high-temperature and high-moisture environment during the subsequent fabrication processes and tests, and not to influence the electrical connection between the resistive material and the electrodes. As a result, accuracy in the resistance value of the resistors and reliability of the fabrication processes are both improved. Furthermore, the circuit layers can be electrically connected to the resistor electrodes by means of a plurality of plated through holes or conductive vias, so as to form a multi-layer package substrate with embedded resistors. This thus increases the number of passive components incorporated in the semiconductor device and improves flexibility of the circuit routability of the substrate, to meet the requirements of high integration and size miniaturization for the semiconductor package.
  • The foregoing drawings only show the partial resistive material. Practically, the numbers and the corresponding positions of the resistive material and the circuit layer are flexibility arranged between the laminated layers of the substrate. The resistive material can be formed on any inner circuit layer in a circuit board and is not limited to being formed on a core circuit layer of the circuit board. Also, the above fabrication processes can be applied to a single side or double sides of the inner circuit board.
  • The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (20)

  1. 1. A method for fabricating a semiconductor package substrate with embedded resistors, the method comprising the steps of:
    providing an inner circuit board having a patterned first circuit layer thereon, the first circuit layer having a plurality of resistor electrodes;
    forming a patterned resistive material on the inner circuit board, and allowing the patterned resistive material to be electrically connected to the resistor electrodes and to partially or completely cover the resistor electrodes;
    applying at least one insulating layer on a surface of the inner circuit board having the patterned resistive material; and
    forming at least one patterned second circuit layer on the insulating layer, and allowing the patterned second circuit layer to be electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer.
  2. 2. The method of claim 1, wherein the inner circuit board is one selected from the group consisting of a double-layer circuit board and a multi-layer circuit board.
  3. 3. The method of claim 1, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    coating a layer of the resistive material on the inner circuit board; and
    patterning the resistive material and allowing the resistive material to be electrically connected to the resistor electrodes.
  4. 4. The method of claim 1, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    depositing the resistive material on the resistor electrodes via a screen-printing technique; and
    accurately defining a resistance value of the resistive material, such that the resistive material is electrically connected to the resistor electrodes.
  5. 5. The method of claim 1, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    forming a patterned resist layer on the inner circuit board to define an area for depositing the resistive material;
    depositing the resistive material in openings of the patterned resist layer, such that the resistive material is electrically connected to the resistor electrodes; and
    removing the resist layer.
  6. 6. (canceled)
  7. 7. (canceled)
  8. 8. (canceled)
  9. 9. (canceled)
  10. 10. (canceled)
  11. 11. A method for fabricating a semiconductor package substrate with embedded resistors, comprising the steps of:
    providing an inner circuit board having a patterned first circuit layer thereon, the first circuit layer having a plurality of resistor electrodes;
    forming a patterned resistive material on the inner circuit board, and allowing the patterned resistive material to be electrically connected to the resistor electrodes;
    applying at least one insulating layer on a surface of the inner circuit board having the patterned resistive material;
    forming a plurality of plated through holes through the insulating layer and the first circuit layer, and allowing the plated through holes to be electrically connected to the first circuit layer and the resistor electrodes; and
    forming at least one patterned second circuit layer on the insulating layer, and allowing the patterned second circuit layer to be electrically connected to the resistor electrodes by a plurality of conductive vias formed in the insulating layer.
  12. 12. The method of claim 11, wherein the inner circuit board is one selected from the group consisting of a double-layer circuit board and a multi-layer circuit board.
  13. 13. The method of claim 11, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    coating a layer of the resistive material on the inner circuit board; and
    patterning the resistive material layer, such that the resistive material is electronically connected to the resistor electrodes.
  14. 14. The method of claim 11, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    depositing the resistive material on the resistor electrodes via a screen-printing technique; and
    accurately defining a resistance value of the resistive material, such that the resistive material is electrically connected to the resistor electrodes.
  15. 15. The method of claim 11, wherein the step of forming the patterned resistive material on the inner circuit board comprises:
    forming a patterned resist layer on the inner circuit board to define an area for depositing the resistive material;
    depositing the resistive material in openings of the patterned resist layer, such that the resistive material is electrically connected to the resistor electrodes; and
    removing the resist layer.
  16. 16. (canceled)
  17. 17. (canceled)
  18. 18. (canceled)
  19. 19. (canceled)
  20. 20. (canceled)
US11133278 2005-05-20 2005-05-20 Semiconductor package substrate with embedded resistors and method for fabricating same Expired - Fee Related US7135377B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11133278 US7135377B1 (en) 2005-05-20 2005-05-20 Semiconductor package substrate with embedded resistors and method for fabricating same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11133278 US7135377B1 (en) 2005-05-20 2005-05-20 Semiconductor package substrate with embedded resistors and method for fabricating same

Publications (2)

Publication Number Publication Date
US7135377B1 US7135377B1 (en) 2006-11-14
US20060261462A1 true true US20060261462A1 (en) 2006-11-23

Family

ID=37397637

Family Applications (1)

Application Number Title Priority Date Filing Date
US11133278 Expired - Fee Related US7135377B1 (en) 2005-05-20 2005-05-20 Semiconductor package substrate with embedded resistors and method for fabricating same

Country Status (1)

Country Link
US (1) US7135377B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070123015A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Passive components in the back end of integrated circuits
US20090223700A1 (en) * 2008-03-05 2009-09-10 Honeywell International Inc. Thin flexible circuits

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20070016383A (en) * 2005-08-03 2007-02-08 삼성전자주식회사 Chip type electric device and liquid crystal display module including the same
JP2008305988A (en) * 2007-06-07 2008-12-18 Nippon Mektron Ltd Method of manufacturing printed wiring board incorporating resistive element
KR20090067249A (en) * 2007-12-21 2009-06-25 삼성전기주식회사 Printed circuit board and manufacturing method thereof

Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648364A (en) * 1970-04-30 1972-03-14 Hokuriku Elect Ind Method of making a printed resistor
US4459321A (en) * 1982-12-30 1984-07-10 International Business Machines Corporation Process for applying closely overlapped mutually protective barrier films
US4490429A (en) * 1981-07-24 1984-12-25 Hitachi, Ltd. Process for manufacturing a multilayer circuit board
US4748085A (en) * 1985-11-16 1988-05-31 Narumi China Corporation Multilayer ceramic circuit board fired at a low temperature
US5108421A (en) * 1990-10-01 1992-04-28 Quinton Instrument Company Insertion assembly and method of inserting a vessel plug into the body of a patient
US5270493A (en) * 1990-11-26 1993-12-14 Matsushita Electric Industrial Co., Ltd. Printed circuit board having electromagnetic wave shield layer and self-contained printed resistor
US5383896A (en) * 1993-05-25 1995-01-24 Gershony; Gary Vascular sealing device
US5613974A (en) * 1992-12-10 1997-03-25 Perclose, Inc. Apparatus and method for vascular closure
US5782861A (en) * 1996-12-23 1998-07-21 Sub Q Inc. Percutaneous hemostasis device
US5810846A (en) * 1995-08-03 1998-09-22 United States Surgical Corporation Vascular hole closure
US6108212A (en) * 1998-06-05 2000-08-22 Motorola, Inc. Surface-mount device package having an integral passive component
US6120524A (en) * 1999-02-16 2000-09-19 Taheri; Syde A. Device for closing an arterial puncture and method
US6261258B1 (en) * 1999-05-03 2001-07-17 Marius Saines Hemostatic device for angioplasty
US6278356B1 (en) * 2000-05-17 2001-08-21 Compeq Manufacturing Company Limited Flat, built-in resistors and capacitors for a printed circuit board
US20010023535A1 (en) * 1999-05-11 2001-09-27 Gregory Dunn Polymer thick-film resistor printed on planar circuit board surface
US6325789B1 (en) * 1990-12-27 2001-12-04 Datascope Investment Corporation Device and method for sealing puncture wounds
US6368341B1 (en) * 1996-08-06 2002-04-09 St. Jude Medical Puerto Rico, B.V. Insertion assembly and method of inserting a hemostatic closure device into an incision
US6383208B1 (en) * 1999-11-05 2002-05-07 Onux Medical, Inc. Apparatus and method for approximating and closing the walls of a hole or puncture in a physiological shell structure
US6458670B2 (en) * 1997-08-05 2002-10-01 Denso Corporation Method of manufacturing a circuit substrate
US6482179B1 (en) * 1999-05-28 2002-11-19 Cohesion Technologies, Inc. Apparatuses, methods and compositions for closing tissue puncture openings
US6524321B2 (en) * 2001-01-03 2003-02-25 Nozomu Kanesaka Closure device for puncture in vessel
US6679904B2 (en) * 1996-10-17 2004-01-20 Malachy Gleeson Device for closure of puncture wound
US6682489B2 (en) * 2001-01-12 2004-01-27 Radi Medical Systems Ab Technique to confirm correct positioning of arterial wall sealing device
US6743195B2 (en) * 2001-03-14 2004-06-01 Cardiodex Balloon method and apparatus for vascular closure following arterial catheterization
US20040150966A1 (en) * 2003-01-30 2004-08-05 Chu-Chin Hu Integrated library core for embedded passive components and method for forming electronic device thereon
US6890342B2 (en) * 2000-08-02 2005-05-10 Loma Linda University Method and apparatus for closing vascular puncture using hemostatic material
US6939738B2 (en) * 2000-12-27 2005-09-06 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US20060094156A1 (en) * 2004-11-01 2006-05-04 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded resistors and method for fabricating the same

Patent Citations (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3648364A (en) * 1970-04-30 1972-03-14 Hokuriku Elect Ind Method of making a printed resistor
US4490429A (en) * 1981-07-24 1984-12-25 Hitachi, Ltd. Process for manufacturing a multilayer circuit board
US4459321A (en) * 1982-12-30 1984-07-10 International Business Machines Corporation Process for applying closely overlapped mutually protective barrier films
US4748085A (en) * 1985-11-16 1988-05-31 Narumi China Corporation Multilayer ceramic circuit board fired at a low temperature
US5108421A (en) * 1990-10-01 1992-04-28 Quinton Instrument Company Insertion assembly and method of inserting a vessel plug into the body of a patient
US5270493A (en) * 1990-11-26 1993-12-14 Matsushita Electric Industrial Co., Ltd. Printed circuit board having electromagnetic wave shield layer and self-contained printed resistor
US6325789B1 (en) * 1990-12-27 2001-12-04 Datascope Investment Corporation Device and method for sealing puncture wounds
US5613974A (en) * 1992-12-10 1997-03-25 Perclose, Inc. Apparatus and method for vascular closure
US5383896A (en) * 1993-05-25 1995-01-24 Gershony; Gary Vascular sealing device
US5810846A (en) * 1995-08-03 1998-09-22 United States Surgical Corporation Vascular hole closure
US6368341B1 (en) * 1996-08-06 2002-04-09 St. Jude Medical Puerto Rico, B.V. Insertion assembly and method of inserting a hemostatic closure device into an incision
US6679904B2 (en) * 1996-10-17 2004-01-20 Malachy Gleeson Device for closure of puncture wound
US5782861A (en) * 1996-12-23 1998-07-21 Sub Q Inc. Percutaneous hemostasis device
US6458670B2 (en) * 1997-08-05 2002-10-01 Denso Corporation Method of manufacturing a circuit substrate
US6108212A (en) * 1998-06-05 2000-08-22 Motorola, Inc. Surface-mount device package having an integral passive component
US6120524A (en) * 1999-02-16 2000-09-19 Taheri; Syde A. Device for closing an arterial puncture and method
US6261258B1 (en) * 1999-05-03 2001-07-17 Marius Saines Hemostatic device for angioplasty
US20010023535A1 (en) * 1999-05-11 2001-09-27 Gregory Dunn Polymer thick-film resistor printed on planar circuit board surface
US6482179B1 (en) * 1999-05-28 2002-11-19 Cohesion Technologies, Inc. Apparatuses, methods and compositions for closing tissue puncture openings
US6383208B1 (en) * 1999-11-05 2002-05-07 Onux Medical, Inc. Apparatus and method for approximating and closing the walls of a hole or puncture in a physiological shell structure
US6278356B1 (en) * 2000-05-17 2001-08-21 Compeq Manufacturing Company Limited Flat, built-in resistors and capacitors for a printed circuit board
US6890342B2 (en) * 2000-08-02 2005-05-10 Loma Linda University Method and apparatus for closing vascular puncture using hemostatic material
US6939738B2 (en) * 2000-12-27 2005-09-06 Matsushita Electric Industrial Co., Ltd. Component built-in module and method for producing the same
US6524321B2 (en) * 2001-01-03 2003-02-25 Nozomu Kanesaka Closure device for puncture in vessel
US6682489B2 (en) * 2001-01-12 2004-01-27 Radi Medical Systems Ab Technique to confirm correct positioning of arterial wall sealing device
US6743195B2 (en) * 2001-03-14 2004-06-01 Cardiodex Balloon method and apparatus for vascular closure following arterial catheterization
US20040150966A1 (en) * 2003-01-30 2004-08-05 Chu-Chin Hu Integrated library core for embedded passive components and method for forming electronic device thereon
US20060094156A1 (en) * 2004-11-01 2006-05-04 Phoenix Precision Technology Corporation Semiconductor package substrate with embedded resistors and method for fabricating the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070123015A1 (en) * 2005-11-30 2007-05-31 International Business Machines Corporation Passive components in the back end of integrated circuits
US7768055B2 (en) * 2005-11-30 2010-08-03 International Business Machines Corporation Passive components in the back end of integrated circuits
US20100297825A1 (en) * 2005-11-30 2010-11-25 International Business Machines Corporation Passive Components in the Back End of Integrated Circuits
US8039354B2 (en) 2005-11-30 2011-10-18 International Business Machines Corporation Passive components in the back end of integrated circuits
US20090223700A1 (en) * 2008-03-05 2009-09-10 Honeywell International Inc. Thin flexible circuits
US20150053465A1 (en) * 2008-03-05 2015-02-26 Honeywell International Inc. Thin flexible circuits

Also Published As

Publication number Publication date Type
US7135377B1 (en) 2006-11-14 grant

Similar Documents

Publication Publication Date Title
US6542379B1 (en) Circuitry with integrated passive components and method for producing
US6740964B2 (en) Semiconductor package for three-dimensional mounting, fabrication method thereof, and semiconductor device
US5689091A (en) Multi-layer substrate structure
US5886415A (en) Anisotropic conductive sheet and printed circuit board
US6744135B2 (en) Electronic apparatus
US5780776A (en) Multilayer circuit board unit
US6281448B1 (en) Printed circuit board and electronic components
US6300576B1 (en) Printed-circuit board having projection electrodes and method for producing the same
US20080041621A1 (en) Circuit board structure and method for fabricating the same
US6967138B2 (en) Process for manufacturing a substrate with embedded capacitor
US7122901B2 (en) Semiconductor device
US20070064375A1 (en) Ceramic capacitor
US20050282314A1 (en) Printed circuit boards and methods for fabricating the same
US20050161833A1 (en) Semiconductor device and method of manufacturing the same
US20070263364A1 (en) Wiring board
US20100044845A1 (en) Circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate
US20090046441A1 (en) Wiring board for mounting semiconductor device, manufacturing method of the same, and wiring board assembly
US20080090335A1 (en) Circuit module and manufacturing method thereof
US6915566B2 (en) Method of fabricating flexible circuits for integrated circuit interconnections
US6504111B2 (en) Solid via layer to layer interconnect
US20050184377A1 (en) Semiconductor device and method of manufacturing the same
US20060121719A1 (en) Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure
US20030011070A1 (en) Semiconductor package, method of manufacturing the same, and semiconductor device
US6759318B1 (en) Translation pad flip chip (TPFC) method for improving micro bump pitch IC substrate structure and manufacturing process
US20040187297A1 (en) Method of fabricating a polymer resistor in an interconnection via

Legal Events

Date Code Title Description
AS Assignment

Owner name: PHOENIX PRECISION TECHNOLOGY CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LAI, ZAO-KUO;WONG, LIN-YIN;REEL/FRAME:016591/0436

Effective date: 20041022

RF Reissue application filed

Effective date: 20090313

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Expired due to failure to pay maintenance fee

Effective date: 20101114