CN203102260U - Information processing device - Google Patents
Information processing device Download PDFInfo
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- CN203102260U CN203102260U CN2012207496485U CN201220749648U CN203102260U CN 203102260 U CN203102260 U CN 203102260U CN 2012207496485 U CN2012207496485 U CN 2012207496485U CN 201220749648 U CN201220749648 U CN 201220749648U CN 203102260 U CN203102260 U CN 203102260U
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Abstract
The utility model discloses an information processing device which is applicable to a high-speed cache of video pixel data or graphic texture data. The information processing device comprises a high-speed buffer memory, a determination type unit, a determination missing unit, a reading unit and a filling unit, wherein the determination type unit is composed of a complementary metal-oxide-semiconductor transistor (CMOS) logic circuit and connected with an external processor, the determination missing unit is composed of a CMOS logic circuit and connected with the determination type unit, the reading unit is composed of a CMOS logic circuit and connected with the determination missing unit and an off-chip memory, and the filling unit is composed of a CMOS logic circuit and connected with the reading unit and the high-speed buffer memory. The multiplex technique is adopted in the information processing device, and therefore chip area is saved, and chip power consumption is reduced.
Description
Technical field
The utility model relates to field of digital information processing, relates in particular to a kind of reusable signal conditioning package.
Background technology
In the technical development of computer process, the access speed of internal memory always than the CPU processing speed slowly many, make the high speed processing ability of CPU not give full play to, influence the work efficiency of whole computer system.Cache memory is used to relax the unmatched contradiction of speed between CPU and the internal memory.Adopt the cache memory technology quite general at present.Cache memory is the single-level memory that is present between internal memory and the CPU, and (SRAM) forms by the static store chip, and volume ratio is less, but its access speed can be complementary with CPU.According to the program locality principle, those unit of a certain unit of the internal memory that is using vicinity are very big with the possibility that is used to.Thereby, when a certain unit of CPU access memory, computer hardware is called in cache memory with regard to that group location contents that automatically will comprise this unit, and CPU is about to the internal storage location of access probably just in just calling in that group unit of cache memory.So CPU just can directly carry out access to cache memory.In the entire process process, if the operation of the most access memory of CPU can be replaced by access cache, computer system processor speed just can significantly improve.
In video encoding-decoding process, video pixel (mainly being the reference frame pixel) need take a large amount of memory bandwidth, is coding and decoding video committed memory bandwidth the best part.Existing coding and decoding video chip majority all uses high-speed cache on the sheet (Cache) to come the storage of reference frames pixel, thereby reduces memory bandwidth, reduces access delay simultaneously.
And in 3 D graphics chip, texture also is a committed memory bandwidth the best part.Existing 3 D graphics chip also all adopts on the sheet texture caching to store texture, thereby reduces memory bandwidth, reduces access delay.
But, the inventor finds: at existing systems chip (System-on-a-chip, SoC) in, the common separate storage of video pixel and texture, need dispose buffer memory on the sheet for coding and decoding video, dispose buffer memory on another sheet again for the 3D texture simultaneously, not only taken chip area, increased chip power-consumption simultaneously.
Publication number is in the Chinese invention patent application of CN101583929A, disclosed a kind of dynamic configurable texture cache that is used for multi-texturing, solved the collision problem under single texture pattern and the many texture pattern, but still the high-speed cache problem between unresolved data texturing and the video pixel data.
The utility model content
Technical problem to be solved in the utility model provides a kind of high-speed cache that can support video pixel data and graphical textures data simultaneously, thereby saves chip area, reduces chip power-consumption.。
In order to address the above problem, according to an aspect of the present utility model, provide a kind of signal conditioning package, be applicable to the high-speed cache of video pixel data or graphical textures data, comprising:
Cache memory;
Definite type units by the CMOS logical circuit constitutes links to each other with ppu;
Definite short-landing account unit by the CMOS logical circuit constitutes links to each other with described definite type units;
Reading unit by the CMOS logical circuit constitutes links to each other with described definite disappearance unit and chip external memory;
Filler cells by the CMOS logical circuit constitutes links to each other with described reading unit and described cache memory.
In one embodiment, described signal conditioning package also comprises: clock generation unit; Described cache configuration becomes to guarantee that per two clock period read all videos pixel component of a cache lines, guarantees that perhaps each clock period reads any four data texturings adjacent one another are.
In one embodiment, described chip external memory comprises: one or more in external storage, the level 2 buffering storer.
In one embodiment, described signal conditioning package also comprises:
The order split cells that is made of the CMOS logical circuit is between described definite type units and described ppu.
The adjustment boundary element that is made of the CMOS logical circuit is between described definite disappearance unit and described reading unit and described reading unit and described filler cells.
In one embodiment, described signal conditioning package also comprises:
The pre-fetch unit that is made of the CMOS logical circuit is between described definite disappearance unit and described reading unit;
First working storage that links to each other, is used to store reading order with described pre-fetch unit with described reading unit;
Link to each other, be used to store second working storage of filling order with described filler cells with described pre-fetch unit.
In one embodiment, described signal conditioning package also comprises: the 3rd working storage that is used to store missing data that links to each other with described reading unit, filler cells.
Compared with prior art, the technical solution of the utility model has the following advantages:
The utility model has designed a unified high-speed cache, can support the reference frame pixel and the 3D graphical textures of coding and decoding video simultaneously, compares the high-speed cache of other videos and texture separate storage, has saved chip area and chip power-consumption greatly.
In the possibility, also be provided with working storage, be used for the memory command formation, by sending reading order in advance and filling the mode of ordering, realized that video and texture are looked ahead and under the situation of cache miss, continued to send order, realize the high-speed cache of unblock, improved the reading speed of cache memory.
Description of drawings
Fig. 1 is the structural representation of signal conditioning package first embodiment of the present utility model;
Fig. 2 is the structural representation of signal conditioning package second embodiment of the present utility model;
Fig. 3 is the data organization form synoptic diagram of video pixel data among second embodiment shown in Figure 2;
Fig. 4 a, 4b are the data organization form synoptic diagram of graphical textures data among second embodiment shown in Figure 2.
Embodiment
A lot of details have been set forth in the following description so that fully understand the utility model.But the utility model can be implemented much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of the utility model intension, so the utility model is not subjected to the restriction of following public concrete enforcement.
Secondly, the utility model utilizes synoptic diagram to be described in detail, and when the utility model embodiment was described in detail in detail, for ease of explanation, described synoptic diagram was an example, and it should not limit the scope of the utility model protection at this.
In order to solve the technical matters in the background technology, the inventor finds: in System on Chip/SoC, coding and decoding video and 3D graphics process can't take place simultaneously, are example with the smart mobile phone: the operator can not watch film simultaneously and play games.Therefore can design a unified high-speed cache, support the reference frame pixel and the 3D graphical textures of coding and decoding video simultaneously.When carrying out the coding and decoding video processing, this high-speed cache is as the video pixel cache memory, and when carrying out the 3D graphics process, this high-speed cache can be used as texture cache again.By reusable high-speed cache, can save chip area greatly, reduced chip power-consumption simultaneously.
Therefore, the utility model provides a kind of signal conditioning package, is applicable to the high-speed cache of video pixel data or graphical textures data.Fig. 1 is the structural representation of signal conditioning package first embodiment of the present utility model.As shown in Figure 1, present embodiment comprises: cache memory Cache, determine type units U11, determine disappearance unit U12, reading unit U13, filler cells U14, be used for the external read command fetch cmd that sends according to described ppu (figure do not show), from chip external memory L2Cache, read in the missing data of data to be read in cache memory Cache, organize form to fill described cache memory Cache according to particular data, described cache memory Cache sends corresponding data to ppu (figure does not show) according to clock CLK rhythm.
Described cache memory Cache is used to store video pixel data or the graphical textures data that particular data is organized form.
Particularly, the particular data of described video pixel data organizes form to comprise: guarantee that per two clock period read all videos pixel component of a cache lines.Further, described video pixel data is a yuv format.The all videos pixel component that per two clock period of described assurance are read a cache lines comprises: guarantee that a clock period reads whole Y components of an alignment buffer, the next clock period is read whole U, V, the A component of described alignment buffer.
The particular data of described graphical textures data organizes form to comprise: guarantee that each clock period reads any four textures adjacent one another are.Described graphical textures data are the RGBA form.
Need to prove, described ppu can be any system level chip that needs configuration cache memory, such as: graphic operation unit (Graphics Processing Unit, GPU), Video Codec (video codec), image data processor (Image Signal Processor, ISP) etc., the utility model is not done concrete qualification to this.
Need to prove that the chip external memory L2Cache in the present embodiment is the level 2 buffering storer, but the utility model is not done concrete qualification to this, in other embodiments, chip external memory can also be an external storage.
Particularly, determine type units U11, constitute by the CMOS logical circuit, link to each other with ppu (figure does not show), be used to receive the external command cmd that described ppu sends, obtain data message to be read, what determine described data to be read is video pixel data or graphical textures data.Particularly, described data message to be read comprises: the capacity of the data type of data to be read, the address of data to be read, data to be read.
Determine disappearance unit U12, constitute by the CMOS logical circuit, link to each other with described definite type units U11 with speed buffering flag register Cache Tag, be used for according to described data message to be read and cache memory flag information, determine the missing data of described data to be read in described cache memory Cache.
Reading unit U13 is made of the CMOS logical circuit, and linking to each other with described definite disappearance unit U12 links to each other with chip external memory L2Cache, is used for reading in described missing data from chip external memory L2Cache.
Filler cells U14 is made of the CMOS logical circuit, links to each other with cache memory Cache with described reading unit U13, is used for described missing data is filled described cache memory Cache according to the data organization form of correspondence.
High-speed cache in the present embodiment both can be used as the high-speed cache of Video Codec, also can be used as the high-speed cache of 3 D graphics chip, so the signal conditioning package chip occupying area of present embodiment is littler, and required chip power-consumption is lower.
Fig. 2 is the structural representation of signal conditioning package second embodiment of the present utility model.The part identical with last embodiment repeats no more herein.Different with last embodiment is, the high-speed cache of present embodiment also can have been realized prefetched command by the configuration working storage, thereby avoid the obstruction of high-speed cache except can be multiplexing.As shown in Figure 2, present embodiment comprises: cache memory Cache, determine type units U201, determine disappearance unit U202, reading unit U203, filler cells U204, order split cells U205, pre-fetch unit U206, adjust boundary element U207, the first working storage U208, the second working storage U209, the 3rd working storage U210.
Described cache memory Cache is used to store video pixel data or the graphical textures data that particular data is organized form.
Determine type units U201, constitute by the CMOS logical circuit, link to each other, be used to receive the external command cmd that described ppu sends with ppu (figure does not show), obtain data message to be read, what determine described data to be read is video pixel data or graphical textures data.
Order split cells U205, constitute by the CMOS logical circuit, link to each other, be used for when the type of data to be read is video pixel data with described definite type units U201, with the capacity of data to be read, be split as one or more internal commands according to cache memory.
Determine disappearance unit U202, constitute by the CMOS logical circuit, link to each other with speed buffering flag register Cache Tag, described definite type units U201, described order split cells U205, be used for according to described data message to be read and cache memory flag information, determine the missing data of described data to be read in described cache memory Cache.
Pre-fetch unit U206, constitute by the CMOS logical circuit, link to each other with described definite disappearance unit U202, be used for described missing data ordering, form reading order formation Msg fifo and the corresponding ResMsg Queue of filling command queue, and will form missing data formation Data fifo according to the missing data ordering that described read command sequence is read in successively.
The first working storage U208 links to each other with described pre-fetch unit U206, is used to store described reading order formation Msg fifo.
The second working storage U28 links to each other with described pre-fetch unit U206, is used to store the described filling ResMsg Queue of command queue.
Reading unit U203, constitute by the CMOS logical circuit, link to each other with chip external memory L2 Cache with the described first working storage U208, be used for reading order according to head of the queue among the described first working storage U208 reading order formation Msgfifo, from chip external memory L2 Cache, read in described missing data, described missing data is come the tail of the queue of described missing data formation Data fifo.
The 3rd working storage U210 links to each other with described reading unit U203, is used to store described missing data formation.
Adjust boundary element U207, constitute by the CMOS logical circuit, link to each other with described pre-fetch unit U206, the first working storage U208, the 3rd working storage U210, filler cells U204, be used for when data to be read are video pixel data, before from chip external memory L2 Cache, reading in described missing data and with before the data organization form filling cache memory Cache of missing data according to correspondence, adjust the pixel image border.
Filler cells U204, constitute by the CMOS logical circuit, link to each other with cache memory Cache with the described second working storage U209, the 3rd working storage U210, adjustment boundary element U207, be used for filling the filling order of head of the queue among the ResMsg Queue of command queue, the missing data of head of the queue among the missing data formation Data fifo among described the 3rd working storage U210 is filled cache memory Cache according to the data organization form of correspondence according to the described second working storage U209.
Fig. 3 is the data organization form synoptic diagram of video pixel data among second embodiment shown in Figure 2.As shown in Figure 3, (BankA ~ BankD) form, each cache lines (Cacheline) is distributed in 4 SRAM storage arrays the high-speed cache of present embodiment by 4 SRAM storage arrays.When this speed buffering is used for the store video pixel data, comprise 128 cache lines altogether.
The form of the video pixel of present embodiment is YUVA4202, that is: the Y component keeps whole precision, U, V component are done the compression of 2:1 at transverse direction and longitudinal direction, the A component is done the compression of 2:1 at transverse direction, the YUVA4202 that obtains like this compares original YUVA and has reduced the storage space of half, and the picture quality influence is little.
Present embodiment is read whole Y components (as: data of entry0) of a Cacheline a clock period, reads whole U, V, the A component (as: data of entry1) of this Cacheline in another clock period.
Shown in Fig. 4 a is the displacement vector synoptic diagram of image texture data coordinates, and shown in Fig. 4 a, data texturing to be read is 4 texels of 16 х in the present embodiment.Because the texture in the 3D figure will be supported the mode of bilinear interpolation, require four texels adjacent one another are of disposable taking-up, therefore the inventor has stipulated the data organization form of graphical textures data, reads any four data texturings adjacent one another are to guarantee each clock period.Shown in Fig. 4 b to be the image texture data be stored in synoptic diagram in the speed buffering according to described data organization form.Shown in Fig. 4 b, still (BankA ~ BankD) form, each cache lines (Cacheline) is distributed in 4 SRAM storage arrays the high-speed cache of present embodiment by 4 SRAM storage arrays.When this speed buffering is used for the store video pixel data, comprise 64 cache lines altogether.Present embodiment is read four texels adjacent one another are (as: data of entry0) a clock period.
The course of work of the signal conditioning package of present embodiment is different according to the difference of data to be read.
The treatment scheme of graphical textures data comprises: receive the external read command fetch cmd that ppu (figure does not show) sends, through determining that type units U201 determines that data to be read are graphical textures data texture.Then, determine disappearance unit U202, produce and hit or signal such as disappearance, reading order is passed to pre-fetch unit U206 according to data message to be read and cache memory sign CacheTag information.According to the situation of disappearance, send out the request that chip external memory L2Cache gets data texturing in pre-fetch unit U206, these requests are stored among the first working storage U208 with formation form Msg fifo.In pre-fetch unit U206, corresponding filling order is stored among the second working storage U209 with formation form ResMsg Queue simultaneously.Then, reading unit U203 reads corresponding missing data according to the reading order of head of the queue in the Msg fifo formation in chip external memory L2Cache, and described missing data is come the tail of the queue of missing data formation Data fifo.Filler cells U204 orders the head of the queue of missing data formation Data fifo to obtain missing data to be filled according to the filling of head of the queue in the ResMsg Queue formation, and corresponding space among the filling cache memory Cache, from cache memory Cache, read required data texturing at last, give described ppu (figure does not show).
The treatment scheme of video pixel data is more complicated than the graphical textures data, specifically comprises: receive the external read command fetch cmd that ppu (figure does not show) sends, through determining that type units U201 determines that data to be read are video pixel data video.Then, the pixel region scope that order split cells U205 is required according to order produces one or more internal command, sends to determine disappearance unit U202.Determine disappearance unit U202 according to data message to be read and cache memory sign Cache Tag information, produce and hit or signal such as disappearance, reading order is passed to pre-fetch unit U206.After adjusting boundary element U207 adjustment pixel boundary, the situation according to disappearance sends out the request that chip external memory L2Cache gets video pixel data, and these requests are stored among the first working storage U208 with formation form Msg fifo.Simultaneously corresponding filling order is stored among the second working storage U209 with formation form ResMsg Queue.Then, reading unit U203 reads corresponding missing data according to the reading order of head of the queue in the Msg fifo formation in chip external memory L2Cache, and described missing data is come the tail of the queue of missing data formation Data fifo.After adjusting boundary element U207 adjustment pixel boundary, filler cells U204 orders the head of the queue of missing data formation Data fifo to obtain missing data to be filled according to the filling of head of the queue in the ResMsgQueue formation, and corresponding space among the filling cache memory Cache, from cache memory Cache, read required video pixel data at last, give described ppu (figure does not show).
Present embodiment is by storing reading order and filling order according to the formation form, carry out reading order according to the order of sequence and fill order, thereby realize prefetched command in advance, the reading speed of cache memory is provided, can avoids simultaneously because of reading order and fill the obstruction of the high-speed cache that the conflict between order causes.
Need to prove, it will be appreciated by those skilled in the art that, above-mentioned part assembly can be such as programmable logic array (Programmable Array Logic, PAL), generic array logic (Generic Array Logic, GAL), field programmable gate array (Field-Programmable Gate Array, FPGA), CPLD (Complex Programmable Logic Device, in the programmable logic device (PLD) one or more such as CPLD), but the utility model is not done concrete restriction to this.
Though the utility model with preferred embodiment openly as above; but it is not to be used for limiting the utility model; any those skilled in the art are not in breaking away from spirit and scope of the present utility model; can utilize the method and the technology contents of above-mentioned announcement that technical solutions of the utility model are made possible change and modification; therefore; every content that does not break away from technical solutions of the utility model; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical solutions of the utility model according to technical spirit of the present utility model.
Claims (6)
1. signal conditioning package is applicable to it is characterized in that the high-speed cache of video pixel data or graphical textures data, comprising:
Cache memory;
Definite type units by the CMOS logical circuit constitutes links to each other with ppu;
Definite short-landing account unit by the CMOS logical circuit constitutes links to each other with described definite type units;
Reading unit by the CMOS logical circuit constitutes links to each other with described definite disappearance unit and chip external memory;
Filler cells by the CMOS logical circuit constitutes links to each other with described reading unit and described cache memory.
2. signal conditioning package according to claim 1 is characterized in that described signal conditioning package also comprises: clock generation unit; Described cache configuration becomes to guarantee that per two clock period read all videos pixel component of a cache lines, guarantees that perhaps each clock period reads any four data texturings adjacent one another are.
3. any signal conditioning package according to claim 1 and 2 is characterized in that, described chip external memory comprises: one or more in external storage, the level 2 buffering storer.
4. signal conditioning package according to claim 3 is characterized in that, described signal conditioning package also comprises:
The order split cells that is made of the CMOS logical circuit is between described definite type units and described ppu;
The adjustment boundary element that is made of the CMOS logical circuit is between described definite disappearance unit and described reading unit and described reading unit and described filler cells.
5. signal conditioning package according to claim 3 is characterized in that, described signal conditioning package also comprises:
The pre-fetch unit that is made of the CMOS logical circuit is between described definite disappearance unit and described reading unit;
First working storage that links to each other, is used to store reading order with described pre-fetch unit with described reading unit;
Link to each other, be used to store second working storage of filling order with described filler cells with described pre-fetch unit.
6. signal conditioning package according to claim 5 is characterized in that, described signal conditioning package also comprises: the 3rd working storage that is used to store missing data that links to each other with described reading unit, filler cells.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012207496485U CN203102260U (en) | 2012-12-31 | 2012-12-31 | Information processing device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012207496485U CN203102260U (en) | 2012-12-31 | 2012-12-31 | Information processing device |
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| CN203102260U true CN203102260U (en) | 2013-07-31 |
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| CN2012207496485U Expired - Lifetime CN203102260U (en) | 2012-12-31 | 2012-12-31 | Information processing device |
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Effective date of registration: 20220725 Address after: 200120 room 11F, building 2, Lane 560, shengxia Road, Pudong New Area, Shanghai Patentee after: GALAXYCORE SHANGHAI Ltd.,Corp. Address before: Room 1004 and room 1005, building 2, No. 560, shengxia Road, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI SUANXIN MICROELECTRONICS Co.,Ltd. |
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