CN203102261U - Information processing device - Google Patents

Abstract

The utility model discloses an information processing device which is applicable to a high-speed cache which can be pre-fetched. The information processing device comprises a high-speed buffer memory, a determination missing unit, a pre-fetching unit, a first transient memory, a reading unit, a second transient memory and a filling unit, wherein the determination missing unit is composed of a complementary metal-oxide-semiconductor transistor (CMOS) logic circuit and connected with an external processor and the high-speed buffer memory, the pre-fetching unit is composed of a CMOS logic circuit and located between the determination missing unit and the reading unit, the first transient memory is connected with the pre-fetching unit and the reading unit and used for storing reading commands, the reading unit is composed of a CMOS logic circuit and connected with the first transient memory and an off-chip memory, the second transient memory is connected with the pre-fetching unit and the filling unit and used for storing filling commands, and the filling unit is composed of a CMOS logic circuit and connected with the reading unit, the second transient memory and the high-speed buffer memory. The information processing device can avoid or reduce the congestion phenomenon of the high-speed buffer memory, thereby improving the processing speed of a system chip.

Description

Signal conditioning package

Technical field

The utility model relates to field of digital information processing, relates in particular to a kind of signal conditioning package of looking ahead.

Background technology

In the technical development of computer process, the access speed of internal memory always than the CPU processing speed slowly many, make the high speed processing ability of CPU not give full play to, influence the work efficiency of whole computer system.Cache memory is used to relax the unmatched contradiction of speed between CPU and the internal memory.Adopt the cache memory technology quite general at present.Cache memory is the single-level memory that is present between internal memory and the CPU, and (SRAM) forms by the static store chip, and volume ratio is less, but its access speed can be complementary with CPU.According to the program locality principle, those unit of a certain unit of the internal memory that is using vicinity are very big with the possibility that is used to.Thereby, when a certain unit of CPU access memory, computer hardware is called in cache memory with regard to that group location contents that automatically will comprise this unit, and CPU is about to the internal storage location of access probably just in just calling in that group unit of cache memory.So CPU just can directly carry out access to cache memory.In the entire process process, if the operation of the most access memory of CPU can be replaced by access cache, computer system processor speed just can significantly improve.

In video encoding-decoding process, video pixel (mainly being the reference frame pixel) need take a large amount of memory bandwidth, is coding and decoding video committed memory bandwidth the best part.Existing coding and decoding video chip majority all uses high-speed cache on the sheet (Cache) to come the storage of reference frames pixel, thereby reduces memory bandwidth, reduces access delay simultaneously.

And in 3 D graphics chip, texture also is a committed memory bandwidth the best part.Existing 3 D graphics chip also all adopts on the sheet texture caching to store texture, thereby reduces memory bandwidth, reduces access delay.

The inventor finds: at existing systems chip (System-on-a-chip, SoC) in, especially in the System on Chip/SoC that the committed memory bandwidth is bigger, the obstruction of cache memory has become the bottleneck of restriction processing speed, and then makes the overall performance of System on Chip/SoC be subject to the access speed of internal memory.

Therefore, solve the jam of cache memory, become the technical barrier that those skilled in the art need to be resolved hurrily.

At publication number is in the Chinese invention patent application of CN101057224A, has disclosed more heterogeneous pass content.

The utility model content

Technical problem to be solved in the utility model provides a kind of cache memory, can avoid or reduce jam, thereby improves the processing speed of System on Chip/SoC.

In order to address the above problem, according to an aspect of the present utility model, provide a kind of signal conditioning package, be applicable to looking ahead of high-speed cache, comprising:

Cache memory;

Definite short-landing account unit by the CMOS logical circuit constitutes links to each other with described cache memory with ppu;

The pre-fetch unit that is made of the CMOS logical circuit is between described definite disappearance unit and reading unit;

First working storage that links to each other, is used to store reading order with described pre-fetch unit with described reading unit;

Reading unit by the CMOS logical circuit constitutes links to each other with described first working storage and chip external memory;

Link to each other, be used to store second working storage of filling order with filler cells with described pre-fetch unit;

Filler cells by the CMOS logical circuit constitutes links to each other with described reading unit, described second working storage and described cache memory.

In one embodiment, described signal conditioning package also comprises: the 3rd working storage that links to each other, is used to store missing data with described reading unit, filler cells;

Described filler cells links to each other with described the 3rd working storage, described second working storage and described cache memory.

In one embodiment, described chip external memory comprises: one or more in external storage, the level 2 buffering storer.

In one embodiment, described signal conditioning package also comprises:

The definite type units that is made of the CMOS logical circuit is between described ppu and described definite disappearance unit.

In one embodiment, described signal conditioning package also comprises: clock generation unit; Described cache configuration becomes to guarantee that per two clock period read all videos pixel component of a cache lines, guarantees that perhaps each clock period reads any four data texturings adjacent one another are.

In one embodiment, described signal conditioning package also comprises:

The order split cells that is made of the CMOS logical circuit is between described definite type units and described definite disappearance unit.

First adjust boundary element by what the CMOS logical circuit constituted, between described pre-fetch unit and described reading unit;

Second adjust boundary element by what the CMOS logical circuit constituted, between described reading unit and described filler cells.

Compared with prior art, the technical solution of the utility model has the following advantages:

The utility model is by being provided with command queue, send reading order in advance and fill the mode of ordering, guaranteed under the situation of cache miss, can also continue to send order, the high-speed cache of unblock and looking ahead of missing data have been realized, improve the reading speed of cache memory, and then improved the bulk treatment speed of System on Chip/SoC.

In the possibility, also by the video pixel data of storing in the regulation cache memory and the data organization form of graphical textures data, and organize form to fill cache memory according to described particular data the missing data, make and use same cache memory just can realize coding and decoding video reference frame pixel and 3D graphical textures high-speed cache, further saved chip area and chip power-consumption.

Description of drawings

Fig. 1 is the structural representation of signal conditioning package first embodiment of the present utility model;

Fig. 2 is the structural representation of signal conditioning package second embodiment of the present utility model;

Fig. 3 is the data organization form synoptic diagram of video pixel data among second embodiment shown in Figure 2;

Fig. 4 a, 4b are the data organization form synoptic diagram of graphical textures data among second embodiment shown in Figure 2.

Embodiment

A lot of details have been set forth in the following description so that fully understand the utility model.But the utility model can be implemented much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of the utility model intension, so the utility model is not subjected to the restriction of following public concrete enforcement.

Secondly, the utility model utilizes synoptic diagram to be described in detail, and when the utility model embodiment was described in detail in detail, for ease of explanation, described synoptic diagram was an example, and it should not limit the scope of the utility model protection at this.

In order to solve the technical matters in the background technology, the utility model also provides a kind of signal conditioning package, is applicable to the high-speed cache of video pixel data or graphical textures data.Fig. 1 is the structural representation of signal conditioning package first embodiment of the present utility model.As shown in Figure 1, present embodiment comprises: cache memory Cache, definite disappearance unit U101, pre-fetch unit U102, reading unit U103, filler cells U104, the first working storage U105, the second working storage U106, the 3rd working storage U107, be used for the external read command fetch cmd that sends according to ppu (figure do not show), obtain data message to be read, according to data message to be read and cache memory sign Cache Tag information, determine the missing data of described data to be read in described cache memory Cache; With described missing data ordering, form reading order formation Msg fifo and the corresponding ResMsg Queue of filling command queue; From chip external memory L2Cache, read in described missing data successively according to described reading order formation Msg fifo; Successively described missing data is filled described cache memory Cache according to the described filling ResMsg Queue of command queue, described cache memory Cache sends corresponding data to ppu (figure does not show) according to clock CLK rhythm.

Described cache memory Cache is used to store video pixel data or the graphical textures data that particular data is organized form.

Need to prove, described ppu can be any system level chip that needs configuration cache memory, such as: graphic operation unit (Graphics Processing Unit, GPU), Video Codec (video codec), image data processor (Image Signal Processor, ISP) etc., the utility model is not done concrete qualification to this.

Need to prove that the chip external memory L2Cache in the present embodiment is the level 2 buffering storer, but the utility model is not done concrete qualification to this, in other embodiments, chip external memory can also be an external storage.

The described first working storage U105 is used to store reading order formation Msg fifo.

The described second working storage U106 is used for storage and fills the ResMsg Queue of command queue.

Described the 3rd working storage U107 is used to store missing data formation Data fifo.

Determine disappearance unit U101, link to each other with ppu (figure does not show) with speed buffering flag register Cache Tag, be used for according to external read command fetch cmd, obtain data message to be read, according to data message to be read and cache memory sign Cache Tag information, determine the missing data of described data to be read in described cache memory Cache.

Pre-fetch unit U102, link to each other with described definite disappearance unit U101, the first working storage U105, the second working storage U106, be used for described missing data ordering, form reading order formation Msg fifo and the corresponding ResMsg Queue of filling command queue, and, form missing data formation Data fifo with described missing data ordering of reading in.

Reading unit U103, link to each other with the described first working storage U105, chip external memory L2Cache, the 3rd working storage U107, be used for from chip external memory L2Cache, reading in missing data, and described missing data come the tail of the queue of described missing data formation Data fifo according to the reading order of described reading order formation Msg fifo head of the queue.

Filler cells U104, link to each other with cache memory Cache with described the 3rd working storage U107, be used for obtaining missing data from the head of the queue of described missing data formation Data fifo, described missing data is filled described cache memory Cache according to the filling order of the described filling ResMsg Queue of command queue head of the queue.

Present embodiment is by being provided with command queue and data queue, realize sending in advance reading order and filled order, thereby realized looking ahead of missing data, avoid or reduced the jam of cache memory, improve the reading speed of cache memory, and then improved the bulk treatment speed of System on Chip/SoC.

Fig. 2 is the structural representation of signal conditioning package second embodiment of the present utility model.The part identical with last embodiment repeats no more herein.Different with last embodiment is, the signal conditioning package of present embodiment has also been realized the reusable of cache memory, thereby significantly reduced chip area except avoiding or reduce the blocking up of cache memory, reduced chip power-consumption.As shown in Figure 2, present embodiment comprises: cache memory Cache, determine disappearance unit U201, pre-fetch unit U202, reading unit U203, filler cells U204, the first working storage U205, the second working storage U206, the 3rd working storage U207, determine type units U208, order split cells U209, adjust boundary element U210.

Particularly, described data to be read are video pixel data or graphical textures data.Described cache memory Cache is used to store video pixel data or the graphical textures data that particular data is organized form.

Particularly, the data organization form of video pixel data in cache memory comprises: guarantee that per two clock period read all videos pixel component of a cache lines (Cache line).In the present embodiment, described video pixel data is a yuv format, luminance component Y: chromatic component U: the data volume ratio of chromatic component V: transparency component A is 4:1:1:2.So all videos pixel component that per two clock period are read a cache lines reads whole U, V, the A component of described alignment buffer for read whole Y components of an alignment buffer a clock period in the next clock period.

Particularly, because the texture format in the 3D graph processing chips has nothing in common with each other, modal is the RGBA form.Therefore, the data organization form of graphical textures data in cache memory comprises: guarantee that each clock period reads any four data texturings adjacent one another are, need with the bilinear interpolation of supporting data texturing.

Determine type units U208, link to each other, be used to receive the external command cmd that described ppu sends that obtain data message to be read, what determine described data to be read is video pixel data or graphical textures data with ppu (figure does not show).Particularly, described data message to be read comprises: the capacity of the data type of data to be read, the address of data to be read, data to be read.

Order split cells U209 links to each other with described definite type units U208, is used for when the type of data to be read is video pixel data, according to the capacity of cache memory, described external read command fetch is split as one or more internal commands.

Determine disappearance unit U201, link to each other with speed buffering flag register Cache Tag, described definite type units U208, described order split cells U209, be used for according to described data message to be read and cache memory flag information, determine the missing data of described data to be read in described cache memory Cache.

Pre-fetch unit U202, link to each other with described definite disappearance unit U201, be used for described missing data ordering, form reading order formation Msg fifo and the corresponding ResMsg Queue of filling command queue, and will form missing data formation Data fifo according to the missing data ordering that described read command sequence is read in successively.

The first working storage U205 links to each other with described pre-fetch unit U202, is used to store described reading order formation Msg fifo.

The second working storage U206 links to each other with described pre-fetch unit U202, is used to store the described filling ResMsg Queue of command queue.

Reading unit U203, link to each other with chip external memory L2Cache with the described first working storage U205, the 3rd working storage U207, be used for reading order according to head of the queue among the described first working storage U205 reading order formation Msg fifo, from chip external memory L2Cache, read in described missing data, described missing data is come the tail of the queue of described missing data formation Data fifo.

Described the 3rd working storage U207 links to each other with described reading unit U203, is used to store described missing data formation Data fifo.

Adjust boundary element U210, link to each other with described pre-fetch unit U202, the described first working storage U205, described the 3rd working storage U207, filler cells U204, be used for when data to be read are video pixel data, before from chip external memory L2Cache, reading in described missing data and with before the data organization form filling cache memory Cache of missing data according to correspondence, adjust the pixel image border.

Filler cells U204, link to each other with described cache memory Cache with the described second working storage U206, described the 3rd working storage U207, described adjustment boundary element U210, be used for filling the filling order of head of the queue among the ResMsg Queue of command queue, the missing data of head of the queue among the missing data formation Data fifo among described the 3rd working storage U207 is filled cache memory Cache according to the data organization form of correspondence according to the described second working storage U206.

Fig. 3 is the data organization form synoptic diagram of video pixel data among second embodiment shown in Figure 2.As shown in Figure 3, (BankA ~ BankD) form, each cache lines (Cacheline) is distributed in 4 SRAM storage arrays the high-speed cache of present embodiment by 4 SRAM storage arrays.When this speed buffering is used for the store video pixel data, comprise 128 cache lines altogether.

The form of the video pixel of present embodiment is YUVA4202, that is: the Y component keeps whole precision, U, V component are done the compression of 2:1 at transverse direction and longitudinal direction, the A component is done the compression of 2:1 at transverse direction, the YUVA4202 that obtains like this compares original YUVA and has reduced the storage space of half, and the picture quality influence is little.

Present embodiment is read whole Y components (as: data of entry0) of a Cacheline a clock period, reads whole U, V, the A component (as: data of entry1) of this Cacheline in another clock period.

Shown in Fig. 4 a is the displacement vector synoptic diagram of image texture data coordinates.Shown in Fig. 4 a, data texturing to be read is 4 texels of 16 х in the present embodiment.Because the texture in the 3D figure will be supported the mode of bilinear interpolation, require four texels adjacent one another are of disposable taking-up, therefore the inventor has stipulated the data organization form of graphical textures data, reads any four data texturings adjacent one another are to guarantee each clock period.Shown in Fig. 4 b to be the image texture data be stored in synoptic diagram in the speed buffering according to described data organization form.Shown in Fig. 4 b, still (BankA ~ BankD) form, each cache lines (Cacheline) is distributed in 4 SRAM storage arrays the high-speed cache of present embodiment by 4 SRAM storage arrays.When this speed buffering is used for the store video pixel data, comprise 64 cache lines altogether.Present embodiment is read four texels adjacent one another are (as: data of entry0) a clock period.

The course of work of the signal conditioning package of present embodiment is different according to the difference of data to be read.

The treatment scheme of graphical textures data comprises: receive the external read command fetch cmd that ppu (figure does not show) sends, through determining that type units U208 determines that data to be read are graphical textures data texture.Then, determine disappearance unit U201, produce and hit or signal such as disappearance, reading order is passed to pre-fetch unit U202 according to data message to be read and cache memory sign Cache Tag information.According to the situation of disappearance, send out the request that chip external memory L2Cache gets data texturing in pre-fetch unit U202, these requests are stored among the first working storage U205 with formation form Msg fifo.In pre-fetch unit U202, corresponding filling order is stored among the second working storage U206 with formation form ResMsg Queue simultaneously.Then, reading unit U203 reads corresponding missing data according to the reading order of head of the queue in the Msg fifo formation in chip external memory L2Cache, and described missing data is come the tail of the queue of missing data formation Data fifo.Filler cells U204 orders the head of the queue of missing data formation Data fifo to obtain missing data to be filled according to the filling of head of the queue in the ResMsg Queue formation, and corresponding space among the filling cache memory Cache, from cache memory Cache, read required data texturing at last, give described ppu (figure does not show).

The treatment scheme of video pixel data is more complicated than the graphical textures data, specifically comprises: receive the external read command fetch cmd that ppu (figure does not show) sends, through determining that type units U208 determines that data to be read are video pixel data video.Then, the pixel region scope that order split cells U209 is required according to order produces one or more internal command, sends to determine disappearance unit U201.Determine disappearance unit U201 according to data message to be read and cache memory sign Cache Tag information, produce and hit or signal such as disappearance, reading order is passed to pre-fetch unit U202.After adjusting boundary element U210 adjustment pixel boundary, the situation according to disappearance sends out the request that chip external memory L2Cache gets video pixel data, and these requests are stored among the first working storage U205 with formation form Msg fifo.Simultaneously corresponding filling order is stored among the second working storage U206 with formation form ResMsg Queue.Then, reading unit U203 reads corresponding missing data according to the reading order of head of the queue in the Msg fifo formation in chip external memory L2Cache, and described missing data is come the tail of the queue of missing data formation Data fifo.After adjusting boundary element U210 adjustment pixel boundary, filler cells U204 orders the head of the queue of missing data formation Data fifo to obtain missing data to be filled according to the filling of head of the queue in the ResMsg Queue formation, and corresponding space among the filling cache memory Cache, from cache memory Cache, read required video pixel data at last, give described ppu (figure does not show).

High-speed cache in the present embodiment both can be used as the high-speed cache of Video Codec, also can be used as the high-speed cache of 3 D graphics chip, so the signal conditioning package chip occupying area of present embodiment is littler, and required chip power-consumption is lower.

Need to prove, it will be appreciated by those skilled in the art that, above-mentioned part assembly can be such as programmable logic array (Programmable Array Logic, PAL), generic array logic (Generic Array Logic, GAL), field programmable gate array (Field-Programmable Gate Array, FPGA), CPLD (Complex Programmable Logic Device, in the programmable logic device (PLD) one or more such as CPLD), but the utility model is not done concrete restriction to this.

Though the utility model with preferred embodiment openly as above; but it is not to be used for limiting the utility model; any those skilled in the art are not in breaking away from spirit and scope of the present utility model; can utilize the method and the technology contents of above-mentioned announcement that technical solutions of the utility model are made possible change and modification; therefore; every content that does not break away from technical solutions of the utility model; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical solutions of the utility model according to technical spirit of the present utility model.

Claims (6)

1. a signal conditioning package is applicable to looking ahead of high-speed cache, it is characterized in that, comprising:

Cache memory;

Definite short-landing account unit by the CMOS logical circuit constitutes links to each other with described cache memory with ppu;

The pre-fetch unit that is made of the CMOS logical circuit is between described definite disappearance unit and reading unit;

First working storage that links to each other, is used to store reading order with described pre-fetch unit with described reading unit;

Reading unit by the CMOS logical circuit constitutes links to each other with described first working storage and chip external memory;

Link to each other, be used to store second working storage of filling order with filler cells with described pre-fetch unit;

Filler cells by the CMOS logical circuit constitutes links to each other with described reading unit, described second working storage and described cache memory.

2. signal conditioning package according to claim 1 is characterized in that, described signal conditioning package also comprises: the 3rd working storage that links to each other, is used to store missing data with described reading unit, filler cells;

Described filler cells links to each other with described the 3rd working storage, described second working storage and described cache memory.

3. any signal conditioning package according to claim 1 and 2 is characterized in that, described chip external memory comprises: one or more in external storage, the level 2 buffering storer.

4. signal conditioning package according to claim 3 is characterized in that, described signal conditioning package also comprises:

The definite type units that is made of the CMOS logical circuit is between described ppu and described definite disappearance unit.

5. signal conditioning package according to claim 4 is characterized in that described signal conditioning package also comprises: clock generation unit; Described cache configuration becomes to guarantee that per two clock period read all videos pixel component of a cache lines, guarantees that perhaps each clock period reads any four data texturings adjacent one another are.

6. signal conditioning package according to claim 5 is characterized in that, described signal conditioning package also comprises:

The order split cells that is made of the CMOS logical circuit is between described definite type units and described definite disappearance unit.

First adjust boundary element by what the CMOS logical circuit constituted, between described pre-fetch unit and described reading unit;

Second adjust boundary element by what the CMOS logical circuit constituted, between described reading unit and described filler cells.

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