CN203014746U - Amplifier - Google Patents

Abstract

The utility model provides an amplifier which comprises a current generating circuit, a current mirror image circuit and an amplifying circuit. The current generating circuit is respectively connected with an external power supply and the current mirror image circuit, the current mirror image circuit is respectively connected with the external power supply and an amplifier circuit, and the amplifying circuit is connected with an external signal input end and a signal output end. The amplifying circuit comprises a third field-effect tube, a fourth field-effect tube and two loading resistors, wherein the third field-effect tube and the fourth field-effect tube are respectively connected with the current mirror image circuit, the external signal input end, the signal output end and one loading resistor, and a second field-effect tube, the third field-effect tube and the fourth field-effect tube have identical parameter characteristics. The amplifier has the advantages of being simple in structure, stable and accurate in yield value, wherein the yield value can not change along with changes of temperature and a process corner, and capable of ensuring stability of signals after the signals are amplified by the amplifier.

Description

Amplifier

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of amplifier.

Background technology

Operational amplifier is mainly that the signal of telecommunication is carried out computing and amplification, therefore is widely used in each electronic device.As everyone knows, the inside of operational amplifier includes a plurality of field effect transistor, and the parameter such as carrier mobility of field effect transistor, threshold voltage can be with the variation of temperature and process corner difference, this gain that will cause operational amplifier is also along with changing, i.e. there is unsettled hidden danger in the gain of operational amplifier.In the prior art, the increase negative feedback networks that adopt reduce technological parameter to the impact of gain more, but this kind mode need to be added extra device in circuit, not only makes whole amplifier architecture complicated, and can not avoid technological parameter on the impact of gain fully.

Therefore, be necessary to provide a kind of simple in structure, can make the gain of amplifier not be subjected to the amplifier of the effects of process parameters such as mobility, threshold voltage, temperature to overcome defects.

The utility model content

The purpose of this utility model is to provide a kind of amplifier, and described amplifier architecture is simple, and has stable and accurate yield value, and its gain can with the variation of temperature and process corner, not guarantee the stability through the amplifier amplified signal.

for achieving the above object, the utility model provides a kind of amplifier, this amplifier comprises current generating circuit, current mirror circuit and amplifying circuit, described current generating circuit comprises the first field effect transistor, the second field effect transistor and the first resistance, described the first field effect transistor respectively with external power source, described the second field effect transistor and described current mirror circuit connect, described the first resistance is connected with described external power source and described the second field effect transistor respectively, described the second field effect transistor also is connected with described current mirror circuit, input to described current mirror circuit with the electric current that described current generating circuit is produced, described current mirror circuit also is connected with external power source and described amplifying circuit respectively, described current mirror circuit amplifies 2 times and input to described amplifying circuit with the current mirror of described current generating circuit output, described amplifying circuit is connected with external signal input and signal output part, and described amplifying circuit comprises the 3rd field effect transistor, the 4th field effect transistor and two load resistances, described the 3rd field effect transistor, the 4th field effect transistor respectively with described current mirror circuit, the external signal input, signal output part and a load resistance connect, described the 3rd field effect transistor and the 4th field effect transistor are amplified the signal of outside signal input part input, and the signal after amplifying by described signal output part output, and described the second field effect transistor, the 3rd field effect transistor and the 4th field effect transistor have identical parameter attribute.

preferably, described current mirror circuit comprises the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and the 9th field effect transistor, the source electrode of described the 7th field effect transistor, the source ground of described the 8th field effect transistor source electrode and described the 9th field effect transistor, the drain electrode of described the 7th field effect transistor is connected with the drain and gate of described the first field effect transistor, the grid of described the 8th field effect transistor and drain electrode, the grid of the grid of the 7th field effect transistor and the 9th field effect transistor is connected with the drain electrode of described the second field effect transistor, the drain electrode of described the 9th field effect transistor is connected jointly with the grid of described the 5th field effect transistor and the grid of drain electrode and the 6th field effect transistor, described the 5th field effect transistor, the source electrode of described the 6th field effect transistor all is connected with described external power source, the drain electrode of described the 6th field effect transistor is connected with the source electrode of described the 3rd field effect transistor and the source electrode of described the 4th field effect transistor respectively.

Preferably, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor, and the breadth length ratio of described the 9th field effect transistor is 2 times of described the 8th field effect transistor breadth length ratio, and described the 5th field effect transistor equates with the breadth length ratio of the 6th field effect transistor.

Preferably, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor, the breadth length ratio of described the 9th field effect transistor equates with described the 8th field effect transistor breadth length ratio, and the breadth length ratio of described the 6th field effect transistor is 2 times of described the 5th field effect transistor breadth length ratio.

Preferably, the source electrode of described the first field effect transistor is connected with described external power source, its grid is connected jointly with the grid of drain electrode with described the second field effect transistor, and be connected with the drain electrode of described the 7th field effect transistor, described the first resistance one end is connected with external power source, the other end is connected with the source electrode of the second field effect transistor, and the drain electrode of described the second field effect transistor is connected with the drain electrode of described the 8th field effect transistor.

Preferably, the breadth length ratio of described the second field effect transistor is N times of described the first field effect transistor breadth length ratio, and N is integer, and N 〉=2.

Preferably, the source electrode of described the 3rd field effect transistor and the 4th field effect transistor all is connected with the drain electrode of described the 6th field effect transistor, the grid of described the 3rd field effect transistor is connected with the positive input of external signal input, its drain electrode is connected with an end of a load resistance and the forward output of signal output part, the grid of described the 4th field effect transistor is connected with the reverse input end of external signal input, its drain electrode is connected with the inverse output terminal of another load resistance and signal output part, and the equal ground connection of the other end of two described load resistances.

compared with prior art, described amplifier of the present utility model is because the current mirror of described current mirror circuit with described current generating circuit output is 2 times and inputs to described amplifying circuit, and the 3rd field effect transistor and the 4th field effect transistor of described the second field effect transistor and described amplifying circuit have identical parameter attribute, make and flow through described the second field effect transistor, the current value of the 3rd field effect transistor and the 4th field effect transistor is identical, the mutual conductance of three field effect transistor is also identical, thereby the gain of the amplifying circuit that is obtained by the long-pending of the load resistance of the mutual conductance of described the 3rd field effect transistor or the 4th field effect transistor and its drain electrode is an amount that has nothing to do with the field effect transistor mutual conductance, therefore the gain of amplifier of the present utility model is stable and smart, gain can be with the variation of temperature and process corner, guaranteed the stability through the amplifier amplified signal.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Description of drawings

Fig. 1 is the structured flowchart of the utility model amplifier.

Fig. 2 is the circuit theory diagrams of the utility model amplifier.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similar element numbers represents similar element.As mentioned above, the utility model provides a kind of amplifier, and described amplifier architecture is simple, and has stable and accurate yield value, and its gain can with the variation of temperature and process corner, not guarantee the stability through the amplifier amplified signal.

Please refer to Fig. 1, Fig. 1 is the structured flowchart of the utility model amplifier.As shown in the figure, amplifier of the present utility model comprises current generating circuit, current mirror circuit and amplifying circuit; Described current generating circuit is connected with external power source and current mirror circuit respectively, producing the required electric current of described amplifier normal operation, and the electric current that produces is sent to described current mirror circuit; Described current mirror circuit is connected with external power source and amplifying circuit respectively, the current mirror that described current mirror circuit produces described current generating circuit is that the electric current of corresponding multiple is delivered to described amplifying circuit, thinks that described amplifying circuit provides normal operating current; Described amplifying circuit also is connected with external signal input and signal output part respectively, and described amplifying circuit requires to amplify to the signal sets of outside signal input part input, and the signal after amplifying by described signal output part output.

Particularly, please combination is with reference to figure 2 again, and Fig. 2 is the circuit theory diagrams of the utility model amplifier.

Described current generating circuit comprises the first field effect transistor M1, the second field effect transistor M2 and the first resistance R 0; The source electrode of described the first field effect transistor M1 is connected with external power source VCC, and the grid of its grid, drain electrode and described the second field effect transistor M2 connects jointly, and is connected with described current mirror circuit; Described the first resistance R 0 one ends are connected with external power source VCC, and the other end is connected with the source electrode of described the second field effect transistor M2, and the drain electrode of described the second field effect transistor M2 is connected with described current mirror circuit; Thereby described the first field effect transistor M1, the second field effect transistor M2 and the first resistance R 0 coordinate the voltage that provides by external power source VCC and electrogenesis stream I0; In addition, in preferred embodiment of the present utility model, the breadth length ratio of described the second field effect transistor M2 is N times of described the first field effect transistor M1 breadth length ratio, and N is integer, and N 〉=2, makes

$I0=\frac{\mathrm{Vsg}1-\mathrm{Vsg}2}{R0}=\frac{(\sqrt{N}-1)(\mathrm{Vsg}2-|\mathrm{Vthp}\left|\right)}{R0}---\left(1\right)$

Wherein Vsg1 is the source gate voltage of the first field effect transistor M1, and Vsg2 is the source gate voltage of the second field effect transistor M2, and Vthp is the threshold voltage of the second field effect transistor M2.

The gm2 that is cross over because of the second field effect transistor M2 is again

$\mathrm{gm}2=\frac{2*I0}{\mathrm{Vsg}2-\left|\mathrm{Vthp}\right|}---\left(2\right)$

Convolution (1) can draw,

$\mathrm{gm}2=\frac{2*(\sqrt{N}-1)}{R0}---\left(3\right)$

described current mirror circuit comprises the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8 and the 9th field effect transistor M9, described the 7th field effect transistor M7, the source grounding of the 8th field effect transistor M8 and the 9th field effect transistor M9, the drain electrode of described the 7th field effect transistor M7 is connected with the drain electrode of described the first field effect transistor M1, the grid of described the 8th field effect transistor M8, drain electrode, the grid of the grid of the 7th field effect transistor M7 and the 9th field effect transistor M9 connects jointly, and the grid of described the 8th field effect transistor M8, drain electrode is connected with the drain electrode of described the second field effect transistor M2, thereby the electric current I 0 that described current generating circuit produces is from the grid of described the 8th field effect transistor M8, drain electrode inputs to described current mirror circuit, the drain electrode of described the 9th field effect transistor M9 is connected jointly with the grid of grid, drain electrode and the 6th field effect transistor M6 of described the 5th field effect transistor M5, the source electrode of described the 5th field effect transistor M5, the 6th field effect transistor M6 all is connected with external power source VCC, and the drain electrode of described the 6th field effect transistor M6 is connected with described amplifying circuit, thereby by described current mirror circuit, described the 9th field effect transistor M9 is I1 with electric current I 0 mirror image on described the 8th field effect transistor M8, and makes the electric current on described the 5th field effect transistor M5 also be I1, and described the 6th field effect transistor M6 is electric current I 2 with electric current I 1 mirror image on described the 5th field effect transistor M5, wherein, the mirror image ratio of electric current I 0 and electric current I 1 is by the ratio-dependent of the breadth length ratio of the breadth length ratio of described the 8th field effect transistor M8 and the 9th field effect transistor M9, correspondingly, the mirror image ratio of electric current I 1 and electric current I 2 is by the ratio-dependent of the breadth length ratio of the breadth length ratio of described the 5th field effect transistor M5 and the 6th field effect transistor M6, and in the utility model, through after the mirror image effect of described current mirror circuit, its output current is 2 times of input current, be I2=2*I0, and arrow shown in Fig. 2 is each sense of current.Wherein, in an embodiment of the present utility model, described the 7th field effect transistor M7 has identical breadth length ratio with the 8th field effect transistor M8, and the breadth length ratio of described the 9th field effect transistor M9 is 2 times of described the 8th field effect transistor M8 breadth length ratio, thereby makes I1=2*I0; And described the 5th field effect transistor M5 equates with the breadth length ratio of the 6th field effect transistor M6, thereby I2=I1=2*I0.In addition, in another embodiment of the present utility model, described the 7th field effect transistor M7 has identical breadth length ratio with the 8th field effect transistor M8, the breadth length ratio of described the 9th field effect transistor M7 equates with described the 8th field effect transistor M8 breadth length ratio, be I1=2*I0, and the breadth length ratio of described the 6th field effect transistor M6 is 2 times of described the 5th field effect transistor M5 breadth length ratio, i.e. I2=2*I1=2*I0.

Described amplifying circuit comprises the 3rd field effect transistor M3, the 4th field effect transistor M4 and two load resistance R1, R2, and described the second field effect transistor M2 and the 3rd field effect transistor M3 and the 4th field effect transistor M4 have identical parameter attribute; The source electrode of described the 3rd field effect transistor M3 and the 4th field effect transistor M4 all is connected with the drain electrode of described the 6th field effect transistor M6, thereby the source electrode of the electric current I 2 of described current mirror circuit output by described the 3rd field effect transistor M3 and the 4th field effect transistor M4 inputs to described amplifying circuit; The grid of the 3rd field effect transistor M3 is connected with the positive input VIN of external signal input, by described positive input VIN, outside forward signal being inputed to described the 3rd field effect transistor M3 amplifies, described the 3rd field effect transistor M3 drain electrode is connected with the end of load resistance R1 and the forward output VOUTN of signal output part, thereby the forward signal after described the 3rd field effect transistor M3 amplifies is by described forward output VOUTN output, the other end ground connection of described load resistance R1; The grid of the 4th field effect transistor M4 is connected with the reverse input end VIP of external signal input, by described reverse input end VIP, outside reverse signal being inputed to described the 4th field effect transistor M4 amplifies, described the 4th field effect transistor M4 drain electrode is connected with the end of load resistance R2 and the inverse output terminal VOUTP of signal output part, thereby the reverse signal after described the 4th field effect transistor M4 amplifies is by described inverse output terminal VOUTP output, the other end ground connection of described load resistance R2.in preferred implementation of the present utility model, because described the second field effect transistor M2 and the 3rd field effect transistor M3 and the 4th field effect transistor M4 have identical parameter attribute, described the 3rd field effect transistor M3 and the 4th field effect transistor M4, thereby described electric current I 2 will be inputted the 3rd field effect transistor M3 and the 4th field effect transistor M4 with dividing equally, make the upper current flowing value of described the 3rd field effect transistor M3 and the 4th field effect transistor M4 equate, and equate with the electric current of flowing through on described the second field effect transistor M2, namely equate with I0, the mutual conductance gm3 that is also described the 3rd field effect transistor M3 equates with the mutual conductance gm2 of the second field effect transistor M2 with the mutual conductance gm4 of the 4th field effect transistor M4, gm2=gm3=gm4, thereby the gain A that can draw described amplifying circuit in conjunction with above-mentioned (1) to (3) formula is

$A=\mathrm{gm}3*R1=\mathrm{gm}4*R2=\mathrm{gm}2*\mathrm{RL}=2*(\sqrt{N}-1)\frac{\mathrm{RL}}{R0}---\left(4\right)$

Wherein, RL is the resistance value of load resistance R1, R2.

By (4) formula as seen, the gain of the utility model amplifier and N, RL is relevant to the ratio of R0, wherein N be one with the irrelevant constant of the variation of temperature and process corner; Though and the resistance of load resistance R1, R2 and the first resistance R 0 can change with the variation of temperature and process corner, the ratio of RL and R0 can not change with temperature and process corner, and the ratio of resistance is usually very accurate; So the gain A of amplifier of the present utility model is a value that has nothing to do with technique, its gain can with the variation of temperature and process corner, not guarantee the stability through the amplifier amplified signal.

Abovely in conjunction with most preferred embodiment, the utility model is described, but the utility model is not limited to the embodiment of above announcement, and should contains various modification, equivalent combinations of carrying out according to essence of the present utility model.

Claims (7)

1. amplifier, it is characterized in that, comprise current generating circuit, current mirror circuit and amplifying circuit, described current generating circuit comprises the first field effect transistor, the second field effect transistor and the first resistance, described the first field effect transistor respectively with external power source, described the second field effect transistor and described current mirror circuit connect, described the first resistance is connected with described external power source and described the second field effect transistor respectively, described the second field effect transistor also is connected with described current mirror circuit, input to described current mirror circuit with the electric current that described current generating circuit is produced, described current mirror circuit also is connected with external power source and described amplifying circuit respectively, described current mirror circuit amplifies 2 times and input to described amplifying circuit with the current mirror of described current generating circuit output, described amplifying circuit is connected with external signal input and signal output part, and described amplifying circuit comprises the 3rd field effect transistor, the 4th field effect transistor and two load resistances, described the 3rd field effect transistor, the 4th field effect transistor respectively with described current mirror circuit, the external signal input, signal output part and a load resistance connect, described the 3rd field effect transistor and the 4th field effect transistor are amplified the signal of outside signal input part input, and the signal after amplifying by described signal output part output, and described the second field effect transistor, the 3rd field effect transistor and the 4th field effect transistor have identical parameter attribute.

2. amplifier as claimed in claim 1, it is characterized in that, described current mirror circuit comprises the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor and the 9th field effect transistor, the source electrode of described the 7th field effect transistor, the source ground of described the 8th field effect transistor source electrode and described the 9th field effect transistor, the drain electrode of described the 7th field effect transistor is connected with the drain and gate of described the first field effect transistor, the grid of described the 8th field effect transistor and drain electrode, the grid of the grid of the 7th field effect transistor and the 9th field effect transistor is connected with the drain electrode of described the second field effect transistor, the drain electrode of described the 9th field effect transistor is connected jointly with the grid of described the 5th field effect transistor and the grid of drain electrode and the 6th field effect transistor, described the 5th field effect transistor, the source electrode of described the 6th field effect transistor all is connected with described external power source, the drain electrode of described the 6th field effect transistor is connected with the source electrode of described the 3rd field effect transistor and the source electrode of described the 4th field effect transistor respectively.

3. amplifier as claimed in claim 2, it is characterized in that, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor, the breadth length ratio of described the 9th field effect transistor is 2 times of described the 8th field effect transistor breadth length ratio, and described the 5th field effect transistor equates with the breadth length ratio of the 6th field effect transistor.

4. amplifier as claimed in claim 2, it is characterized in that, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor, the breadth length ratio of described the 9th field effect transistor equates with described the 8th field effect transistor breadth length ratio, and the breadth length ratio of described the 6th field effect transistor is 2 times of described the 5th field effect transistor breadth length ratio.

5. amplifier as claimed in claim 2, it is characterized in that, the source electrode of described the first field effect transistor is connected with described external power source, its grid is connected jointly with the grid of drain electrode with described the second field effect transistor, and be connected with the drain electrode of described the 7th field effect transistor, described the first resistance one end is connected with external power source, and the other end is connected with the source electrode of the second field effect transistor, and the drain electrode of described the second field effect transistor is connected with the drain electrode of described the 8th field effect transistor.

6. amplifier as claimed in claim 5, is characterized in that, the breadth length ratio of described the second field effect transistor is N times of described the first field effect transistor breadth length ratio, and N is integer, and N 〉=2.

7. amplifier as claimed in claim 2, it is characterized in that, the source electrode of described the 3rd field effect transistor and the 4th field effect transistor all is connected with the drain electrode of described the 6th field effect transistor, the grid of described the 3rd field effect transistor is connected with the positive input of external signal input, its drain electrode is connected with an end of a load resistance and the forward output of signal output part, the grid of described the 4th field effect transistor is connected with the reverse input end of external signal input, its drain electrode is connected with the inverse output terminal of another load resistance and signal output part, and the equal ground connection of the other end of two described load resistances.

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