CN202940828U - Avionic full duplex real-time Ethernet data transmitting device - Google Patents

Abstract

The utility model discloses an avionic full duplex real-time Ethernet data transmitting device, and relates to the technical field of aviation bus ARINC 664 test. The AFDX data transmitting device disclosed by the utility model comprises a setting unit, a timing circuit and a data processing circuit, wherein the setting unit determines a data timed transmitting period according to user operations, and sets the determined data timed transmitting period as a timing period of the timing circuit; the timing circuit detects whether the timing period set by the setting unit is reached or not, and starts the data processing circuit when the timing period is reached; and the data processing circuit transmits messages predefined by users. The technical solution disclosed by the utility model meets requirements of the users in the test process, that is, particular test operations are carried out according to particular triggering conditions set by the users, thereby enriching the test environment, and further improving the reliability of the test.

Description

A kind of avionics full duplex real-time ethernet data sending device

Technical field

The utility model relates to aviation bus ARINC 664 technical field of measurement and test, is specifically related to a kind of avionics full duplex real-time ethernet data sending device.

Background technology

AFDX (Avionics Full Duplex Switched Ethernet, avionics full duplex real-time ethernet) be Airbus SAS according to the ARINC664 standard, the technology that realizes for the aircraft data network (Aircraft Data Networks) of determining.Be widely used at present interconnecting electronic system in aviation aircraft is as engine, flight-control component, cruise system etc.Up to now, AFDX has used at A380, in A400M and Boeing B787 project.And based on the equipment of this agreement also increasing, so be sought after very perfect testing scheme, this kind equipment is tested.In test process, often need to set some specific conditions, do some special test jobs when condition satisfies, provide a kind of trigger mechanism so be necessary for test, when some trigger condition satisfies, just can carry out some specific test events according to different test conditions.

The utility model content

Technical problem to be solved in the utility model is to provide a kind of avionics full duplex real-time ethernet data sending device, to improve testing reliability.

In order to solve the problems of the technologies described above, the utility model discloses a kind of avionics full duplex real-time ethernet (AFDX) data sending device, comprise setting unit, timing circuit and and data processing circuit, wherein:

Described setting unit operates the specified data timed sending cycle according to the user, and the determined data timing transmission cycle is set to the timing cycle of described timing circuit;

Described timing circuit detects whether arrive the timing cycle that described setting unit arranges, and starts described data processing circuit when arriving timing cycle;

Described data processing circuit sends user's predefined message.

Preferably, in said apparatus, described timing circuit adopts two cycle timers to consist of, and each cycle timer produces independently triggering signal, and wherein, the timing cycle of each cycle timer is the timing cycle that described setting unit arranges.

Preferably, in said apparatus, described setting unit adopts Programmable Logic Controller and central processing unit to realize.

Preferably, said apparatus also comprises, the first testing circuit detects the triggering signal whether input interface of setting receives external transistor-transistor logic (TTL) level of setting, and when the triggering signal of the outside Transistor-Transistor Logic level that receives setting, start described data processing circuit.

Preferably, said apparatus also comprises, memory cell stores the internal trigger information that the user arranges;

The second testing circuit, whether real-time judge system current state satisfies the requirement of the internal trigger information of storing in described memory cell, when satisfying the requiring of one or more internal trigger information, starts described data processing circuit.

Preferably, in said apparatus, described memory cell is register.

Preferably, in said apparatus, described the second testing circuit adopts Programmable Logic Controller to realize.

The present techniques scheme has satisfied user's request in test process, the special trigger condition that namely arranges according to the user is carried out special test operation, has enriched test environment, has further improved the reliability of test.

Description of drawings

The AFDX data sending device structural representation that Fig. 1 provides for the present embodiment;

Fig. 2 increases the structural representation of the AFDX data sending device that memory cell and the second testing circuit are arranged in the present embodiment.

Embodiment

For making the purpose of this utility model, technical scheme and advantage clearer, hereinafter technical solutions of the utility model are described in further detail.Need to prove, in the situation that do not conflict, the application's embodiment and the feature in embodiment can make up arbitrarily mutually.

Embodiment 1

A kind of avionics full duplex of the present embodiment article real-time ethernet data sending device as shown in Figure 1, comprises setting unit, timing circuit and data processing circuit.

Setting unit operates the specified data timed sending cycle according to the user, and the determined data timing transmission cycle is set to the timing cycle of timing circuit;

Timing circuit detects whether to arrive the timing cycle that setting unit arranges, and when arriving timing cycle the log-on data treatment circuit;

Data processing circuit sends user's predefined message.

Wherein, timing circuit judges and can be realized by timer when whether the timed sending cycle arrives.Be timing circuit adopt two cycle timers produce 2 the tunnel independently triggering signal judge whether the timed sending cycle arrives.The timing length of each cycle timer is the data transmitting period that setting unit arranges.Mainly to use for redundancy and why adopt two timers.Wherein, can also realize with FPGA the timing of cycle timer.

In addition, data processing circuit can use the central processing unit (CPU) of Programmable Logic Controller (FPGA) and a POWERPC to realize., namely setting unit is obtained the upward frame period between every two Frames of each VlINK according to the timing cycle of user's setting, and the data timing that the frame period that obtains is configured to corresponding VlINK sends the cycle.And when the timing circuit judgement timed sending cycle arrived, the log-on data treatment circuit carried out data and sends.This moment, test on corresponding VlINK is searched and sent to data processing circuit with packet (being user's predefined message).

Preferred version is on the basis that comprises above-mentioned setting unit, timing circuit and data processing circuit, can also comprise the first testing circuit, detect the triggering signal whether input interface of setting receives external transistor-transistor logic (TTL) level of setting, and when the triggering signal of the outside Transistor-Transistor Logic level that receives setting, start described data processing circuit, thereby realize the external signal triggering mode.And the triggering signal of the outside Transistor-Transistor Logic level of setting that to be generally the user be is that each input interface arranges respectively, it can also arrange for the triggering signal of each outside Transistor-Transistor Logic level corresponding user's predefined message.Like this, when data processing circuit sends data, can send corresponding user's predefined message on the output port of correspondence.

For example, the user can arrange the triggering signal input interface of 4 tunnel outside Transistor-Transistor Logic levels in advance, is used for special test environment.The triggering signal of input allows unsettled, is pulled to high level.Can define for triggering signal that rising edge is effective or trailing edge is effective.Simultaneously when triggering signal is too intensive, can the unnecessary triggering signal of automatic fitration.Wherein, the user can arrange the corresponding input port of configure trigger signal and output port in advance, and signal is effectively along being the information such as rising edge or trailing edge be effective.Trigger to send and to be configured to single or circulation transmission appointment sequence of message (being user's predefined message).Need to prove, after setting in advance each information, with the start and stop of external input signal as the data message sending function.Also namely starting message by outer triggering signal sends.Each triggering signal that configures is can corresponding certain output port effective.Also can be to two output ports simultaneously effectively.Each start trigger signal sends one or a series of predefined message (being user's predefined message).Process of transmitting that will the log-on data processing unit when each triggering signal satisfies set condition.

Also have in some embodiment, said apparatus also includes the memory cell of the internal trigger information that stores user's setting.And second testing circuit, whether real-time judge system current state satisfies the requirement of the internal trigger information of storing in memory cell, when satisfying the requiring of arbitrary or a plurality of internal trigger information, and the log-on data treatment circuit.Particularly, memory cell adopts register to realize, as shown in Figure 2, stores the internal trigger information (also can be described as the internal trigger condition) that the user arranges in this register, and user's predefined message corresponding to this internal trigger condition.And the second testing circuit judges when system's current state satisfies one or more internal trigger condition of user's setting, and the trigger data treatment circuit carries out data and sends.And data processing circuit sends the packet (i.e. user's predefined message of correspondence) of given content when sending data.For example, receive the packet that some are special in test process, when these special packets of configuration in memory cell when being exactly trigger condition, the second testing circuit namely can judge and produced the internal trigger signal, and data processing circuit can send the user predefined message corresponding with this trigger condition and get final product.Wherein, the second testing circuit can adopt Programmable Logic Controller (FPGA) to realize.

One of ordinary skill in the art will appreciate that all or part of step in said method can come the instruction related hardware to complete by program, described program can be stored in computer-readable recording medium, as read-only memory, disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuits.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, also can adopt the form of software function module to realize.The application is not restricted to the combination of the hardware and software of any particular form.

Can find out from above-described embodiment, the present techniques scheme realized in test process according to user instruction, and clocked flip, outside input trigger and three kinds of test modes of internal trigger, have enriched test environment, and then have improved the reliability of test.

The above is only preferred embodiments of the present utility model, is not be used to limiting protection range of the present utility model.All within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.

Claims (7)

1. an avionics full duplex real-time ethernet AFDX data sending device, is characterized in that, this device comprise setting unit, timing circuit and and data processing circuit, wherein:

Described setting unit operates the specified data timed sending cycle according to the user, and the determined data timing transmission cycle is set to the timing cycle of described timing circuit;

Described timing circuit detects whether arrive the timing cycle that described setting unit arranges, and starts described data processing circuit when arriving timing cycle;

Described data processing circuit sends user's predefined message.

2. device as claimed in claim 1, is characterized in that,

Described timing circuit adopts two cycle timers to consist of, and each cycle timer produces independently triggering signal, and wherein, the timing cycle of each cycle timer is the timing cycle that described setting unit arranges.

3. device as claimed in claim 1, is characterized in that, described setting unit adopts Programmable Logic Controller and central processing unit to realize.

4. device as described in the claims 1 to 3 any one, is characterized in that, this device also comprises:

The first testing circuit, whether the input interface that detects setting receives the triggering signal of the external transistor of setting-transistor logic Transistor-Transistor Logic level, and when the triggering signal of the outside Transistor-Transistor Logic level that receives setting, starts described data processing circuit.

5. device as claimed in claim 4, is characterized in that, this device also comprises:

Memory cell stores the internal trigger information that the user arranges;

The second testing circuit, whether real-time judge system current state satisfies the requirement of the internal trigger information of storing in described memory cell, when satisfying the requiring of one or more internal trigger information, starts described data processing circuit.

6. device as claimed in claim 5, is characterized in that,

Described memory cell is register.

7. device as claimed in claim 5, is characterized in that,

Described the second testing circuit adopts Programmable Logic Controller to realize.

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