CN202940574U - New type undervoltage protection circuit in motor driving chip - Google Patents

Abstract

The utility model discloses an undervoltage protection circuit. The undervoltage protection circuit comprises a band-gap reference circuit, a first current mirror circuit, a second current mirror circuit, a plurality of resistors, metal-oxide-semiconductor type field effect transistors and inverters. A resistor R4 is serially connected with a negative channel-metal-oxide-semiconductor type field effect transistor MN1 and then connected in parallel with a resistor R3, the resistor R3, a resistor R1 and a resistor R2 are serially connected between a power supply VDD and the ground GND, the gate of a positive channel-metal-oxide-semiconductor type field effect transistor MP0 is grounded; the voltage VA between the resistor R1 and the resistor R2 is loaded onto the band-gap reference circuit; a first input end and a second input end of the band-gap reference circuit are connected with two current branches of the first current mirror circuit respectively; the second input end of the band-gap reference circuit is connected to the second current mirror circuit through a positive channel-metal-oxide-semiconductor type field effect transistor MP5, and the positive channel-metal-oxide-semiconductor type field effect transistor MP5 is connected to the gate of the negative channel-metal-oxide-semiconductor type field effect transistor MN1 through a first inverter. According to the utility model, advantages of simple structure and small transmission delay can be realized, and a undervoltage signal can be generated rapidly.

Description

Under-voltage protecting circuit in a kind of novel motor drive ic

Technical field

The utility model relates to a kind of protective circuit, relates in particular to the under-voltage protecting circuit in a kind of motor drive ic.

Background technology

Motor is in the process of operation, except completing various normal operations by the technological requirement of manufacturing machine, also must be when the phenomenons such as short circuit, overload, overcurrent, under-voltage, decompression and loss of excitation appear in circuit, can stop operating by automatic cut-off power, to prevent and to avoid the damage accident of electric equipment and the equipment of unloading, guarantee operating personnel's personal safety.For this reason, in the electric control circuit of manufacturing machine, the various safeguard measures to motor have been taked.The protection of motor commonly used has short-circuit protection, overload protection, overcurrent protection, under-voltage protection, o-volt protection and field loss protection etc.

In motor-driven, the voltage stability in system is particularly important, and overvoltage, under-voltage circuit are essential.When the line voltage reduction, motor is just in under-voltage lower operation.Because motor load does not change, so under-voltage lower motor speed descends, the electric current in stator winding increases.Therefore the amplitude that increases of electric current still deficiency so that fuse and thermal relay action, so these two kinds of electrical equipment do not have protective effect.As not taking safeguard measure, time one length will make motor overheating damage.In addition, under-voltagely will cause that some electrical equipment discharge, make the circuit cisco unity malfunction, also may cause personal injury and device damage accident.Therefore, should avoid the under-voltage lower operation of motor.

Modern efficient, accurate Electric Machine Control is all that employing is computer implemented, consists of a complete kinetic control system by motor chip and primary processor, motor and increment encoder.During lower than the normal range of operation of chip, some circuit of chip internal possibly can't work when supply voltage, and this might produce the internal logic mistake, makes the external switch pipe be in nondeterministic statement.If the external switch pipe is in conducting state during the other parts cisco unity malfunction of chip; chip is burnt; or external circuit is caused damage; therefore; it is essential that chip internal adds under-voltage protecting circuit; can guarantee supply voltage lower than the cleaning door of setting in limited time, most of module of external power pipe and chip internal is in off state.

When working due to under-voltage protecting circuit, chip belt gap reference circuit and LDO module be not normal operation also, that is to say, under-voltage protecting circuit must have reference voltage.And in order to make trigger voltage not along with variations such as technique, temperature, reference voltage must be a voltage that does not change with temperature, technique etc.Often have reference circuit part producing reference voltage in the under-voltage protecting circuit of prior art, will the sample reference voltage signal of the power supply voltage signal that comes and reference circuit generation of usage comparison device compares.

The under-voltage protecting circuit of prior art as shown in Figure 1 has reference circuit 1 and comparison circuit, and reference circuit 1 produces reference current I _nAnd reference voltage V _n, signal and the reference voltage V of the supply voltage VDD1 that comparison circuit will be sampled _nSignal, judge whether to occur under-voltage.Wherein, when not occuring when under-voltage, VDD1＞V _n, VOUT1 output high level (VOUT1=1) is to control the motor drive ic normal operation; When generation is under-voltage, VDD1＜V _n, VOUT1 output low level (VOUT1=0) quits work to control motor drive ic.But the under-voltage protecting circuit of this class prior art easily is subject to the interference of reference generating circuit, therefore needs the special comparator circuit of design, the structure relative complex.

Therefore, those skilled in the art is devoted to develop a kind of under-voltage protecting circuit, and it is not subjected to the impact of reference circuit, does not also need special comparator circuit.

The utility model content

Because the defects of prior art; technical problem to be solved in the utility model is to provide a kind of under-voltage protecting circuit; when supply voltage reduces, can produce fast and export under-voltage signal, and this under-voltage protecting circuit does not need extra supply voltage.

For achieving the above object, the utility model provides a kind of under-voltage protecting circuit, it is characterized in that, comprises band-gap reference circuit, the first current mirroring circuit, the second current mirroring circuit and some resistance, NMOS pipe, PMOS pipe and inverter; Resistance R 4 is connected afterwards and resistance R 3 parallel connections with NMOS pipe MN1, and described resistance R 3 and resistance R 1, resistance R 2 are connected between power vd D and ground GND; Voltage V between described resistance R 1 and described resistance R 2 _ABe carried on described band-gap reference circuit; The first input end of described band-gap reference circuit be connected input and connect respectively two current branch of described the first current mirroring circuit; Described second input of described band-gap reference circuit is connected to described the second current mirroring circuit to control the level of output voltage VO UT through PMOS pipe MP5, and described PMOS pipe MP5 is connected to the grid of described NMOS pipe MN1 by the first inverter.

Further, described band-gap reference circuit comprises triode Q1, triode Q2, resistance R 5 and resistance R 6, the base stage of described triode Q1 is connected with the base stage of described triode Q2, the emitter of described triode Q1 is connected with the emitter of described triode Q2 through described resistance R 5, and the emitter of described triode Q2 is through described resistance R 6 ground connection GND; The described first input end of the very described band-gap reference circuit of the current collection of described triode Q1, described second input of the very described band-gap reference circuit of the current collection of described triode Q2; Described voltage V between resistance R 1 and described resistance R 2 _ABe carried on the base stage of the base stage of described triode Q1 and described triode Q2.

Further, the ratio of the emitter area of the emitter area of described triode Q1 and described triode Q2 is n.

Further, described triode Q1 and described triode Q2 are all NPN type triode.

Further, described the first current mirroring circuit comprises PMOS pipe MP1, PMOS pipe MP2 and PMOS pipe MP3, and the source electrode of the source electrode of described PMOS pipe MP1, described PMOS pipe MP2 and the source electrode of described PMOS pipe MP3 all are connected to described power vd D; The drain electrode of described PMOS pipe MP1 is connected to the collector electrode of described triode Q1, and the drain electrode of described PMOS pipe MP2 is connected to the collector electrode of described triode Q2.

Further, the grid of described PMOS pipe MP1 is connected with drain electrode.

Further, described the second current mirroring circuit comprises NMOS pipe MN2, NMOS pipe MN3 and NMOS pipe MN4, and the source electrode of the source electrode of described NMOS pipe MN2, described NMOS pipe MN3 and the source electrode of described NMOS pipe MN4 be ground connection all; The drain electrode of described NMOS pipe MN2 is connected with the drain electrode of described PMOS pipe MP3; The drain electrode of described NMOS pipe MN3 is connected with the source electrode of described PMOS pipe MP5.

Further, the grid of described NMOS pipe MN2 is connected with drain electrode.

Further, the source electrode of described PMOS pipe MP5 is connected to the grid of NMOS pipe MN5 through described the first inverter and the second inverter, and the source electrode of described NMOS pipe MN5 is connected with the drain electrode of described NMOS pipe MN4.

Further, the voltage V of described power vd D _DDFrom being increased to lower than normal value the process of normal value, when

The time, described output voltage VO UT transfers high level to from low level; The voltage V of described power vd D _DDFrom normal value is reduced to process lower than normal value, when

The time, described output voltage VO UT transfers low level to from high level; V wherein _refIt is the value of the collector current of the described triode Q1 described voltage VA when equating with the collector current of triode Q2.

In better embodiment of the present utility model, comprise band-gap reference circuit, the first current mirroring circuit, the second current mirroring circuit and some resistance, NMOS pipe, PMOS pipe and inverter.Wherein, triode Q1, triode Q2, resistance R 5 and resistance R 6 consist of band-gap reference circuit, the base stage of triode Q1 is connected with the base stage of triode Q2, and the emitter of triode Q1 is connected with the emitter of triode Q2 through resistance R 5, and the emitter of triode Q2 is through resistance R 6 ground connection.Resistance R 4 is connected afterwards and resistance R 3 parallel connections with NMOS pipe MN1, and resistance R 3 and PMOS pipe MP0, resistance R 1, resistance R 2 are connected between power vd D and ground GND, the voltage V between resistance R 1 and resistance R 2 _ABe carried on the base stage of the base stage of triode Q1 and triode Q2.As voltage V _AWhen being in a certain threshold value, band-gap reference circuit normal operation, i.e. I _CQ1=I _CQ2, this moment V _ABe the magnitude of voltage V of a zero-temperature coefficient _refPMOS pipe MP1, PMOS pipe MP2 and PMOS pipe MP3 consist of the first current mirroring circuit, and the source electrode of the source electrode of PMOS pipe MP1, PMOS pipe MP2 and the source electrode of PMOS pipe MP3 all are connected to power vd D.NMOS pipe MN2, NMOS pipe MN3 and NMOS pipe MN4 consist of the second current mirroring circuit, and the source electrode of the source electrode of NMOS pipe MN2, NMOS pipe MN3 and the source electrode of NMOS pipe MN4 be ground connection all.The drain electrode of PMOS pipe MP1 is connected to the collector electrode of triode Q1, and the drain electrode of PMOS pipe MP2 is connected to the collector electrode of triode Q2.The collector electrode of triode Q2 is managed MP5 by PMOS and is connected to the second current mirroring circuit to control the level of output voltage VO UT, and PMOS pipe MP5 is by the break-make of the first inverter controlling NMOS pipe MN1.At the voltage of power vd D from be increased to the process of normal value lower than normal value, when

The time, output voltage VO UT transfers high level to from low level; Voltage V at power vd D _DDFrom normal value is reduced to process lower than normal value, when

The time, output voltage VO UT transfers low level to from high level.

This shows, under-voltage protecting circuit of the present utility model is simple in structure, only is made of several resistance, NMOS pipe, PMOS pipe and inverter, and does not need circuit and the comparator circuit of extra generation reference voltage; And band-gap reference circuit wherein is by the power drives of motor drive ic, and does not need to provide extra driving power for it.Under-voltage protecting circuit of the present utility model has advantages of that also transmission delay is less; can produce fast under-voltage signal; and can pass through its output voltage control motor drive ic; make on the one hand motor drive ic quit work fast in order to avoid cause damage when under-voltage situation occurs, make on the other hand motor drive ic quick-recovery normal operation soon after eliminating under-voltage situation.

Be described further below with reference to the technique effect of accompanying drawing to design of the present utility model, concrete structure and generation, to understand fully the purpose of this utility model, feature and effect.

Description of drawings

Fig. 1 is the circuit structure diagram of the under-voltage protecting circuit of prior art.

Fig. 2 is the circuit structure diagram of under-voltage protecting circuit of the present utility model.

Fig. 3 is the voltage characteristic curve of under-voltage protecting circuit of the present utility model.

Embodiment

As shown in Figure 2, in the present embodiment, under-voltage protecting circuit of the present utility model comprise resistance R 1, R2 ..., R8, triode Q1, Q2, PMOS pipe MP0, MP1 ..., MP6, NMOS pipe MN1, MN2 ..., MN5 and two inverters.Wherein, triode Q1, triode Q2, resistance R 5 and resistance R 6 consist of band-gap reference circuit; PMOS pipe MP1, PMOS pipe MP2 and PMOS pipe MP3 consist of the first current mirroring circuit; NMOS pipe MN2, NMOS pipe MN3 and NMOS pipe MN4 consist of the second current mirroring circuit.The PMOS pipe is P type MOSFET pipe, and the NMOS pipe is N-type MOSFET pipe.

In the band-gap reference circuit of under-voltage protecting circuit of the present utility model, the base stage of triode Q1 is connected with the base stage of triode Q2, and the emitter of triode Q1 is connected with the emitter of triode Q2 through resistance R 5, and the emitter of triode Q2 is through resistance R 6 ground connection.Triode Q1, Q2 are two NPN type triodes, and the ratio of both emitter area is n, namely the emitter area of triode Q1 be triode Q2 emitter area n doubly.

In the first current mirroring circuit of under-voltage protecting circuit of the present utility model, the source electrode of the source electrode of PMOS pipe MP1, PMOS pipe MP2 and the source electrode of PMOS pipe MP3 all are connected to power vd D, and the grid of PMOS pipe MP1 is connected with drain electrode.PMOS pipe MP1, MP2 and MP3 have basically identical structure, technique and parameter.

In the second current mirroring circuit of under-voltage protecting circuit of the present utility model, the source electrode of the source electrode of NMOS pipe MN2, NMOS pipe MN3 and the source electrode of NMOS pipe MN4 be ground connection all, and the grid of NMOS pipe MN2 is connected with drain electrode.NMOS pipe MN2, MN3 and MN4 have basically identical structure, technique and parameter.

In under-voltage protecting circuit of the present utility model, resistance R 4 is connected afterwards and resistance R 3 parallel connections with NMOS pipe MN1, and resistance R 3 and resistance R 1, resistance R 2 are connected between power vd D and ground GND.Voltage V between resistance R 1 and resistance R 2 _ABe carried on the base stage of triode Q1 and the base stage of triode Q2 (the A point place in Fig. 2).In the present embodiment, also increased PMOS pipe MP0 and connected with resistance R 1, resistance R 2 and resistance R 3, the grounded-grid of PMOS pipe MP0.The drain electrode of PMOS pipe MP1 is connected to the collector electrode of triode Q1, the drain electrode of PMOS pipe MP2 is connected to the collector electrode (the B point place in Fig. 2) of triode Q2, the collector electrode of triode Q2 connects grid and the drain electrode of PMOS pipe MP5, and the collector electrode of triode Q2 connects the grid of PMOS pipe MP4.The source electrode of PMOS pipe MP4 connects power vd D, and the drain electrode of PMOS pipe MP4 connects the source electrode of PMOS pipe MP5.The drain electrode of NMOS pipe MN2 is connected with the drain electrode of PMOS pipe MP3, the source electrode that the drain electrode of NMOS pipe MN3 and PMOS manage MP5 be connected (the C point place in Fig. 2).PMOS pipe MP5 is connected to the grid (the D point place in Fig. 2) of NMOS pipe MN1 by the first inverter, control the break-make of NMOS pipe MN1; The source electrode of PMOS pipe MP5 is connected to the grid of NMOS pipe MN5 by the first inverter and the second inverter, the source electrode of NMOS pipe MN5 is connected with the drain electrode of NMOS pipe MN4.The drain electrode of NMOS pipe MN5 is connected to power vd D through resistance R 7, and the drain electrode of NMOS pipe MN5 is connected to the grid of PMOS pipe MP4.The source electrode of PMOS pipe MP4 is connected to power vd D, and its drain electrode is through resistance R 8 ground connection, and the voltage at resistance R 8 two ends is output voltage VO UT.

For the band-gap reference circuit of under-voltage protecting circuit of the present utility model, the mutual conductance relation of two triode Q1 and Q2 is:

g _m1＝ng _m2’

Wherein, g _m1The mutual conductance of triode Q1, g _m2It is the mutual conductance of triode Q2.

Due to the emitter-base bandgap grading feedback effect of R5, R6, so the equivalent transconductance of triode Q1, Q2 is respectively:

${\mathrm{<figure-callout\; id="1"\; label="G\; m"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">G</figure-callout>}}_m=\frac{{\mathrm{<figure-callout\; id="1"\; label="g\; m"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">g</figure-callout>}}_m}{1+g_{m1}(R_5+R_6)}=\frac{g_{m2}}{1+g_{m2}{R}_6+g_{m2}{R}_5+\frac{1}{n}-1},$ $G_{m2}=\frac{g_{m2}}{1+g_{m2}{R}_6},$

Wherein, G _m1The mutual conductance of triode Q1, G _m2The mutual conductance of triode Q2, R ₅, R ₆Be respectively the resistance of resistance R 5, R6.

The general g that selects _m2R ₅＞＞1, G _m1＜G _m2So, when the voltage fluctuation of the power vd D of electrode drive chip, the collector current I of triode Q1 _C1Collector current I with respect to triode Q2 _C2Variable quantity is little.Just be based on the speed of this collector current variable quantity, under-voltage protecting circuit of the present utility model is by comparing I _C1And I _C2Size, whether the power vd D that can show motor drive ic by the level of output voltage VO UT for under-voltage condition, labor is as follows:

As A point voltage V _refWhen reaching a certain threshold value, I _C1=I _C2Collector current due to triode

I wherein _sA constant for this triode,

Be positive temperature coefficient, V _BEBe negative temperature coefficient.Therefore by appropriate design n, R ₅And R ₆Value, can realize V _ArefZero-temperature coefficient, namely the band-gap reference circuit of under-voltage protecting circuit of the present utility model has the not reference voltage level V of temperature influence _Aref

The voltage V of power vd D _DDFrom being increased to lower than normal value the process of normal value, voltage V _DDRaise gradually, A point voltage V _AIncrease, thus V _BE1, V _BE2Increase, thereby make I _Co1, I _Co2Increase, and I _Co2＞I _CQ1So B point current potential descends, PMOS pipe MP4 conducting, the C point voltage raises, when the C point voltage higher than B point voltage V _THThe time, PMOS pipe MP5 conducting pours into electric current on the collector electrode of triode Q2, thereby draws high B point current potential, makes the B point current potential can be because of voltage V _DDRising and by drawn very low, triode Q1, Q2 still are operated in normal condition, make as voltage V _DDThe electrical potential energy that during reduction, B is ordered is drawn high more fast, produces under-voltage signal.After the C point voltage raises, D point current potential output low level, MN1 turn-offs, and final output voltage VO UT transfers high level to from low level.Wherein, the voltage V of power vd D _DDThreshold value from the process that is increased to normal value lower than normal value $V_S$ $1_{}=\frac{R_1+R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3//R_4}{R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3//R_4}{V}_{\mathrm{Aref}},$ Namely work as $V_{\mathrm{DD}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3//R_4}{R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3+R_4}{V}_{\mathrm{ref}}$ The time, output voltage VO UT transfers high level to from low level.In formula, R ₁, R ₂, R ₃And R ₄Be respectively the resistance of resistance R 1, R2, R3 and R4, R ₃//R ₄Resistance after expression resistance R 3 and R4 parallel connection.

The voltage V of power vd D _DDFrom normal value is reduced to process lower than normal value, voltage V _DDReduce gradually A point voltage V _AReduce, thus V _BE1, V _BE2Reduce, thereby make I _Co1, I _Co2Reduce, and I _Co2＜I _CQ1, it is very low that the current potential of ordering due to B is not drawn, and Q1, Q2 still are operated in normal condition, and B point current potential is drawn high fast, MP4 turn-offs, and C point current potential is dragged down, and MP5 turn-offs, D point current potential output high level, the MN1 conducting, final output voltage VO UT transfers low level to from high level.Wherein, the voltage V of power vd D _DDBe reduced to lower than the threshold value the process of normal value from normal value

Namely work as The time, output voltage VO UT transfers low level to from high level.In formula, R ₁, R ₂And R ₃Be respectively the resistance of resistance R 1, R2 and R3.

The voltage V of above-mentioned power vd D _DDFrom the process that is increased to normal value lower than normal value and be reduced to lower than the voltage response the process of normal value as shown in Figure 3 from normal value.Wherein, the threshold difference of these two processes $\mathrm{\&Delta;}{V}_{\mathrm{DD}}=\frac{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_1+R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3//R_4}{R_2+{\mathrm{<figure-callout\; id="3"\; label="R"\; filenames="HDA00002522594700011.png"\; state="\{\{state\}\}">R</figure-callout>}}_3//R_4}{V}_{\mathrm{Aref}}-\frac{R_1+R_2+R_3}{R_2+R_3}{V}_{\mathrm{Aref}}.$

More than describe preferred embodiment of the present utility model in detail.Should be appreciated that those of ordinary skill in the art need not creative work and just can make many modifications and variations according to design of the present utility model.Therefore, all those skilled in the art comply with design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be in the determined protection range by claims.

Claims (9)

1. a under-voltage protecting circuit, is characterized in that, comprises band-gap reference circuit, the first current mirroring circuit, the second current mirroring circuit and some resistance, NMOS pipe, PMOS pipe and inverter; Resistance (R4) is connected afterwards and resistance (R3) parallel connection with NMOS pipe (MN1), and described resistance (R3) and resistance (R1), resistance (R2) are connected between power supply (VDD) and ground (GND); Voltage (V between described resistance (R1) and described resistance (R2) _A) be carried on described band-gap reference circuit; The first input end of described band-gap reference circuit be connected input and connect respectively two current branch of described the first current mirroring circuit; Described second input of described band-gap reference circuit is connected to described the second current mirroring circuit through PMOS pipe (MP5), and described PMOS pipe (MP5) is connected to the grid of described NMOS pipe (MN1) by the first inverter.

2. under-voltage protecting circuit as claimed in claim 1, wherein said band-gap reference circuit comprises triode (Q1), triode (Q2), resistance (R5) and resistance (R6), the base stage of described triode (Q1) is connected with the base stage of described triode (Q2), the emitter of described triode (Q1) is connected with the emitter of described triode (Q2) through described resistance (R5), and the emitter of described triode (Q2) is through described resistance (R6) ground connection (GND); The described first input end of the very described band-gap reference circuit of current collection of described triode (Q1), described second input of the very described band-gap reference circuit of current collection of described triode (Q2); Described voltage (V between resistance (R1) and described resistance (R2) _A) be carried on the base stage of the base stage of described triode (Q1) and described triode (Q2).

3. under-voltage protecting circuit as claimed in claim 2, the ratio of the emitter area of the emitter area of wherein said triode (Q1) and described triode (Q2) is n.

4. under-voltage protecting circuit as claimed in claim 2 or claim 3, wherein said triode (Q1) and described triode (Q2) are all NPN type triode.

5. under-voltage protecting circuit as claimed in claim 4, wherein said the first current mirroring circuit comprises PMOS pipe (MP1), PMOS pipe (MP2) and PMOS pipe (MP3), and the source electrode of the source electrode of described PMOS pipe (MP1), described PMOS pipe (MP2) and the source electrode of described PMOS pipe (MP3) all are connected to described power supply (VDD); The drain electrode of described PMOS pipe (MP1) is connected to the collector electrode of described triode (Q1), and the drain electrode of described PMOS pipe (MP2) is connected to the collector electrode of described triode (Q2).

6. under-voltage protecting circuit as claimed in claim 5, the grid of wherein said PMOS pipe (MP1) is connected with drain electrode.

7. under-voltage protecting circuit as claimed in claim 6, wherein said the second current mirroring circuit comprises NMOS pipe (MN2), NMOS pipe (MN3) and NMOS pipe (MN4), and the source electrode of the source electrode of described NMOS pipe (MN2), described NMOS pipe (MN3) and the source electrode of described NMOS pipe (MN4) be ground connection all; The drain electrode of described NMOS pipe (MN2) is connected with the drain electrode that described PMOS manages (MP3); The drain electrode of described NMOS pipe (MN3) is connected with the source electrode that described PMOS manages (MP5).

8. under-voltage protecting circuit as claimed in claim 7, the grid of wherein said NMOS pipe (MN2) is connected with drain electrode.

9. under-voltage protecting circuit as claimed in claim 8; the source electrode of wherein said PMOS pipe (MP5) is connected to the grid of NMOS pipe (MN5) through described the first inverter and the second inverter, the source electrode of described NMOS pipe (MN5) is connected with the drain electrode that described NMOS manages (MN4).

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