CN202917457U - Epitaxial defect analytical structure - Google Patents
Epitaxial defect analytical structure Download PDFInfo
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- CN202917457U CN202917457U CN 201220641783 CN201220641783U CN202917457U CN 202917457 U CN202917457 U CN 202917457U CN 201220641783 CN201220641783 CN 201220641783 CN 201220641783 U CN201220641783 U CN 201220641783U CN 202917457 U CN202917457 U CN 202917457U
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Abstract
The utility model provides an epitaxial defect analytical structure, comprising a semiconductor substrate, one part of a surface of which forms an epitaxial growth area and the other part of a surface is exposed to a semiconductor substrate protected by a barrier layer protection area; and an epitaxial layer formed on the epitaxial growth area. The epitaxial defect analytical structure performs defect correlation analysis and contrast on the semiconductor substrate protected by the barrier layer protection area and an epitaxial layer in the epitaxial growth area in an epitaxial defect analytical structure, determines epitaxial detects in the epitaxial layer are from the epitaxial technique, the epitaxial front semiconductor manufacture technique or a semiconductor substrate and avoids the problem that in a process of performing defect correlation analysis and contrast, selected samples are not completely consistent in material selection and epitaxial processing processes, which is caused by the reason that the semiconductor substrate with epitaxy and the semiconductor substrate without epitaxy are not a same semiconductor substrate.
Description
Technical field
The utility model belongs to the semiconductor fabrication process technical field, is specifically related to a kind of epitaxy defect analytical structure.
Background technology
Epitaxy technique is to have on the substrate in certain crystal orientation in the integrated circuit manufacturing, adopt under certain conditions the methods such as chemical vapor deposition growth, along the original crystal axis direction of substrate, grow the process that the parameters such as conduction type, resistivity, thickness, lattice structure, integrality all meet the new single-crystal body layer of product structure requirement, this layer single crystalline layer is called epitaxial loayer.
In the epitaxial diposition process, be subjected to the impact of substrate and epitaxy technique, epitaxy defect (Epitaxy Defect) in epitaxial loayer, can occur.Can be divided into two large classes in the position of Yanzhong outside from epitaxy defect: a class is the epitaxy defect on the surface, generally can observe by metallomicroscope, such as angle body cone, cone, crescent moon, fish tail, orange peel, cloud surface etc.; Another kind of is the lattice structure defects that has epitaxial loayer inside, such as fault, slip dislocation, separate out impurity etc.The existence of epitaxy defect makes strictly the monocrystal by the combination of crystal arrangement rule change, and semiconductor structure is produced on the defective silicon chip of tool electric leakage, yield inefficacy, disabler etc. can occur unusually.
The reason that epitaxy defect produces is general all by introducing in technique, the epitaxial process before backing material, substrate surface, the extension.In practice, some epitaxy defect originates from epitaxial loayer inside, and some epitaxy defect originates from substrate interior even substrate surface, but by epitaxial growth rule and characteristic, can grown crystal in position that noncrystal key mapping is connected, originating from the defective of substrate interior even substrate surface carries out delaying to be exaggerated outward extending to epitaxial surface, more complicated situation also might all can cause identical defective in substrate and epitaxial loayer, therefore in the production of reality, how to judge epitaxy defect be introduce from substrate or what cause from the extension course of processing is our problem to be solved.Figure 1 shows that common epitaxy defect schematic diagram.Wherein 10 is substrate, and 11 is epitaxial loayer.In the substrate 10 shown in Figure 1, can have the defective of variety classes and degree, be the defective that crescent moon in the substrate or fishtail stacking fault cause such as 10a, and this class defective shows as since an end and along the pit of certain orientation elongation; 10b is common oxidation induced defective, is usually expressed as shaft-likely, but general occurs all can be with 10a the time.Simultaneously, in described epitaxial loayer 11,11a is comparatively common stacking fault, is generally caused by described substrate 10 precipitates or the oxide layer of remained on surface, hydrocarbon thing; There is the line dislocation that also extends to continuously in the described substrate 10 in the described epitaxial loayer 11 in 11b; 11c is the relevant cone defective of surface treatment, in described epitaxial loayer 11, show as little spike projection, such as other growth bodies such as pyramid, cima body, temperature is lower in the epitaxy technique, the source gas concentration is too high, growing system atmosphere is stain, and substrate surface is of poor quality, the substrate crystal orientation is unusual etc. all can cause the centrum defective; 11d is that the extension that causes in the epitaxy technique is separated out material; 11e is that described substrate 10 or substrate surface large tracts of land stacking extend to the stacking fault that described epitaxial loayer 11 forms.Can find out from above example, when the defective of described substrate 10 during near described epitaxial loayer 11, the defective of described substrate 10 can become the source in epitaxial process, and delaying defective outward can be exaggerated.So in described substrate 10 courses of processing, except very strict single crystal preparation flow process, the process that also has a step gettering, make the inducement of these defectives such as oxonium ion, metal ion etc. away from front side of silicon wafer, away from epitaxial loayer, formation is called " place of safety " or " transition region " level, and the thickness H of described " place of safety " or " transition region " is generally about 50um.
In traditional epitaxy defect analytical method, normally externally delay unusual silicon chip and carry out microscopic examination, after confirming the epitaxial surface situation, again by to confirming described epitaxial loayer 11 behind the chromic acid corrosion of the front of defective locations or side, substrate 10, substrate is to the defect kind of this transition region of extension, quantity, density, shape, size, the data such as distance, and site technique data such as epitaxial temperature, gas flow, growth rate, chamber pressure, the contents such as the intact degree inspection of body of heater, the reason of synthetic determination epitaxy defect, yet this procedure is complicated, usually all need to look for the relevant substrate of not doing extension to do simulated experiment, when suspecting the substrate problem, more need to do enough experiments so that more data to be provided, cause material, production capacity, the waste of manpower, owing to being formed with the substrate 10 of an epitaxial loayer 11 and easily existing not quite identical in material selection and the extension course of processing for the substrate of not doing extension that carries out the defect analysis contrast, limited in one's ability for epitaxy technique especially, the manufacturing and processing enterprise that technological fluctuation is larger, often unusual repeatability can't guarantee again to reappear, thereby makes the investigation and analysis of epitaxy defect have a lot of parameters.
Therefore, the utility model need to provide a kind of epitaxial structure, can avoid being formed with the substrate of extension and have not quite identical problem for the substrate of not doing extension of looking for related data in material selection and the extension course of processing.
The utility model content
The purpose of this utility model is to provide a kind of epitaxy defect analytical structure, make outer delaying at same substrate have growing epitaxial and the figure of growing epitaxial not, by contrast growth the substrate of extension and the defective correlation of the substrate of growing epitaxial are not arranged, analyze and judge that epitaxy defect comes from epitaxy technique, the front semiconductor fabrication process of extension or Semiconductor substrate.
In order to address the above problem, the utility model provides a kind of epitaxy defect analytical structure, comprising:
Semi-conductive substrate, a part of surface of described Semiconductor substrate are formed with epitaxial growth zone, expose another part surface of the described Semiconductor substrate of a barrier layer protected locality protection;
One epitaxial loayer is formed on the described epitaxial growth zone.
Further, the epitaxy defect analytical structure also comprises semiconductor structure, be formed at respectively in the described epitaxial growth zone and the described barrier layer protected zone of part in.
Further, for the used Semiconductor substrate of ambipolar circuit be＜111〉crystal orientation P type semiconductor substrate.
Further, the thickness of described epitaxial loayer is 1～100um.
Further, the horizontal and vertical minimum dimension of the figure in described barrier layer protected zone is all greater than epitaxy layer thickness.
As seen from the above technical solution, the utility model provides a kind of epitaxy defect analytical structure, comprise semi-conductive substrate and epitaxial loayer, a part of surface of described Semiconductor substrate is formed with epitaxial growth zone, exposes another part surface of the described Semiconductor substrate of a barrier layer protected locality protection; Described epitaxial loayer is formed on the described epitaxial growth zone.The epitaxy defect analytical method that the epitaxy defect analytical structure that utilizes the utility model to provide forms is compared with existing epitaxy defect analytical structure, and epitaxy defect analytical structure of the present utility model has the following advantages:
1. make extension and keep the consistency of Semiconductor substrate at same sample, the difference of semiconductor substrate materials, the fluctuation of epitaxy technique and the factors such as difference between the equipment heat are evaded;
In the epitaxy defect analytical sampling process can to the Semiconductor substrate of making on the same sample and epitaxial loayer disposable finish or the number of taking a sample less, got rid of when carrying out chromic acid corrosion technique, because the factors such as chromic acid corrosion liquid concentration, etching time guarantee the accuracy that epitaxy defect is analyzed to the fluctuation that the Semiconductor substrate do not made at same sample and epitaxial loayer cause;
3. when sampling uses that Semiconductor substrate quantity, production capacity take, the manpower time cost is starkly lower than existing method;
4. the method simple and fast possesses very strong operability, can be used for the monitoring print, even also can be used as normal product sheet and carry out subsequent technique processing, forms new product.
Description of drawings
Fig. 1 is the common epitaxy defect schematic diagram of tradition;
Fig. 2 is the schematic flow sheet of the manufacture method of the utility model epitaxy defect analytical structure;
Fig. 3 a to Fig. 3 e is the manufacture method schematic diagram of the utility model epitaxy defect analytical structure;
Fig. 4 is the schematic flow sheet of the analytical method of the utility model epitaxy defect;
Fig. 5 a is the side schematic view of epitaxy defect in the analytical method of the utility model epitaxy defect;
Fig. 5 b is the front schematic view of epitaxy defect in the analytical method of the utility model epitaxy defect.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing embodiment of the present utility model is described in detail.
A lot of details have been set forth in the following description so that fully understand the utility model.But the utility model can be implemented much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to the utility model intension, so the utility model is not subjected to the restriction of following public implementation.
The utility model is described in further detail below in conjunction with specific embodiments and the drawings, but should not limit protection range of the present utility model with this.
Referring to Fig. 2, the utility model provides a kind of manufacture method flow process of epitaxy defect analytical structure to be:
S10: semi-conductive substrate is provided;
S11: form a barrier layer in described Semiconductor substrate;
S12: remove the part barrier layer, form a barrier layer protected zone and form epitaxial growth zone in the described Semiconductor substrate that exposes;
S13: carry out epitaxy technique, growing epitaxial not on the described barrier layer protected zone, described epitaxial growth region growing extension forms an epitaxial loayer;
S14: remove described barrier layer, form an epitaxy defect analytical structure.
Take method flow shown in Figure 2 as example, 3a to 3e by reference to the accompanying drawings is described in detail a kind of manufacture method of epitaxy defect analytical structure.
S10: semi-conductive substrate is provided.
Referring to Fig. 3 a, semi-conductive substrate 31 is provided, described Semiconductor substrate 31 can be silicon substrate, germanium silicon substrate, III-V group element compound substrate or well known to a person skilled in the art other semiconductive material substrate.What adopt in the present embodiment is silicon substrate.More specifically, the silicon substrate that adopts in the present embodiment can be formed with the semiconductor device such as MOS field-effect transistor or bipolar transistor.For the used Semiconductor substrate of ambipolar circuit take＜111 the P type semiconductor substrate in crystal orientation is as main.
S11: form a barrier layer in described Semiconductor substrate.
Referring to Fig. 3 b, form a barrier layer 32 in described Semiconductor substrate 31.Described barrier layer 32 can form by a secondary growth, also can obtain in conjunction with the accumulation of idiographic flow multiple working procedure.
Concrete, the material that use on described barrier layer can be silicon dioxide or silicon nitride or polysilicon; The thickness on described barrier layer can for
Because when making the very high epitaxial loayer of quality requirement for subsequent technique, usually before extension, can arrange the polishing of HCL (hydrogen chloride) gas, the purpose of HCL gas polishing is to erode for impurity and damage layer that described Semiconductor substrate 31 surfaces are implicit, release surface stress, smoothness of improving described Semiconductor substrate 31 surfaces etc. is optimized the quality of described Semiconductor substrate 31, if the thickness on described barrier layer 32 is partially thin, light is corroded on barrier layer 32 described in the process of HCL polishing, do not reach the effect that stops, if or HCL gas polishing time is long, also can increases pattern distortion and reduce doping content.Therefore, in order to verify the whether reason of described Semiconductor substrate 31 of epitaxy defect, can not do the polishing of HCL gas in the present embodiment.
S12: remove the part barrier layer, form a barrier layer protected zone and form epitaxial growth zone in the described Semiconductor substrate that exposes.
Referring to Fig. 3 c; spare glue, exposure, development, etching on described barrier layer 32 and the technique such as remove photoresist; optionally remove the part barrier layer; make remaining part barrier layer 32 form a barrier layer protected regional 33a; in order to the Semiconductor substrate 31 of protecting barrier layer protected regional 33a to cover, form epitaxial growth zone 33b in the described Semiconductor substrate 31 that exposes.Described etching can adopt dry method or wet etching, is controlled in 10% but cross to carve, and crosses and carves the surface appearance damage that can make too much described Semiconductor substrate 31.
Further, adopt wet etching in the present embodiment, can guarantee the more intact state that retains original Semiconductor substrate 31 in surface of the epitaxial growth zone 33b that removal zone, described barrier layer exposes.The material that use on described barrier layer 32 is during as silicon dioxide, what wet etching was removed 32 employings of part barrier layer is HF (hydrofluoric acid) solution, can not corrode with buffer silicon oxide (buffered oxide etch, BOE) solution is because corrosion silicon easily appears in BOE solution when silicon chip has damage, contamination, defective.
Further; after removing the part barrier layer; in the follow-up epitaxy technique process of reality; because the edge on remaining described barrier layer 32 to epitaxial growth zone 33b can generate polycrystalline; the polycrystalline of assembling can accumulate and extend toward the barrier layer from the extension border; therefore the horizontal X of the figure of described barrier layer protected district 33a and the vertically thickness of the epitaxial loayer all made greater than subsequent technique of the minimum dimension of Y (indicating) can guarantee that the polycrystalline that the figure of described barrier layer protected district 33a can not be assembled covers.
S13: carry out epitaxy technique, growing epitaxial not on the described barrier layer protected zone, described epitaxial growth region growing extension forms an epitaxial loayer.
Referring to Fig. 3 d, carry out epitaxy technique, utilize on the Semiconductor substrate 31 with described barrier layer 32 the not characteristic of growing epitaxial, growing epitaxial not on the described barrier layer protected regional 33a, and described epitaxial growth zone 33b growing epitaxial forms an epitaxial loayer 34.Therefore, make to have on the described barrier layer protected regional 33a the not described barrier layer protected regional 33a of the corresponding step S12 of growing epitaxial district 34a the described epitaxial growth zone 33b of the corresponding step S12 of all the other region growing epitaxial region 34b.
Concrete, the parameter that described epitaxy technique adopts is: extension gas is dichlorosilane (SiH
2CL
2), impurity gas is phosphine (PH
3), deposition temperature is 1050～1200 ℃, deposition rate is 0.35um～0.45um/min.Utilizing the thickness of the epitaxial loayer of described epitaxy technique formation is 1～100um.
Further, carry out the epitaxy technique step before, in Semiconductor substrate 31 corresponding to described epitaxial growth zone 33b, make semiconductor structure.Described semiconductor structure can be the semiconductor structure that forms by making the isolation of n type buried layer and/or P type, also can be the semiconductor structure that forms by making N trap and P trap, or the semiconductor structure that forms by making the isolation of n type buried layer and/or P type, N trap and P trap.
S14: remove described barrier layer, form an epitaxy defect analytical structure.
Referring to Fig. 3 e, remove described barrier layer 32, form an epitaxy defect analytical structure.The technique on the described barrier layer 32 of described removal is given unnecessary details at this no longer one by one referring to step S12.As seen; described epitaxy defect analytical structure comprises described Semiconductor substrate 31 and epitaxial loayer 34; a part of surface of described Semiconductor substrate 31 is formed with described epitaxial growth zone 33b; and exposing another part surface of the Semiconductor substrate that described barrier layer protected regional 33a protects, described epitaxial loayer 34 is formed on the described epitaxial growth zone 33b.And; because the horizontal X of the figure of described barrier layer protected district 33a and the vertical thickness of the epitaxial loayer all made greater than subsequent technique of the minimum dimension of Y (indicating); so, the horizontal X of the figure of the Semiconductor substrate 31 that described barrier layer protected regional 33a exposes and vertically the minimum dimension of Y also greater than the thickness of epitaxial loayer.
Further; the semiconductor structure that in Semiconductor substrate 31 corresponding to described epitaxial growth zone 33b, mixes and make by carrying out N-type and/or P type; the difference on figure; in follow-up high temperature reparation; in the epitaxial process; the defective that occurs also is not identical; so after removing described barrier layer step; also can in the claimed part semiconductor substrate of described barrier layer protected regional 33a, carry out corresponding N-type; the P type mixes and/or the described semiconductor structure of non-doping graphic making; follow-up can be used to contrasts the defect situation of delaying outward, and this is to analyzing different dopant species; the concentration outside defective etc. of Yanzhong has great importance.
According to the described epitaxy defect analytical structure that provides, participate in Fig. 4, the utility model also provides a kind of flow process of analytical method of epitaxy defect to be:
S20: an epitaxy defect analytical structure is provided;
S21: described epitaxy defect analytical structure is carried out technical finesse;
S22: the epitaxial loayer that forms in the Semiconductor substrate that the barrier layer protected zone in the described epitaxy defect analytical structure is protected and the epitaxial growth zone carries out the contrast of defective correlation analysis;
S23: judge that the epitaxy defect that forms in the described epitaxial loayer comes from epitaxy technique, the front semiconductor fabrication process of extension or Semiconductor substrate.
Take method flow shown in Figure 4 as example, by reference to the accompanying drawings 3e, accompanying drawing 5a and accompanying drawing 5b are described in detail a kind of analytical method of epitaxy defect.
S20: an epitaxy defect analytical structure is provided.
Referring to Fig. 3 e, provide described epitaxy defect analytical structure.
The epitaxy defect analytical structure that the utility model provides obtains the manufacturing of same sample, therefore, make extension and kept the consistency of Semiconductor substrate at same sample, the difference of semiconductor substrate materials, the fluctuation of epitaxy technique and the factors such as difference between the equipment heat are evaded.
S21: described epitaxy defect analytical structure is carried out technical finesse.
Can carry out microexamination, chromic acid corrosion technique or ESEM (SEM) technical finesse to described epitaxy defect analytical structure.When described technical finesse was microexamination, described microscope was metallomicroscope or has the microscope of differentiating step appearance; When described technical finesse is chromic acid corrosion technique, the parameter of described chromic acid corrosion technique is: the volume ratio that adopts the chromium trioxide aqueous solution and hydrofluoric acid is 1: 1 chromic acid corrosion liquid, the volume ratio that the described chromium trioxide aqueous solution is water and chromium trioxide is 67: 33 mixed liquor, and etching time is 10 seconds～5 minutes.
S22: the epitaxial loayer that forms in the Semiconductor substrate that the barrier layer protected zone in the described epitaxy defect analytical structure is protected and the epitaxial growth zone carries out the contrast of defective correlation analysis.
After the above-mentioned technical finesse of process; the epitaxial loayer that forms in the Semiconductor substrate protected of barrier layer protected zone in described epitaxy defect analytical structure and the epitaxial growth zone respectively forms the defect point of all kinds, quantity, density, shape, size and distance, and the defect kind, quantity, density, shape, size and the distance samples that are respectively formed at described epitaxial loayer and be formed on the Semiconductor substrate of protecting in described barrier layer protected zone are carried out the contrast of defective correlation analysis.
Because the epitaxy defect analytical structure is in through the sampling process after the technical finesse, can to the Semiconductor substrate of making on the same sample and epitaxial loayer disposable finish or the number of taking a sample less, got rid of when carrying out chromic acid corrosion technique, because the factors such as chromic acid corrosion liquid concentration, etching time guarantee the accuracy that epitaxy defect is analyzed to the fluctuation that the Semiconductor substrate do not made at same sample and epitaxial loayer cause.
In addition, to the Semiconductor substrate on the same sample with epitaxial loayer is sampled and when the Semiconductor substrate on same sample and epitaxial loayer were not sampled, the Semiconductor substrate quantity of use, production capacity took, the manpower time cost is starkly lower than existing method.
S23: judge that the epitaxy defect that forms in the described epitaxial loayer comes from epitaxy technique, the front semiconductor fabrication process of extension or Semiconductor substrate.
In described defective correlation analysis comparison process, can adopt the mode of positive and side combination to carry out analysis confirmation to the feature of defect point, thereby judge that the epitaxy defect that is formed in the described epitaxial loayer comes from epitaxy technique or Semiconductor substrate.
Concrete, in the present embodiment, referring to the front schematic view shown in the defective side schematic view shown in Fig. 5 a and Fig. 5 b, wherein the 35A among Fig. 5 a is that substrate stacking fault, 35B are that the substrate surface fiber grain stains, 35C is that outer Yanzhong finds that stacking fault, 35D are that the discovery of outer Yanzhong is because defect point 35a, defect point 35b, defect point 35c, defect point 35d, defect point 35e and the defect point 35f among the stacking fault difference corresponding diagram 5b that the pyramid defective that stacking fault, the 35E that the fiber grain contamination causes is outer Yanzhong to be found and 35F are outer Yanzhong to be found.
Concrete, during epitaxy defect is analyzed, if on the utility model epitaxy defect analytical structure, contrast by the technical finesse post analysis, in the aforesaid stacking fault defect, under the identical etching condition, defect point 35a, defect point 35c, defect point 35f occurs simultaneously, and the figure of defect point 35c is greater than the figure of defect point 35a, the figure of defect point 35c is greater than defect point 35f simultaneously, the line stretcher of side observation 35C is very long until described Semiconductor substrate 31, but 35F extends limited and away from described Semiconductor substrate 31, so just can judge that itself there is defect point 35a in described Semiconductor substrate 31, and the defective of defect point 35c is caused by described Semiconductor substrate 31, and the defective of 35F can be got rid of to a great extent by described Semiconductor substrate 31 and introduces, defect point 35f can think and semiconductor process flows in doping content before the extension, annealing is repaired, clean, mechanical damage and epitaxy technique are relevant, and maximum with the epitaxy technique correlation;
Concrete, during epitaxy defect is analyzed, if on the utility model epitaxy defect analytical structure, by the contrast of technical finesse post analysis, under the identical etching condition, defect point 35b and defect point 35d occur simultaneously, structure is identical and similar, the boundary of 35B and 35D is observed again from described Semiconductor substrate 31 surfaces in the side, can think that described defect point 35b and defect point 35d are not that extension causes, and the semiconductor cleaning is relevant before the fundamental sum extension;
Concrete, during epitaxy defect is analyzed, on the utility model epitaxy defect analytical structure, contrast by the technical finesse post analysis, under the identical etching condition, erode away defective if can not erode away on the described Semiconductor substrate 31 still on the extension, defective can not be found the extension of oriented described Semiconductor substrate 31 from the side simultaneously, and behind the increase etching time without becoming large trend along described Semiconductor substrate 31 directions, basic like this can think cause in the epitaxy technique during defective.Pyramid defective 35e as shown in Fig. 5 b, it is a kind of projection that side etch 35E does not worsen serious trend yet, and the emphasis of suspection should be placed on the extension process conditions, and temperature is lower, source concentration is too dense, growth rate is too fast all can cause this type of defective.As seen, the analytical method simple and fast of the utility model epitaxy defect possesses very strong operability.
Defect analysis example cited in the present embodiment just can become apparent more for purpose, the feature and advantage that make the utility model epitaxy defect analytical structure, but be not limited to cited defect kind and the content of analysis, concrete epitaxy defect kind, structure, the origin cause of formation, formation condition, generation position etc. are very complicated, process analysis procedure analysis needs a series of analysis verification, analysis for defective in the reality is very complicated, long-term process, equipment improvement is experienced in the research that suppresses defective especially just reach present epitaxial quality level.
In addition, the pointed not characteristic of long extension of utilizing on the described barrier layer in the present embodiment, and the described epitaxy defect analytical structure that forms can also be utilized the method for testing of carrying out epitaxial thickness, alignment mark, extension amount of distortion and extension drift value, in order to monitor sample.
Need to prove, the described epitaxy defect analytical structure that forms in the present embodiment and the analytical method of epitaxy defect can be used as the method that extension detects print and test epitaxial quality, even can be used as product sheet and process, and the utility model is applicable to common epitaxial growth technology in the semiconductor manufacturing, comprise silicon, the epitaxial growth of germanium etc.
Although the utility model with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art are not within breaking away from spirit and scope of the present utility model; can make possible change and modification, therefore protection range of the present utility model should be as the criterion with the scope that the utility model claim is defined.
Claims (5)
1. epitaxy defect analytical structure comprises:
Semi-conductive substrate, a part of surface of described Semiconductor substrate are formed with epitaxial growth zone, expose another part surface of the described Semiconductor substrate of a barrier layer protected locality protection;
One epitaxial loayer is formed on the described epitaxial growth zone.
2. epitaxy defect analytical structure as claimed in claim 1 is characterized in that, also comprises semiconductor structure, be formed at respectively in the described epitaxial growth zone and the described barrier layer protected zone of part in.
3. epitaxy defect analytical structure as claimed in claim 1 is characterized in that, is＜111〉crystal orientation P type semiconductor substrate for the used Semiconductor substrate of ambipolar circuit.
4. epitaxy defect analytical structure as claimed in claim 1 is characterized in that, the thickness of described epitaxial loayer is 1～100um.
5. epitaxy defect analytical structure as claimed in claim 1 is characterized in that, the horizontal and vertical minimum dimension of the figure in described barrier layer protected zone is all greater than epitaxy layer thickness.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931118A (en) * | 2012-11-27 | 2013-02-13 | 杭州士兰集成电路有限公司 | Epitaxy defect analyzing structure and manufacturing method thereof as well as epitaxy defect analyzing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931118A (en) * | 2012-11-27 | 2013-02-13 | 杭州士兰集成电路有限公司 | Epitaxy defect analyzing structure and manufacturing method thereof as well as epitaxy defect analyzing method |
| CN102931118B (en) * | 2012-11-27 | 2015-09-02 | 杭州士兰集成电路有限公司 | The analytical method of epitaxy defect analytical structure and manufacture method and epitaxy defect |
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Granted publication date: 20130501 Effective date of abandoning: 20150902 |
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