CN202916560U - Liquid crystal display deivce - Google Patents

Liquid crystal display deivce Download PDF

Info

Publication number
CN202916560U
CN202916560U CN 201220315345 CN201220315345U CN202916560U CN 202916560 U CN202916560 U CN 202916560U CN 201220315345 CN201220315345 CN 201220315345 CN 201220315345 U CN201220315345 U CN 201220315345U CN 202916560 U CN202916560 U CN 202916560U
Authority
CN
China
Prior art keywords
substrate
via hole
insulation course
metal layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN 201220315345
Other languages
Chinese (zh)
Inventor
曹兆铿
蒋顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai AVIC Optoelectronics Co Ltd
Original Assignee
Shanghai AVIC Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai AVIC Optoelectronics Co Ltd filed Critical Shanghai AVIC Optoelectronics Co Ltd
Priority to CN 201220315345 priority Critical patent/CN202916560U/en
Application granted granted Critical
Publication of CN202916560U publication Critical patent/CN202916560U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The utility model discloses a liquid crystal display deivce which comprises a first substrate, a second substrate and an adhesive frame. An amorphous silicon grid driving circuit is arranged on the surface of the first substrate and comprises a first metal layer, a first insulation layer, a second metal layer and a second insulation layer, wherein the first insulation layer is covered on the surfaces of the first metal layer and the first substrate, and the second insulation layer is covered on the surfaces of the second metal layer and the first insulation layer. A plurality of through holes are respectively arranged in the first insulation layer and the second insulation layer and respectively disposed in a closed space formed by enclosing the adhesive frame, the first substrate and the second substrate. Therefore, vapors, carbon dioxides or other corrosive matters in the outside can be effectively prevented from entering the liquid crystal display deivce, the first metal layer and the second metal layer are prevented from being corroded, and shorting out of the amorphous silicon grid driving circuit is avoided.

Description

A kind of liquid crystal indicator
Technical field
The utility model belongs to field of liquid crystal display, relates in particular to a kind of liquid crystal indicator.
Background technology
Along with the development of informationized society, the application of electronic product, in the middle of daily life, the application of liquid crystal indicator is also more and more extensive.
Existing liquid crystal indicator is generally by two substrates that form electrode with inject that liquid crystal layer between the two substrates forms, and to electrode application voltage, rearranges the liquid crystal molecule of liquid crystal layer, and then the light quantity that sees through of adjustment.Wherein, two substrates closes by the frame rubber seal, and general user oriented substrate is used for regulating the color of display frame, is called color membrane substrates, is provided with thin film transistor (TFT) on user's the substrate dorsad, is used for controlling the voltage that is applied on the electrode, is called array base palte.On described array base palte, also be provided with grid shift register driving circuit, described grid shift register driving circuit comprises the first metal layer and the second metal level, the first metal layer (grid layer) on the first metal layer of described grid shift register driving circuit and the described array base palte in the pixel region realizes that simultaneously figure is shaped, the second metal level (source layer) on the second metal level of described grid shift register driving circuit and the described array base palte in the pixel region realizes that simultaneously figure is shaped, so described grid shift register driving circuit can be used for driving the thin film transistor (TFT) that is arranged on the array base palte.
Existing described grid shift register driving circuit is generally the amorphous silicon driving circuit, and by repeatedly film forming etching technics formation, as described in Figure 1, the physical arrangement of described the first metal layer driving circuit generally comprises:
The first metal layer 2, described the first metal layer 2 are set directly on a substrate 1 surface;
The first insulation course 3, described the first insulation course 3 covers on described the first metal layer 2 and the substrate surface 1, and is provided with the first via hole 21 in described the first insulation course 2, and described the first via hole 21 comes out described the first metal layer 2;
The second metal level 4, described the second metal level 4 are arranged on described the first insulation course 2 surfaces;
The second insulation course 5, described the second insulation course 5 covers on described the first insulation course 2 and the second metal level 4 surfaces, and be provided with the second via hole 22 in the position corresponding with the first via hole 21, to expose the first metal layer 2, be provided with the 3rd via hole 23 in the position corresponding with the second metal level 4 in addition, so that the second metal level 4 is come out, described the first via hole 21, the second via hole 22 and the 3rd via hole 23 operated by rotary motion are in the outer side of the center line of frame glue 7;
Transparency conducting layer 6, described transparency conducting layer 6 cover described the second insulation course 5 surfaces, and by be arranged on the second insulation course 5 be connected in the insulation course 3 via hole respectively with the first metal layer 2 be connected metal level 4 and be connected.
In hot and humid environment, the first metal layer 2 and second metal level 4 of the grid shift register driving circuit of existing liquid crystal indicator easily are corroded, and cause opening circuit of amorphous silicon grid driving circuit.
The utility model content
In view of this, the purpose of this utility model is to provide a kind of liquid crystal indicator, with solve existing liquid crystal indicator grid shift register driving circuit the first metal layer and the second metal level easily be corroded, cause the problem that opens circuit of amorphous silicon grid driving circuit.
This liquid crystal indicator comprises:
First substrate is provided with amorphous silicon grid driving circuit on the described first substrate surface; Second substrate, described second substrate and described first substrate are oppositely arranged, and between described first substrate and the second substrate by the gluing involution that connects of frame, it is characterized in that, described amorphous silicon grid driving circuit comprises:
The first metal layer, described the first metal layer are arranged on the first substrate surface;
The first insulation course, described the first insulation course cover on described the first metal layer and the first substrate surface;
The second metal level, described the second metal level are arranged on described the first surface of insulating layer;
The second insulation course, described the second insulation course cover on described the second metal level and the first surface of insulating layer;
Wherein, be provided with a plurality of via holes in described the first insulation course and the second insulation course, described a plurality of via hole comes out described the first metal layer and the second metal level, and described a plurality of via hole all is arranged in the confined space that is surrounded by described frame glue and first substrate, second substrate.
Preferably, described a plurality of via hole is arranged on described frame glue inward flange in the scope of 0 ~ 200 μ m.
Preferably, be provided with the first via hole in described the first insulation course, described the first via hole comes out described the first metal layer.
Preferably, be provided with the second via hole and the 3rd via hole in described the second insulation course;
Wherein, described the second via hole and the first via hole correspondence arrange and described the first metal layer are come out, and described the 3rd via hole comes out described the second metal level.
Preferably, described the first insulation course and the second insulation course are silicon nitride layer or silicon oxide layer.
Preferably, be provided with transparency conducting layer on described the second surface of insulating layer.
Preferably, described transparency conducting layer is electrically connected with described the first metal layer and the second metal level respectively by a plurality of via holes.
Preferably, be provided with pixel unit array on the described first substrate surface.
Preferably, described amorphous silicon grid driving circuit and described pixel unit array are by same technique, be formed on the described first substrate surface simultaneously.
As seen, because a plurality of via holes of liquid crystal indicator provided by the utility model are arranged in the seal cavity that is surrounded by frame glue and first substrate, second substrate, so can effectively avoid extraneous water vapor, carbon dioxide or other to have entering of corrosive material, and then avoid the first metal layer and the second metal level to be corroded, prevent the generation of amorphous silicon grid driving circuit breaking phenomena.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, the below will do to introduce simply to the required accompanying drawing that will use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is existing LCD device structure schematic diagram;
Fig. 2 is the structural representation of a kind of liquid crystal indicator of providing of the utility model;
Fig. 3 is the structural representation of the another kind of liquid crystal indicator that provides of the utility model.
Embodiment
For purpose, technical scheme and the advantage of the utility model embodiment is clearer, below in conjunction with the accompanying drawing among the utility model embodiment, technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
Just as stated in the Background Art, the first metal layer of existing liquid crystal indicator and the second metal level easily are corroded, and cause opening circuit of amorphous silicon grid driving circuit.
The inventor finds after deliberation, because existing the first via hole, the second via hole and the 3rd via hole operated by rotary motion are in the outer side of the center line of frame glue, so under hot and humid environment, extraneous water vapor, carbon dioxide etc. have corrosive material can pass through very thin transparency conducting layer and the first via hole, the second via hole, the 3rd via hole arrives the position of the first metal layer and the second metal level, and then will get the first metal layer and the second metal level is corroded, the phenomenon that causes amorphous silicon grid driving circuit to open circuit, therefore, the inventor is with the first via hole, the second via hole and the 3rd via hole are arranged on the position that extraneous corrosive substance does not arrive, and then avoid the be corroded generation of phenomenon of the first metal layer and the second metal level, the phenomenon that amorphous silicon grid driving circuit can not be opened circuit.
The utility model discloses a kind of liquid crystal indicator, comprising:
First substrate is provided with amorphous silicon grid driving circuit on the described first substrate surface; Second substrate, described second substrate and described first substrate are oppositely arranged, and between described first substrate and the second substrate by the gluing involution that connects of frame, described amorphous silicon grid driving circuit comprises:
The first metal layer, described the first metal layer are arranged on the first substrate surface;
The first insulation course, described the first insulation course cover on described the first metal layer and the first substrate surface;
The second metal level, described the second metal level are arranged on described the first surface of insulating layer;
The second insulation course, described the second insulation course cover on described the second metal level and the first surface of insulating layer;
Wherein, be provided with a plurality of via holes in described the first insulation course and the second insulation course, described a plurality of via hole comes out described the first metal layer and the second metal level, and described a plurality of via hole all is arranged in the confined space that is surrounded by described frame glue and first substrate, second substrate.
Can be found out by such scheme, a plurality of via holes of liquid crystal indicator provided by the utility model are arranged in the seal cavity that is surrounded by frame glue and first substrate, second substrate, so can effectively avoid extraneous water vapor, carbon dioxide or other to have entering of corrosive material, and then avoid the first metal layer and the second metal level to be corroded, prevent the generation of amorphous silicon grid driving circuit breaking phenomena.
It more than is the application's core concept, below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
A lot of details have been set forth in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here and implement, those skilled in the art can be in the situation that do similar popularization without prejudice to the utility model intension, so the utility model is not subjected to the restriction of following public specific embodiment.
The utility model embodiment discloses a kind of liquid crystal indicator, as shown in Figure 2, comprising:
First substrate 101, described first substrate is provided with amorphous silicon grid driving circuit on 101 surfaces;
Second substrate 102, described second substrate 102 is oppositely arranged with described first substrate 101, and passes through frame glue 103 bonding involutions between described first substrate 101 and the second substrate 102.
Wherein, described amorphous silicon grid driving circuit specifically comprises:
The first metal layer 111, described the first metal layer 111 are arranged on first substrate 101 surfaces;
The first insulation course 112, described the first insulation course 112 covers on described the first metal layer 111 and first substrate 101 surfaces, and described the first insulation course 112 is preferably silicon nitride layer or monox;
The second metal level 113, described the second metal level 113 are arranged on described the first insulation course 112 surfaces;
The second insulation course 114, described the second insulation course 114 cover on described the second metal level 113 and the first insulation course 112 surfaces, and described the second insulation course 114 is preferably silicon nitride layer or monox;
Wherein, be provided with a plurality of via holes 30 in described the first insulation course 112 and the second insulation course 114, described a plurality of via hole 30 comes out described the first metal layer 111 or the second metal level 112, and described a plurality of via hole 30 all is arranged on by described frame glue 103 and first substrate 101, (described by described frame glue 103 and first substrate 101 in the confined space that second substrate 102 surrounds, the confined space that second substrate 102 surrounds is that frame glue 103 right sides are near the part of liquid crystal indicator viewing area), and described a plurality of via hole 30 is arranged on described frame glue 103 in the scope of 0 ~ 200 μ m, preferred, described a plurality of via holes 30 are arranged on described frame glue 103 in the scope of 50 μ m ~ 150 μ m.
Be provided with transparency conducting layer 115 on described the second insulation course 114 surfaces, described transparency conducting layer 115 is preferably indium tin oxide layer or silver oxide zinc layer or other transparency conducting layer, and described transparency conducting layer 115 is electrically connected with described the first metal layer 111 and the second metal level 113 respectively by a plurality of via holes 30.
Because extraneous water vapor, carbon dioxide or other have corrosive material and are difficult to enter by described frame glue 103 and first substrate 101, in the confined space that second substrate 102 surrounds, so, the inventor all is arranged on described a plurality of via holes 30 by described frame glue 103 and first substrate 101, in the confined space that second substrate 102 surrounds, and then avoid extraneous water vapor, carbon dioxide or other have 115 pairs of the first metal layers 111 of corrosive material permeance transparency conducting layer and the second metal level 113 causes corrosion prevents the generation of amorphous silicon grid driving circuit breaking phenomena.
Be provided with the pixel unit array (not shown) on described first substrate 101 surfaces, described pixel unit array is positioned at the confined space that is surrounded by described frame glue 103 and first substrate 101, second substrate 102, be used for realizing the picture disply of liquid crystal indicator, and, between described pixel unit array and the described frame glue 103 at a distance of the distance of 400 μ m ~ 500 μ m, therefore, the equal position between described frame glue 103 and pixel unit array of described a plurality of via hole.
In the present embodiment, described amorphous silicon grid driving circuit and described pixel unit array are by same technique, be formed on described first substrate 101 surfaces simultaneously.
Another embodiment of the utility model discloses another kind of liquid crystal indicator, as shown in Figure 3, comprising:
First substrate 101, described first substrate is provided with amorphous silicon grid driving circuit on 101 surfaces;
Second substrate 102, described second substrate 102 is oppositely arranged with described first substrate 101, and passes through frame glue 103 bonding involutions between described first substrate 101 and the second substrate 102.
Wherein, described amorphous silicon grid driving circuit specifically comprises:
The first metal layer 111, described the first metal layer 111 are arranged on first substrate 101 surfaces;
The first insulation course 112, described the first insulation course 112 covers on described the first metal layer 111 and first substrate 101 surfaces, and described the first insulation course 112 is preferably silicon nitride layer or monox;
The second metal level 113, described the second metal level 113 are arranged on described the first insulation course 112 surfaces, and described the second insulation course 114 is preferably silicon nitride layer or monox;
The second insulation course 114, described the second insulation course 114 cover on described the second metal level 113 and the first insulation course 112 surfaces;
Wherein, be provided with the first via hole 31 in described the first insulation course 112, described the first via hole 31 comes out described the first metal layer 111; Be provided with the second via hole 32 and the 3rd via hole 33 in described the second insulation course 114, described the second via hole 32 and the first via hole 31 corresponding settings, and described the first metal layer 111 is come out, described the 3rd via hole 33 comes out described the second metal level 113.
Wherein, described the first via hole 31, the second via hole 32 and the 3rd via hole 33 are arranged on by described frame glue 103 and first substrate 101, (described by described frame glue 103 and first substrate 101 in the confined space that second substrate 102 surrounds, the confined space that second substrate 102 surrounds is that frame glue 103 right sides are near the part of liquid crystal indicator viewing area), and concrete, described the first via hole 31, the second via hole 32 and the 3rd via hole 33 are arranged on described frame glue 103 in the scope of 0 ~ 200 μ m, preferred, described the first via hole 31, the second via hole 32 and the 3rd via hole 33 are arranged on described frame glue 103 in the scope of 50 μ m ~ 150 μ m.
Be provided with transparency conducting layer 115 on described the second insulation course 114 surfaces, described transparency conducting layer 115 is preferably indium tin oxide layer or silver oxide zinc layer or other transparency conducting layer, described transparency conducting layer 115 is electrically connected with described the first metal layer 111 and the second metal level 113 respectively by the first via hole 31, the second via hole 32 and the 3rd via hole 33, finally realizes being electrically connected between described the first metal layer 111 and the second metal level 113.
Because extraneous water vapor, carbon dioxide or other have corrosive material and are difficult to enter by described frame glue 103 and first substrate 101, in the confined space that second substrate 102 surrounds, so, the inventor is with described the first via hole 31, the second via hole 32 and the 3rd via hole 33 all are arranged on by described frame glue 103 and first substrate 101, in the confined space that second substrate 102 surrounds, and then avoid extraneous water vapor, carbon dioxide or other have 115 pairs of the first metal layers 111 of corrosive material permeance transparency conducting layer and the second metal level 113 causes corrosion prevents the generation of amorphous silicon grid driving circuit breaking phenomena.
Be provided with the pixel unit array (not shown) on described first substrate 101 surfaces, described pixel unit array is positioned at the confined space that is surrounded by described frame glue 103 and first substrate 101, second substrate 102, be used for realizing the picture disply of liquid crystal indicator, and, between described pixel unit array and the described frame glue 103 at a distance of the distance of 400 μ m ~ 500 μ m, therefore, the equal position between described frame glue 103 and pixel unit array of described the first via hole 31, the second via hole 32 and the 3rd via hole 33.
In the present embodiment, described amorphous silicon grid driving circuit and described pixel unit array are by same technique, be formed on described first substrate 101 surfaces simultaneously.
Various piece adopts the mode of going forward one by one to describe in this instructions, and what each part stressed is and the difference of other parts that identical similar part is mutually referring to getting final product between the various piece.
To the above-mentioned explanation of the disclosed embodiments, this area professional and technical personnel can be realized maybe will using the utility model.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can be in the situation that do not break away from spirit or scope of the present utility model, in other embodiments realization.Therefore, the utility model will can not be restricted to embodiment illustrated herein, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims (9)

1. liquid crystal indicator, comprising: first substrate is provided with amorphous silicon grid driving circuit on the described first substrate surface; Second substrate, described second substrate and described first substrate are oppositely arranged, and between described first substrate and the second substrate by the gluing involution that connects of frame, it is characterized in that, described amorphous silicon grid driving circuit comprises:
The first metal layer, described the first metal layer are arranged on the first substrate surface;
The first insulation course, described the first insulation course cover on described the first metal layer and the first substrate surface;
The second metal level, described the second metal level are arranged on described the first surface of insulating layer;
The second insulation course, described the second insulation course cover on described the second metal level and the first surface of insulating layer;
Wherein, be provided with a plurality of via holes in described the first insulation course and the second insulation course, described a plurality of via hole comes out described the first metal layer and the second metal level, and described a plurality of via hole all is arranged in the confined space that is surrounded by described frame glue and first substrate, second substrate.
2. described display device according to claim 1 is characterized in that, described a plurality of via holes are arranged on described frame glue inward flange in the scope of 0 ~ 200 μ m.
3. described display device according to claim 1 is characterized in that, be provided with the first via hole in described the first insulation course, described the first via hole comes out described the first metal layer.
4. described display device according to claim 3 is characterized in that, is provided with the second via hole and the 3rd via hole in described the second insulation course;
Wherein, described the second via hole and the first via hole correspondence arrange and described the first metal layer are come out, and described the 3rd via hole comes out described the second metal level.
5. described display device according to claim 1 is characterized in that, described the first insulation course and the second insulation course are silicon nitride layer or silicon oxide layer.
6. described display device according to claim 1 is characterized in that, is provided with transparency conducting layer on described the second surface of insulating layer.
7. described display device according to claim 6 is characterized in that, described transparency conducting layer is electrically connected with described the first metal layer and the second metal level respectively by a plurality of via holes.
8. described display device according to claim 1 is characterized in that, described first substrate is provided with pixel unit array on the surface.
9. described display device according to claim 8 is characterized in that, described amorphous silicon grid driving circuit and described pixel unit array are by same technique, be formed on the described first substrate surface simultaneously.
CN 201220315345 2012-06-29 2012-06-29 Liquid crystal display deivce Expired - Lifetime CN202916560U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220315345 CN202916560U (en) 2012-06-29 2012-06-29 Liquid crystal display deivce

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220315345 CN202916560U (en) 2012-06-29 2012-06-29 Liquid crystal display deivce

Publications (1)

Publication Number Publication Date
CN202916560U true CN202916560U (en) 2013-05-01

Family

ID=48164861

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201220315345 Expired - Lifetime CN202916560U (en) 2012-06-29 2012-06-29 Liquid crystal display deivce

Country Status (1)

Country Link
CN (1) CN202916560U (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107315294A (en) * 2017-07-25 2017-11-03 深圳市华星光电技术有限公司 A kind of preparation method of display base plate, display panel and display base plate
WO2019085067A1 (en) * 2017-10-30 2019-05-09 深圳市华星光电技术有限公司 Liquid crystal display panel and preparation method therefor
CN110531555A (en) * 2018-05-24 2019-12-03 瀚宇彩晶股份有限公司 Display panel
CN111308794A (en) * 2020-02-28 2020-06-19 Tcl华星光电技术有限公司 Display panel and display device
CN113219740A (en) * 2021-04-20 2021-08-06 绵阳惠科光电科技有限公司 Display panel and display device
CN113359359A (en) * 2021-04-20 2021-09-07 绵阳惠科光电科技有限公司 Display panel and display device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107315294A (en) * 2017-07-25 2017-11-03 深圳市华星光电技术有限公司 A kind of preparation method of display base plate, display panel and display base plate
WO2019085067A1 (en) * 2017-10-30 2019-05-09 深圳市华星光电技术有限公司 Liquid crystal display panel and preparation method therefor
CN110531555A (en) * 2018-05-24 2019-12-03 瀚宇彩晶股份有限公司 Display panel
CN111308794A (en) * 2020-02-28 2020-06-19 Tcl华星光电技术有限公司 Display panel and display device
CN113219740A (en) * 2021-04-20 2021-08-06 绵阳惠科光电科技有限公司 Display panel and display device
CN113359359A (en) * 2021-04-20 2021-09-07 绵阳惠科光电科技有限公司 Display panel and display device
WO2022222543A1 (en) * 2021-04-20 2022-10-27 绵阳惠科光电科技有限公司 Display panel and display apparatus
CN113359359B (en) * 2021-04-20 2023-08-25 绵阳惠科光电科技有限公司 Display panel and display device
CN113219740B (en) * 2021-04-20 2023-08-29 绵阳惠科光电科技有限公司 Display panel and display device

Similar Documents

Publication Publication Date Title
CN202916560U (en) Liquid crystal display deivce
CN104503131B (en) Color membrane substrates and display device
CN105446031B (en) Display panel and display device
JP5847061B2 (en) Array substrate and manufacturing method thereof
US8159641B2 (en) Array substrate having common electrode with slits that overlap data lines, and liquid crystal display apparatus having the array substrate
JP5627768B2 (en) Display device
KR101985246B1 (en) Thin film transistor substrate having metal oxide and manufacturing method thereof
US7715089B2 (en) Electrophoretic display panel and method of fabricating the same
JP2015511026A (en) Array substrate, method for manufacturing the same, and display device
TW200700807A (en) Liquid crystal display device having common electrodes with reduced resistance and method for fabricating the same
CN103311253B (en) Thin-film transistor array base-plate and preparation method thereof and liquid crystal indicator
CN106886107A (en) Display panel
CN203133452U (en) Array substrate and liquid crystal display device
KR20080001769A (en) Liquid crystal display device and fabricating method of the same
WO2013139192A1 (en) Touch liquid crystal display device, liquid crystal display panel and upper substrate
JP2007206135A5 (en)
CN204270000U (en) A kind of array base palte and display panels
CN107346083A (en) Display device
US20170256649A1 (en) Semiconductor device
CN102779783B (en) Pixel structure, as well as manufacturing method and display device thereof
TW201205178A (en) Electrophoretic display device and method for manufacturing the same
WO2009019917A1 (en) Liquid crystal panel, liquid crystal display unit, liquid crystal display device, and television receiver
CN106298809B (en) Thin-film transistor array base-plate and preparation method thereof, liquid crystal display device
TWI529584B (en) Touch display device, driving method thereof and manufacturing method thereof
JP2014092771A (en) Liquid crystal display device

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20130501

CX01 Expiry of patent term