CN202903992U - Control panel for program-controlled standard source - Google Patents
Control panel for program-controlled standard source Download PDFInfo
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- CN202903992U CN202903992U CN 201220529376 CN201220529376U CN202903992U CN 202903992 U CN202903992 U CN 202903992U CN 201220529376 CN201220529376 CN 201220529376 CN 201220529376 U CN201220529376 U CN 201220529376U CN 202903992 U CN202903992 U CN 202903992U
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Abstract
The utility model discloses a control panel for a program-controlled standard source. The control panel is formed by an RS-232 transceiver drive chip, an FPGA chip, a DAC chip and an operational amplifier. The DAC chip carries out digital to analog conversion on standard source data sent by the FPGA chip to obtain two paths of analog current signals, a first path of analog current signal is used as a current signal outputted by the control panel of the program-controlled standard source, and a second path of analog current signal is transmitted to an inverting input terminal of the operational amplifier. A voltage signal outputted by an output end of the operational amplifier is used as a voltage signal outputted by the control panel of the program-controlled standard source. The RS-232 transceiver drive chip carries out level conversion on an RS-232 level parameter transmitted from outside and outputs a TTL level parameter to the FPGA chip. The operational amplifier converts the second analog current signal transmitted by the DAC chip into an analog voltage signal, and an output of the operational amplifier is used as a voltage signal outputted by the control panel for the program-controlled standard source. The control panel has the advantages of simple realization, low cost and convenient maintenance.
Description
Technical field
The utility model relates to a kind of control panel, is specifically related to a kind of control panel for the programmed criteria source, belongs to the power automation technical field.
Background technology
In electric system, because the existence of the non-linear electrical equipments such as large-scale power start stop apparatus, rectifying installation, converter plant, the undulatory property of non-linear (harmonic wave) of electrical network is larger, cause power system voltage, current waveform seriously to distort, the degree of unbalancedness of voltage, electric current is strengthened, and the quality of power supply descends.Therefore, in electric system, instrument and meter calibration and power quality index test all need special signal source, and it mainly provides high precision industrial frequency harmonic detection signal 2～21 times.
The signal ability good stability that traditional low-frequency harmonics detection signal that utilizes electronic circuit to produce only has frequency to produce more than 1kHz if produce several hertz to tens hertz low frequency signal, just is difficult for realizing with mimic channel.And in the market, the control panel of standard source is main mainly with producing sophisticated signal, and its precision and real-time all do not meet the requirement that electric system is used.
Summary of the invention
The purpose of this utility model be not high for the precision that overcomes the existing standard source, computing velocity is slow and realize the defective of more complicated technology, satisfy the requirement that electric system is used, and a kind of control panel for the programmed criteria source be provided.
For achieving the above object, the technical scheme that the utility model adopts is:
A kind of control panel for the programmed criteria source is characterized in that: drive chip, fpga chip, DAC chip and operational amplifier by the RS-232 transceiver and consist of; Described DAC chip carries out digital-to-analog conversion to the standard source data that fpga chip is sent here, obtain the two-way analog current signal, first via analog current signal is as the current signal of the control panel output in programmed criteria source, the the second road analog current signal is delivered to the operational amplifier inverting input, and the voltage signal of the output terminal output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source; Described RS-232 transceiver drives chip the RS-232 level parameters that the outside sends is carried out level conversion, and output Transistor-Transistor Logic level parameter is given fpga chip; Described operational amplifier is converted to analog voltage signal to the second analog current signal that the DAC chip is sent to, and the output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source.
The control method of described control panel for the programmed criteria source is:
The DAC chip carries out digital-to-analog conversion to the standard source data that fpga chip is sent here, obtain the two-way analog current signal, first via analog current signal is as the current signal of the control panel output in programmed criteria source, the second analog current signal is delivered to the operational amplifier inverting input, and the voltage signal of the output terminal output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source;
The RS-232 transceiver drives chip the RS-232 level parameters that the outside sends is carried out level conversion, and output Transistor-Transistor Logic level parameter is given fpga chip;
Operational amplifier is converted to analog voltage signal to the second analog current signal that the DAC chip is sent to, and the output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source.
Described fpga chip operation may further comprise the steps:
1) acquiescence first-harmonic and harmonic parameters are set;
2) receive outside programmed criteria source signal frequency and the phase information that sends by RS-232 transceiver driving chip;
3) judge whether Wave data and initial phase will change;
If Wave data and initial phase do not need to change, enter 5) step, if Wave data and initial phase any one need to change, what need not change enters 5) step, need the execution 4 that changes) step;
Whether 4) calculate first-harmonic and harmonic data and prima facies place value will change;
5) directly frequency synthesis (DDS) technology utilizes fundamental frequency control word and fundamental phase control word to export respectively frequency and the phase place of first-harmonic, generates the first-harmonic data;
The DDS technology is utilized harmonic frequency control word and harmonic phase control word respectively frequency and the phase place of output harmonic wave, generates harmonic data;
Each time clock, phase register increases progressively with step-length M, the output of phase register and phase control words addition, its result is as the address of waveform look-up table; The deposit data of waveform look-up table is in ROM, and there is the digital amplitude information of the waveform signal of one-period inside, and the address of each look-up table is corresponding to a phase point in 0 °～360 ° scopes in the sine wave; Look-up table is mapped to the location information of input the digital amplitude signal of waveform;
6) obtain the standard source data after the stack of first-harmonic data and harmonic data;
7) by logic control signal, the standard source data are delivered to the DAC chip.
Advantage and beneficial effect that the utility model has compared with prior art are:
The utility model receives the external control parameter, and produces corresponding standard source electric current and voltage signal as the input of power amplification plate.The program of the control panel in this programmed criteria source all uses Verilog HDL language to realize in FPGA, but online programming is easy to realize and upgrading; FPGA parallel processing speed is exceedingly fast, and has improved computing velocity; Use the DDS technology to improve to a certain extent computational accuracy; The utility model is realized simply, cost is lower, easy to maintenance.
Description of drawings
Fig. 1 is the utility model organigram;
Fig. 2 is signal product process figure.
Embodiment
As shown in Figure 1, a kind of control panel for the programmed criteria source, drive chip by the RS-232 transceiver, fpga chip, DAC chip and operational amplifier consist of, the Transistor-Transistor Logic level that the RS-232 transceiver drives chip sends data, the Transistor-Transistor Logic level receive data, and the control signal of DAC chip, data bus signal connects respectively the corresponding I/O pin of fpga chip, the first analog current signal of DAC chip output is as the current signal of the control panel output in programmed criteria source, the inverting input of the second analog current signal concatenation operation amplifier U4 of DAC chip output, the output terminal of operational amplifier U4 is as the voltage signal of the control panel output in programmed criteria source.
Described control panel for the programmed criteria source as shown in Figure 1, the RS-232 transceiver drives chip MAX3223TTL level and sends data pins 17 and are connected the corresponding I/O pin that connects respectively fpga chip XC3S50A with Transistor-Transistor Logic level receive data pin one; The write control signal pin one 8 of DAC chip AD5547 control bus, register control signal pin two 1, register reset signal pin two 3, chip reset signal pin 22, high address signal pin 19 is connected the corresponding I/O pin that connects respectively fpga chip XC3S50A with the low address signal pin, DAC chip AD5547 data bus D[15:0] pin one, pin two, pin 38, pin 37, pin 36, pin 35, pin 34, pin 33, pin 32, pin 31, pin 30, pin two 8, pin two 7, pin two 6, pin two 5 is connected the corresponding I/O pin that connects respectively fpga chip XC3S50A with pin two, the first analog current signal pin 8 of DAC chip AD5547 is directly exported for the current signal of the control panel in programmed criteria source, the second analog current signal pin one 2 of DAC chip AD5547 and secondary signal ground pin one 1 be inverting input pin two and the positive input pin 3 of concatenation operation amplifier AD8512 respectively, and operational amplifier A D8512 output terminal pin one is the voltage signal output of the control panel in programmed criteria source.
As shown in Figure 2, described fpga chip U2 main program may further comprise the steps:
1) the acquiescence fundamental frequency being set is that 50Hz and fundamental phase are that 0,2～21 subharmonic number of times are that 0 and 2～21 subharmonic phase places are 0;
2) receive the outside parameter informations such as signal frequency that chip sends and phase place that drive by the RS-232 transceiver;
3) judge whether Wave data and initial phase will change;
If Wave data and initial phase do not need to change, enter 5) step, if Wave data and initial phase any one need to change, what need not change enters 5) step, need the execution 4 that changes) step;
Whether 4) calculate first-harmonic and harmonic data and prima facies place value will change;
5) the DDS technology utilizes fundamental frequency control word and fundamental phase control word to export respectively frequency and the phase place of first-harmonic, generates the first-harmonic data;
The DDS technology is utilized harmonic frequency control word and harmonic phase control word respectively frequency and the phase place of output harmonic wave, generates harmonic data;
To each periodic sampling 36000 point of every road signal, can guarantee that the phase adjusted fineness reaches 0.01 ° (360 °/36000).Each time clock, phase register increases progressively with step-length 0.01.The output of phase register and phase control words addition, its result is as the address of waveform look-up table.The deposit data of waveform look-up table is in ROM, and there is the digital amplitude information of the waveform signal of one-period inside, and the address of each look-up table is corresponding to a phase point in 0 °～360 ° scopes in the sine wave.Look-up table is mapped to the location information of input the digital amplitude signal of waveform.
6) obtain the standard source data after the stack of first-harmonic data and harmonic wave signal data;
7) by logic control signal, the standard source data are delivered to DAC chip U3;
As shown in Figure 1, described DAC chip AD5547 mainly carries out digital-to-analog conversion to the standard source data that fpga chip XC3S50A sends here, and its current signal amplitude adopts the 16bit binary data, and signal distortion is 0.002%.Obtain the two-way analog current signal, first via analog current signal is as the current signal of the control panel output in programmed criteria source, the second analog current signal is delivered to operational amplifier A D8512 inverting input, and the voltage signal of the output terminal output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source;
As shown in Figure 1, described RS-232 transceiver drives the RS-232 level parameters that chip MAX3223 mainly sends the outside and carries out level conversion, and the RS-232 transceiver drives chip MAX3223TTL level and sends data pins 17 and are connected the corresponding I/O pin that connects respectively fpga chip XC3S50A with Transistor-Transistor Logic level receive data pin one;
As shown in Figure 1, described operational amplifier A D8512 mainly is converted to analog voltage signal to the second analog current signal that DAC chip AD5547 is sent to, and the output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source.
Claims (1)
1. a control panel that is used for the programmed criteria source is characterized in that: drive chip, fpga chip, DAC chip and operational amplifier by the RS-232 transceiver and consist of; Described DAC chip carries out digital-to-analog conversion to the standard source data that fpga chip is sent here, obtain the two-way analog current signal, first via analog current signal is as the current signal of the control panel output in programmed criteria source, the the second road analog current signal is delivered to the operational amplifier inverting input, and the voltage signal of the output terminal output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source; Described RS-232 transceiver drives chip the RS-232 level parameters that the outside sends is carried out level conversion, and output Transistor-Transistor Logic level parameter is given fpga chip; Described operational amplifier is converted to analog voltage signal to the second analog current signal that the DAC chip is sent to, and the output of operational amplifier is as the voltage signal of the control panel output in programmed criteria source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220529376 CN202903992U (en) | 2012-10-16 | 2012-10-16 | Control panel for program-controlled standard source |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220529376 CN202903992U (en) | 2012-10-16 | 2012-10-16 | Control panel for program-controlled standard source |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202903992U true CN202903992U (en) | 2013-04-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220529376 Expired - Fee Related CN202903992U (en) | 2012-10-16 | 2012-10-16 | Control panel for program-controlled standard source |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202903992U (en) |
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2012
- 2012-10-16 CN CN 201220529376 patent/CN202903992U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130424 Termination date: 20151016 |
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| EXPY | Termination of patent right or utility model |