CN202841103U - Circuit for carrying out digital linearity compensation on voltage/frequency conversion circuit - Google Patents
Circuit for carrying out digital linearity compensation on voltage/frequency conversion circuit Download PDFInfo
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- CN202841103U CN202841103U CN 201220304044 CN201220304044U CN202841103U CN 202841103 U CN202841103 U CN 202841103U CN 201220304044 CN201220304044 CN 201220304044 CN 201220304044 U CN201220304044 U CN 201220304044U CN 202841103 U CN202841103 U CN 202841103U
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Abstract
The utility model belongs to a compensation circuit and in particular to a circuit for carrying out digital linearity compensation on a voltage/frequency conversion circuit. The circuit comprises six-bit binary counting/frequency-dividing devices, the output of the first six-bit binary counting/frequency-dividing device is separately connected with a six-input AND gate and 64 groups of six-input AND gate arrays, the output of the 64 groups of six-input AND gate arrays is connected with a one-out-of-sixty-four data selector, the output of the six-input AND gate is separately connected with a two-input AND gate and a six-bit latch, the output of the two-input AND gate is separately connected with the second six-bit binary counting/frequency-dividing device and a D trigger, the output of the second six-bit binary counting/frequency-dividing device is connected with the six-bit latch, the output of the six-bit latch is connected with the one-out-of-sixty-four data selector, and the output of the one-out-of-sixty-four data selector is connected with the D trigger. The circuit for carrying out digital linearity compensation on the voltage/frequency conversion circuit has the advantages that the output frequency of the voltage/frequency conversion circuit can be changed, and linearity compensation can be carried out on the voltage/frequency conversion circuit.
Description
Technical field
The utility model belongs to compensating circuit, is specifically related to a kind of circuit that the voltage/frequency change-over circuit is carried out the compensation of digital linear degree.
Background technology
The voltage/frequency change-over circuit can be divided into charge balancing circuit on principle, feedback reference current source circuit, the functional module of the three basics such as synchronous logic control circuit.The chief component of charge balancing circuit is integrator; The major function of synchronous logic control circuit provides reference frequency, detects the output voltage of integrator, determines accordingly polarity and the feedback time of feedback current; The feedback reference current source is as the electric current counterweight of voltage/frequency conversion.The operation principle of voltage/frequency change-over circuit is: when circuit had the voltage signal input, input voltage was added to the integrator input by integrating resistor with current forms, and integrator output voltage begins to increase.When the output voltage values of integrator surpasses the threshold voltage of setting, under the effect of synchronous logic control circuit, to introduce and the opposite polarity feedback reference electric current of integrator input voltage, this electric current directly is added to the inverting input of integration amplifier.Under this state, integrator to the electric current to be converted that is added to simultaneously its input and feedback reference electric current and carry out integration, the output voltage values of integrator is reduced to below the threshold voltage.After the synchronous logic control circuit detects integrator output voltage and is lower than threshold voltage, will close the feedback reference current channel, under the independent role of electric current to be converted, integrator output voltage begins again to increase, and surpasses threshold voltage.More than two processes go round and begin again, change up and down around the threshold voltage of setting with the output voltage that guarantees integrator.The number of times of introducing the feedback reference electric current in unit interval is the output frequency of voltage/frequency change-over circuit.
The scale factory non-linearity degree is one of important technology index of voltage/frequency change-over circuit, and it has reflected the voltage/frequency change-over circuit in the conversion range ability, corresponding different input voltages, the inconsistency of circuit constant multiplier.The linearity compensation of voltage/frequency change-over circuit is by the feedback reference current source is compensated, and namely the electric current counterweight of bucking voltage/freq converting circuit is realized.
Summary of the invention
The utility model provides a kind of circuit that the voltage/frequency change-over circuit is carried out the compensation of digital linear degree for the defective of prior art.
Summary of the invention: a kind of circuit that the voltage/frequency change-over circuit is carried out the compensation of digital linear degree comprises six binary counting/frequency dividers (1), six inputs and door (2), two inputs and door (3); The output of six binary counting/frequency dividers (1) respectively with six inputs and door (2) with are connected 14 group six input gate array (4) and be connected; The output and 64 of 64 group of six input gate array (4) selects a data selector (7) to be connected; The output of six inputs and door (2) respectively with two inputs and (3) with are connected a latch (6) and are connected; Two inputs are connected 8 with six binary counting/frequency dividers (5) with d type flip flop respectively with the output of door (3)) be connected; The output of six binary counting/frequency dividers (5) is connected with six latchs (6); The output and 64 of six latchs (6) selects a data selector (7) to be connected; 64 select the output of a data selector (7) to be connected with d type flip flop (8); The output of d type flip flop (8) is connected with resistor (9); The output of resistor (9) is connected 11 with resistor (10) with capacitor respectively) be connected; The output of resistor (10) is connected with feedback reference current source (12).
Effect of the present utility model is: a kind of digital compensating circuit that can bucking voltage/freq converting circuit scale factory non-linearity, by the output frequency of voltage/frequency change-over circuit is measured, according to the frequency values that records, choose the compensating parameter of coupling, the PWM ripple that generates corresponding duty ratio is waveform by way of compensation, the compensation waveform is after low-pass filtering, be converted to the direct voltage amount, this voltage is converted to offset current access in parallel feedback reference current source by compensating resistor, in order to adjust the amplitude of feedback current, thereby reach the output frequency that changes the voltage/frequency change-over circuit, the voltage/frequency change-over circuit is carried out the purpose of linearity compensation.
Description of drawings
This novel electrical block diagram that circuit is provided of Fig. 1.
Fig. 2 cyclical signal PA, PB oscillogram.
Fig. 3 duty ratio is 63/128 compensation oscillogram.
1. six binary counting/frequency dividers; 2. six inputs and door; 3. two inputs and door; 4. input gate array for 64 group six; 5. six binary counting/frequency dividers; 6. six latchs; 7. 64 select a data selector; 8.D trigger; 9. resistor; 10. resistor; 11. capacitor; 12. feedback reference current source.
Embodiment
Below in conjunction with drawings and Examples to this novel being described further.
As shown in Figure 1, a kind of circuit that the voltage/frequency change-over circuit is carried out the compensation of digital linear degree comprises six binary counting/frequency dividers 1, six inputs and door 2, two inputs and door 3; The output of six binary counting/frequency dividers 1 respectively with six inputs and door 2 with are connected 14 group six input gate array 4 and be connected; The output and 64 of 64 group of six input gate array 4 selects a data selector 7 to be connected; Six inputs and door 2 output respectively with two inputs with 3 with are connected a latch 6 and are connected; Two inputs and 3 output are connected with d type flip flop with six binary counting/frequency dividers 5 respectively and are connected; The output of six binary counting/frequency dividers 5 is connected with six latchs 6; The output of six latchs 6 and 64 selects a data selector 7 to be connected; 64 select the output of a data selector 7 to be connected with d type flip flop 8; The output of d type flip flop 8 is connected with resistor 9; The output of resistor 9 is connected with capacitor with resistor 10 respectively and is connected; The output of resistor 10 is connected with feedback reference current source 12.
Operation principle of the present invention and the course of work are as follows: the square-wave signal CP of 128kHz and the output frequency FOUT of voltage/frequency change-over circuit are as a kind of input signal of digital compensating circuit that can bucking voltage/freq converting circuit scale factory non-linearity.Wherein the square-wave signal CP of 128kHz obtains square-wave signal Q0～Q5 of 2kHz～64kHz behind six binary counting/frequency divider 1 frequency divisions.Square-wave signal Q0～Q5 accesses the input pin of 64 group of six input gate array 4,64 group of six input be integrated 64 six inputs and door in the gate array 4, square-wave signal Q0～Q5 carries out different combinations, can obtain altogether 64 kinds of compound modes, accessing respectively 64 six inputs annotates with the input of door: only under this a kind of compound mode of Q0Q1Q2Q3Q4Q5, six inputs connect respectively Q0～Q5 signal with six inputs of door; Under other compound modes, six inputs have the input that does not connect Q0～Q5 signal with door, such input all connects high level, the output signal D0～D63 of 64 six inputs and door is as the output signal of 64 group of six input gate array 4, accesses the 64 data input pins that select a data selector 7.Square-wave signal Q0～Q5 obtains frequency behind six inputs and door 2 be 2kHz, and duty ratio is 1/64 cyclical signal PB.The square-wave signal CP of cyclical signal PB and 128kHz obtains frequency behind two inputs and door 3 be 2kHz, and duty ratio is 1/128 cyclical signal PA.The counting input pin of six binary counting/frequency dividers 5 of output frequency FOUT access of voltage/frequency change-over circuit, two inputs are 2kHz with the frequency of door 3 outputs, duty ratio is the reset pin of six binary counting/frequency dividers 5 of 1/128 cyclical signal PA access, and this pin high level is effective.The output frequency FOUT of 5 pairs of voltage/frequency change-over circuits of six binary counting/frequency dividers counts, six count output signals of counter are A0～A5, the PA signal with the frequency of 2kHz to six binary counting/frequency dividers 5 reset, zero clearing, prevent that counter is saturated.Six count output signal A0～A5 of six binary counting/frequency dividers 5 are as the input signal of six latchs 6, six inputs are 2kHz with the frequency of door 2 outputs, duty ratio be six latchs 6 of 1/64 cyclical signal PB access latch the control pin, this pin rising edge is effective.The PB signal latchs with six count output signal A0～A5 of 6 pairs of six binary counting/frequency dividers 5 of six latchs of FREQUENCY CONTROL of 2kHz, and six output signals of six latchs 6 are B0～B5.Can be found out by Fig. 2 cyclical signal PA, PB oscillogram, the latch control signal PB signal rising edge of six latchs 6 is early than the reset signal PA signal high level of six binary counting/frequency dividers 5, before six binary counting/frequency dividers 5 reset its output signal latched guaranteeing.The output signal B0 of six latchs 6～B5 accesses the 64 address input pins that select a data selector 7,64 select a data selector 7 to select the signal D0～D63 of the data input pin of a data selector 7 to carry out gating according to address signal B0～B5 to 64, make one road signal wherein as the 64 clock signal input pins that select the output signal access d type flip flop 8 of a data selector 7.Two inputs are 2kHz with the frequency of door 3 outputs, duty ratio is the reset pin of 1/128 cyclical signal PA access d type flip flop 8, this pin high level is effective, the PA signal resets to d type flip flop 8 with the frequency of 2kHz, the D end input pin of d type flip flop 8 connects the power supply of d type flip flop 8, namely keeps high level.The Q end of d type flip flop 8 is output as the cyclical signal of frequency 2kHz, when the reset signal PA of d type flip flop 8 rising edge arrives, Q holds output low level, and keep always, PA becomes low level by high level when the d type flip flop reset signal, after the end that namely resets, when first rising edge of the clock signal input pin of d type flip flop 8 arrives, Q end output becomes high level by low level, and before the next rising edge that remains to the reset signal PA of d type flip flop 8 arrives.The Q end of d type flip flop 8 is output as the PWM ripple of frequency 2kHz, and its duty ratio depends on the input clock signal of d type flip flop 8.The PWM ripple of the Q of d type flip flop 8 end output by way of compensation waveform after resistor 9 and capacitor 11 low-pass filtering, be converted to the direct voltage amount, this voltage is converted to offset current by compensating resistor 10 and accesses feedback reference current source 12, and feedback reference current source 12 is compensated.
Fig. 3 is that duty ratio is 63/128 compensation oscillogram, production process of this compensation waveform is: the 64 address signal B0 that selects a data selector 7～B5 gatings the D32 signal as output, the D32 signal is produced with door AND32 by the 32nd six input in 64 group of six input gate array 4, six inputs meet respectively Q5, VCC, VCC, VCC, VCC, VCC with six inputs of door AND32, and six inputs are the Q5 signal with the output of door AND32.Therefore, the Q5 signal is the input clock signal of d type flip flop 8, and it has determined the duty ratio of the compensation waveform that the Q end of d type flip flop 8 is exported.
Claims (1)
1. the circuit that the voltage/frequency change-over circuit is carried out the compensation of digital linear degree is characterized in that: comprise six binary counting/frequency dividers (1), six inputs and door (2), two inputs and door (3); The output of six binary counting/frequency dividers (1) respectively with six inputs and door (2) with are connected 14 group six input gate array (4) and be connected; The output and 64 of 64 group of six input gate array (4) selects a data selector (7) to be connected; The output of six inputs and door (2) respectively with two inputs and (3) with are connected a latch (6) and are connected; Two inputs are connected 8 with six binary counting/frequency dividers (5) with d type flip flop respectively with the output of door (3)) be connected; The output of six binary counting/frequency dividers (5) is connected with six latchs (6); The output and 64 of six latchs (6) selects a data selector (7) to be connected; 64 select the output of a data selector (7) to be connected with d type flip flop (8); The output of d type flip flop (8) is connected with resistor (9); The output of resistor (9) is connected 11 with resistor (10) with capacitor respectively) be connected; The output of resistor (10) is connected with feedback reference current source (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304044 CN202841103U (en) | 2012-06-26 | 2012-06-26 | Circuit for carrying out digital linearity compensation on voltage/frequency conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220304044 CN202841103U (en) | 2012-06-26 | 2012-06-26 | Circuit for carrying out digital linearity compensation on voltage/frequency conversion circuit |
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| CN202841103U true CN202841103U (en) | 2013-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220304044 Expired - Lifetime CN202841103U (en) | 2012-06-26 | 2012-06-26 | Circuit for carrying out digital linearity compensation on voltage/frequency conversion circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105571590A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | Fusion compensation method |
-
2012
- 2012-06-26 CN CN 201220304044 patent/CN202841103U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105571590A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | Fusion compensation method |
| CN105571590B (en) * | 2014-10-13 | 2018-07-20 | 北京自动化控制设备研究所 | A kind of fusion compensation method |
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Granted publication date: 20130327 |
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