CN203658459U - Metering circuit based on SWF2L23A type chip - Google Patents
Metering circuit based on SWF2L23A type chip Download PDFInfo
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- CN203658459U CN203658459U CN201320687039.6U CN201320687039U CN203658459U CN 203658459 U CN203658459 U CN 203658459U CN 201320687039 U CN201320687039 U CN 201320687039U CN 203658459 U CN203658459 U CN 203658459U
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- 238000005070 sampling Methods 0.000 claims abstract description 36
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 38
- 230000007935 neutral effect Effects 0.000 claims description 14
- 230000005540 biological transmission Effects 0.000 claims description 13
- 238000004891 communication Methods 0.000 abstract description 4
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- 238000005516 engineering process Methods 0.000 description 2
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Abstract
The utility model discloses a metering circuit based on a SWF2L23A type chip. The circuit comprises a metering chip SWF2L23A and a peripheral circuit thereof, a firing line current sampling circuit, a zero line current sampling circuit, a voltage sampling circuit, a metering pulse output circuit, and a SPI communication circuit. The firing line current sampling circuit, the zero line current sampling circuit, and the voltage sampling circuit input respective sampling signals to the metering chip SWF2L23A. A pulse output end of the metering chip SWF2L23A is connected with the metering pulse output circuit. The metering chip SWF2L23A is connected with a corresponding SPI interface of a master control unit of a metering device through the SPI communication circuit. The circuit performs RC filtering processing on the sampling signals through anti-interference capability of the sampling circuits, so that the sampling signals are matched with the internal design of the metering chip SWF2L23A in an optimal manner. The circuit is designed to input firing line current sampling signals in a differential input method, and zero line current sampling signals and voltage sampling signals are input by pseudo differential processing. The SPI communication circuit uses a signal level converting circuit, providing convenience for design of MCU chips in different levels.
Description
Technical field
The utility model relates to electronic circuit technology field, is specifically related to the metering circuit that a kind of intelligent electric meter is used.
Background technology
Along with power industry intelligent electric energy meter updates in enormous quantities, intelligent electric energy meter is also more and more higher to the accuracy of metering, measures the inaccurate electric power dispute that usually can produce if existed, and loses great.Here the most direct factor is exactly whether performance and the work of the computation chip above intelligent electric energy meter is stable, so the relevant design of computation chip is just particularly important.
SWF2L23A cake core is the electric energy computation chip of Zhuhai Zhonghui Microelectronics Co., Ltd.'s a high-accuracy wide-range of openly producing, and its distinctive ADC has guaranteed that chip also can maintaining a long-term stability property in the time that electrical network condition and external environment condition change.
Shown in Fig. 1, SWF2L23A cake core has 24 pins, adopts green SSOP24 encapsulation.SWF2L23A cake core is supported multiple-working mode: normal mode of operation/frequency reducing quantitative model/current effective value quantitative model/constant quantitative model/park mode, support SPI interface.
As from the foregoing, cake core provides basic condition for the realization of metering circuit, now also need to develop a kind of special measuring circuit matching based on cake core.
Utility model content
The purpose of this utility model be to provide a kind of based in the metering circuit of intelligent SWF2L23A computation chip, guarantee the stability of the anti-interference and computation chip of sampled signal.The purpose of this utility model is realized by following technical scheme:
Based on a metering circuit for SWF2L23A cake core, comprise computation chip SWF2L23A and peripheral circuit thereof, live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit, metrical pulse output circuit and SPI telecommunication circuit; Live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit input to computation chip SWF2L23A by sampled signal separately respectively; The pulse output end of computation chip SWF2L23A connects metrical pulse output circuit; Computation chip SWF2L23A connects the corresponding SPI interface of the main control unit of metering outfit by SPI telecommunication circuit.
In the utility model, sample circuit has done very strong antijamming capability, sampled signal is carried out to RC filtering processing, and optimum matching is carried out in the indoor design of SWF2L23A computation chip; Can adopt difference In-put design to live wire current sampling signal, neutral line current sampled signal and voltage sampling signal are adopted to pseudo-differential processing; Can adopt signal level shift circuit to SPI telecommunication circuit, facilitate the MCU chip design of varying level; Comprised impulse output circuit, optional be furnished with the output of merit and reactive energy simultaneously.
Accompanying drawing explanation
The formation block diagram of the metering circuit based on SWF2L23A cake core that Fig. 1 provides for embodiment.
The schematic diagram of computation chip and peripheral circuit thereof in the metering circuit based on SWF2L23A cake core that Fig. 2 provides for embodiment.
The schematic diagram of the metering circuit moderate heat line current sample circuit based on SWF2L23A cake core that Fig. 3 provides for embodiment.
The schematic diagram of neutral line current sample circuit in the metering circuit based on SWF2L23A cake core that Fig. 4 provides for embodiment.
The schematic diagram of voltage sampling circuit in the metering circuit based on SWF2L23A cake core that Fig. 5 provides for embodiment.
In the metering circuit based on SWF2L23A cake core that Fig. 6 provides for embodiment, measure the schematic diagram of pulsing circuit.
The schematic diagram of SPI telecommunication circuit in the metering circuit based on SWF2L23A cake core that Fig. 7 provides for embodiment.
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Embodiment
As shown in Figure 1, the metering circuit based on SWF2L23A cake core that the present embodiment provides, comprises computation chip SWF2L23A and peripheral circuit thereof, live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit, metrical pulse output circuit and SPI telecommunication circuit.Wherein, live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit are sampled to live wire electric current, neutral line current and voltage respectively, and sampled signal is separately inputed to computation chip SWF2L23A; The pulse output end of computation chip SWF2L23A connects metrical pulse output circuit; The SPI interface of computation chip SWF2L23A connects the corresponding SPI interface of main control unit by telecommunication circuit.Magnitude of voltage, current value and the reverse electric weight that computation chip SWF2L23A obtains is by SPI interface input main control unit, and main control unit can be electric weight by the pulses switch of computation chip output.
As shown in Figure 2,1-24 the pin of computation chip SWF2L23A is defined as respectively: AVDD, AVSS, REF, UP, UN, IBN, IBP, IAN, IAP, DFTEN, SCANEN, RSTn, SPDO, SPDI, SPCK, INT, CF1, CF2, VDD33, DVSS, DCPL, SPCSN, CTI, CTO.The peripheral circuit of computation chip SWF2L23A mainly comprises feed circuit, crystal oscillating circuit and the grounding circuit of chip operation necessity.
As shown in Figure 3, live wire current sampling circuit adopts difference processing In-put design to live wire current sampling signal, specifically by resistance R 214, resistance R 234, resistance R 217, resistance R 218, capacitor C 209, capacitor C 210 forms, resistance R 214, resistance R 234 is attempted by between sampled point 1 and sampled point 2, resistance R 217 is connected between the 7th pin IBP of sampled point 2 and computation chip SWF2L23A, resistance R 218 is connected between the 6th pin IBN of sampled point 1 and computation chip SWF2L23A, capacitor C 209, capacitor C 210 is serially connected with between the 7th pin IBP and the 6th pin IBN of computation chip SWF2L23A, the connected node of capacitor C 209 and capacitor C 210 connects in analog, resistance R 218 connects in analog with the connected node of resistance R 234.
As shown in Figure 4, neutral line current sample circuit adopts pseudo-differential to process In-put design to neutral line current sampled signal, specifically by resistance R 237, resistance R 215, resistance R 216, capacitor C 203, capacitor C 204 forms, resistance R 237 is attempted by between sampled point Lin+ and sampled point Lin-, resistance R 215 is connected between the 9th pin IAP of sampled point Lin+ and computation chip SWF2L23A, resistance R 216 is connected between the 8th pin IAN of sampled point Lin-and computation chip SWF2L23A, capacitor C 209, capacitor C 210 is serially connected with between the 9th pin IAP and the 8th pin IAN of computation chip SWF2L23A, the connected node of capacitor C 203 and capacitor C 204 connects in analog, resistance R 237 connects in analog with the connected node of resistance R 216.
As shown in Figure 5, voltage sampling circuit adopts pseudo-differential to process In-put design to the sampled signal of voltage, is specifically made up of resistance R 201, resistance R 202, resistance R 203, resistance R 204, resistance R 205, resistance R 206, resistance R 211, resistance R 213, capacitor C 212, capacitor C 213, wherein, resistance R 201, resistance R 202, resistance R 203, resistance R 204, resistance R 205, after resistance R 206 order series connection, be connected between the 4th pin UP of sampled point ZERO and computation chip SWF2L23A, resistance R 211 connects resistance R 206 and the node of the 4th pin UP of computation chip SWF2L23A in analog, capacitor C 212, capacitor C 213 is serially connected with between the 4th pin UP and the 5th pin UN of computation chip SWF2L23A, the connected node of capacitor C 212 and capacitor C 213 connects in analog, resistance R 2213 connects the 5th pin UN of computation chip SWF2L23A and the connected node of capacitor C 213 in analog.
As shown in Figure 6, metrical pulse output circuit connects the 17th pin CF1 of computation chip SWF2L23A, comprises active energy output He Yi road, a road reactive energy output.
As shown in Figure 7, SPI telecommunication circuit comprises the transmission line that four tunnels are made up of signal level shift circuit and photoelectric isolating device respectively, wherein, first via transmission line connects the 12nd pin RSTn of computation chip SWF2L23A and the reset signal end RST of main control unit, the control that enables for main control unit to computation chip SWF2L23A; The second road transmission line connects the 15th pin SPCK of computation chip SWF2L23A and the clock signal terminal ADSCK of main control unit, is used to computation chip SWF2L23A that clock signal is provided; Third Road transmission line connects the 14th pin SPDI of computation chip SWF2L23A and the data-signal output terminals A DDTI of main control unit, transmits data for main control unit to computation chip SWF2L23A; Si road transmission line connects the 13rd pin SPDO of computation chip SWF2L23A and the data-signal input end ADDTO of main control unit, and for computation chip, SWF2L23A transmits data to main control unit.
The above-mentioned metering circuit based on SWF2L23A cake core, its sample circuit has done very strong antijamming capability design, sampled signal is carried out to RC filtering processing (carrying out optimum matching with the indoor design of SWF2L23A computation chip), live wire current sampling signal is adopted to difference In-put design, neutral line current sampled signal and voltage sampling signal are adopted to pseudo-differential processing.SPI communication port is adopted to signal level shift circuit, facilitate the MCU chip design of varying level.In addition, metrical pulse output circuit is optional is furnished with the output of merit and reactive energy.
Above embodiment fully discloses the utility model, wherein physical circuit schematic diagram should not be considered to realize unique example of the present utility model, based on the utility model practical matter, based on the present embodiment without creative work be attainable other concrete examples should belong to the application disclose scope.
Claims (7)
1. the metering circuit based on SWF2L23A cake core, is characterized in that: comprise computation chip SWF2L23A and peripheral circuit thereof, live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit, metrical pulse output circuit and SPI telecommunication circuit; Live wire current sampling circuit, neutral line current sample circuit, voltage sampling circuit input to computation chip SWF2L23A by sampled signal separately respectively; The pulse output end of computation chip SWF2L23A connects metrical pulse output circuit; Computation chip SWF2L23A connects the corresponding SPI interface of the main control unit of metering outfit by SPI telecommunication circuit.
2. the metering circuit based on SWF2L23A cake core according to claim 1, it is characterized in that: described live wire current sampling circuit adopts difference processing In-put design to live wire current sampling signal, specifically by resistance R 214, resistance R 234, resistance R 217, resistance R 218, capacitor C 209, capacitor C 210 forms, resistance R 214, resistance R 234 is attempted by between sampled point 1 and sampled point 2, resistance R 217 is connected between the 7th pin IBP of sampled point 2 and computation chip SWF2L23A, resistance R 218 is connected between the 6th pin IBN of sampled point 1 and computation chip SWF2L23A, capacitor C 209, capacitor C 210 is serially connected with between the 7th pin IBP and the 6th pin IBN of computation chip SWF2L23A, the connected node of capacitor C 209 and capacitor C 210 connects in analog, resistance R 218 connects in analog with the connected node of resistance R 234.
3. the metering circuit based on SWF2L23A cake core according to claim 1, it is characterized in that: described neutral line current sample circuit adopts pseudo-differential to process In-put design to neutral line current sampled signal, specifically by resistance R 237, resistance R 215, resistance R 216, capacitor C 203, capacitor C 204 forms, resistance R 237 is attempted by between sampled point Lin+ and sampled point Lin-, resistance R 215 is connected between the 9th pin IAP of sampled point Lin+ and computation chip SWF2L23A, resistance R 216 is connected between the 8th pin IAN of sampled point Lin-and computation chip SWF2L23A, capacitor C 209, capacitor C 210 is serially connected with between the 9th pin IAP and the 8th pin IAN of computation chip SWF2L23A, the connected node of capacitor C 203 and capacitor C 204 connects in analog, resistance R 237 connects in analog with the connected node of resistance R 216.
4. the metering circuit based on SWF2L23A cake core according to claim 1, it is characterized in that: described voltage sampling circuit adopts pseudo-differential to process In-put design to the sampled signal of voltage, is specifically made up of resistance R 201, resistance R 202, resistance R 203, resistance R 204, resistance R 205, resistance R 206, resistance R 211, resistance R 213, capacitor C 212, capacitor C 213, resistance R 201, resistance R 202, resistance R 203, resistance R 204, resistance R 205, after resistance R 206 order series connection, be connected between the 4th pin UP of sampled point ZERO and computation chip SWF2L23A, resistance R 211 connects resistance R 206 and the node of the 4th pin UP of computation chip SWF2L23A in analog, capacitor C 212, capacitor C 213 is serially connected with between the 4th pin UP and the 5th pin UN of computation chip SWF2L23A, the connected node of capacitor C 212 and capacitor C 213 connects in analog, resistance R 2213 connects the 5th pin UN of computation chip SWF2L23A and the connected node of capacitor C 213 in analog.
5. the metering circuit based on SWF2L23A cake core according to claim 1, it is characterized in that: described metrical pulse output circuit connects the 17th pin CF1 of computation chip SWF2L23A, comprise active energy output He Yi road, a road reactive energy output.
6. the metering circuit based on SWF2L23A cake core according to claim 1, it is characterized in that: described SPI telecommunication circuit comprises the transmission line that four tunnels are made up of signal level shift circuit and photoelectric isolating device respectively, four road transmission lines are respectively used to: the enable control of main control unit to computation chip SWF2L23A; Main control unit provides clock signal for computation chip SWF2L23A; Main control unit is to computation chip SWF2L23A transmission data; Computation chip SWF2L23A transmits data to main control unit.
7. the metering circuit based on SWF2L23A cake core according to claim 6, is characterized in that: in described four road transmission lines, first via transmission line connects the 12nd pin RSTn of computation chip SWF2L23A and the reset signal end RST of main control unit; The second road transmission line connects the 15th pin SPCK of computation chip SWF2L23A and the clock signal terminal ADSCK of main control unit; Third Road transmission line connects the 14th pin SPDI of computation chip SWF2L23A and the data-signal output terminals A DDTI of main control unit; Si road transmission line connects the 13rd pin SPDO of computation chip SWF2L23A and the data-signal input end ADDTO of main control unit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320687039.6U CN203658459U (en) | 2013-10-31 | 2013-10-31 | Metering circuit based on SWF2L23A type chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320687039.6U CN203658459U (en) | 2013-10-31 | 2013-10-31 | Metering circuit based on SWF2L23A type chip |
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| CN203658459U true CN203658459U (en) | 2014-06-18 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914301A (en) * | 2015-06-26 | 2015-09-16 | 张新安 | Digital power meter |
| CN110161308A (en) * | 2019-05-22 | 2019-08-23 | 重庆国翰能源发展有限公司 | A kind of electric energy metering device for alternating-current charging pile |
| CN111413541A (en) * | 2020-04-22 | 2020-07-14 | 上海国泉科技有限公司 | Metering circuit of ammeter and ammeter |
| CN114301134A (en) * | 2021-12-29 | 2022-04-08 | 广州南方电力集团科技发展有限公司 | Back-up power on-off control circuit |
| CN116106623A (en) * | 2023-04-12 | 2023-05-12 | 浙江恒业电子股份有限公司 | Dual-power calculation single-phase electric energy meter and method for non-isolated sampling alternating current |
-
2013
- 2013-10-31 CN CN201320687039.6U patent/CN203658459U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104914301A (en) * | 2015-06-26 | 2015-09-16 | 张新安 | Digital power meter |
| CN110161308A (en) * | 2019-05-22 | 2019-08-23 | 重庆国翰能源发展有限公司 | A kind of electric energy metering device for alternating-current charging pile |
| CN111413541A (en) * | 2020-04-22 | 2020-07-14 | 上海国泉科技有限公司 | Metering circuit of ammeter and ammeter |
| CN114301134A (en) * | 2021-12-29 | 2022-04-08 | 广州南方电力集团科技发展有限公司 | Back-up power on-off control circuit |
| CN114301134B (en) * | 2021-12-29 | 2024-05-24 | 广州南方电力集团科技发展有限公司 | On-off control circuit of backup power supply |
| CN116106623A (en) * | 2023-04-12 | 2023-05-12 | 浙江恒业电子股份有限公司 | Dual-power calculation single-phase electric energy meter and method for non-isolated sampling alternating current |
| CN116106623B (en) * | 2023-04-12 | 2023-08-29 | 浙江恒业电子股份有限公司 | Dual-power calculation single-phase electric energy meter and method for non-isolated sampling alternating current |
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Granted publication date: 20140618 |