CN202841063U - D-class power amplifier chip - Google Patents
D-class power amplifier chip Download PDFInfo
- Publication number
- CN202841063U CN202841063U CN201220491672.3U CN201220491672U CN202841063U CN 202841063 U CN202841063 U CN 202841063U CN 201220491672 U CN201220491672 U CN 201220491672U CN 202841063 U CN202841063 U CN 202841063U
- Authority
- CN
- China
- Prior art keywords
- power amplifier
- output
- over
- module
- class power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The utility model discloses a D-class power amplifier chip in the field of integrated circuits. The D-class power amplifier chip comprises a pulse-width modulation (PWM) module, a first output drive, a second output drive, a load and an over-current protection circuit. A first power amplifier pipe is arranged at an output end of the first output drive. A second power amplifier pipe is arranged at an output end of the second output drive. A filtering device is arranged on the over-current protection circuit. A voltage difference between two input ends of the PWM module can be adjusted in the range from 0 to the full power amplitude voltage difference. When the voltage different between two input ends of the PWM module is the full power amplitude voltage difference, the PWM module continuously outputs a first full amplitude PWM signal and a second full amplitude PWM signal, wherein the first full amplitude PWM signal and the second full amplitude PWM signal are anti-phase. The D-class power amplifier chip has the advantages of being capable of solving the problem that the filtering device on the over-current protection circuit accidentally performs pulse width filtering on an over-current signal as high potential pulse width of the over-current signal is too low.
Description
Technical field
The utility model relates to a kind of D class power amplifier chips of integrated circuit fields.
Background technology
See also Fig. 1, present D class power amplifier chips comprises: amplification module 11, PWM modulation module 12, the first output drive the 13, second output driving 14, load 17 and current foldback circuit 2.The P output of described PWM modulation module 12 connects described the first output and drives 13, and the N output of described PWM modulation module 12 connects described the second output and drives 14.The output of described the first output driving 13 is provided with the first power tube 15, and the output of described the second output driving 14 is provided with the second power tube 16, and described load 17 connects described the first power tube 15 and described the second power tubes 16.Input described amplification module 11 audio input signal waveform as shown in Figure 2, after this audio input signal amplifies through described amplification module 11, input described PWM modulation module 12 and modulate, described PWM modulation module 12 output the first pwm signal and the second pwm signals.Described the first pwm signal and described the second pwm signal are mutually anti-phase.Described the first pwm signal is after the driving through described the first output driving 13, P end to described load 17 loads, described the second pwm signal is after the driving through described the second output driving 14, N end to described load 17 loads, described load forms voltage difference between 17 two ends, described load 17 output pulse signals.The waveform of described pulse signal as shown in Figure 3.Vpower represents that described pulse signal is in high potential among Fig. 3, and-Vpower represents that described pulse signal is in negative potential.When described pulse signal is high potential or negative potential, there is electric current to flow through in the described load 17.
Carry out signal feedback in order to make described the first output drive 13 pairs of described PWM modulation modules 12, described the first power tube 15 takes back the P input of described PWM modulation module 12 through the first tieback resistance 18.Carry out signal feedback in order to make described the second output drive 14 pairs of described PWM modulation modules 12, described the second power tube 16 takes back the N input of described PWM modulation module 12 through the second tieback resistance 19.The resistance of described the first tieback resistance 18 and described the second tieback resistance 19 equates.Such circuit design easily makes described the first power tube 15 and described the second power tube 16 short circuit occur, thereby cause large electric current, short circuit current flows through described the first power tube 15 and described the second power tube 16 in other words conj.or perhaps, and chip damages, and this moment is very little by the electric current in the described load 17.Because be directly proportional with the electric current that described load 17 is flow through from the high potential level of the pulse signal of described load 17 outputs, therefore the high potential level of this pulse signal is very low at this moment, is lower than overcurrent threshold value b.The current foldback circuit 2 in parallel with described load 17 can be set on the D class power amplifier chips for this reason, be used for monitoring the electric current in the described load 17.Described overcurrent threshold value b is by default.
Described current foldback circuit 2 comprises: the first over-current detection module 21 that is connected with the P end of described load 17, the second over-current detection module 22 and the Logic control module 23 between described the first over-current detection module 21 and described the second over-current detection module 22 that are connected with the N end of described load 17; when the high potential level of the pulse signal of described load 17 outputs is lower than overcurrent threshold value b; produce OC+ over-current signal (positive over-current signal) on described the first over-current detection module 21, described the second over-current detection module 22 produces OC-over-current signal (negative over-current signal).Described Logic control module 23 receives described OC+ over-current signal and described OC-over-current signal and carries out the signal conversion, described the first output driving 13 is turn-offed in output and described the second output drives 14 cut-off signals, and described PWM modulation module 12 keeps normal operating conditions.Described D class power amplifier chips enters the overcurrent protection state.
After described the first output driving 13 and described the second output driving 14 reopen, if D class power amplifier chips is operated near the dc point, the power supply amplitude of audio input signal of inputting described PWM modulation mould 12 is very low, cause the high potential pulsewidth of described first pwm signal of PWM modulation module 12 output and described the second pwm signal very low, the high potential pulsewidth of the pulse signal of described load 17 outputs is very low, cause the high potential pulsewidth of described OC+ over-current signal and described OC-over-current signal very low, namely be lower than filter threshold a, as shown in Figure 4.A is by default for this filter threshold.Therefore, described OC+ over-current signal and described OC-over-current signal can be filtered away by the described filter pulsewidth of crossing on the current circuit 2, these filters both can be built in described the first over-current detection module 21 and described the second over-current detection module 22 simultaneously, also can only be built in described Logic control module 23.Therefore described Logic control module 23 can't turn-off described the first output driving 13 and described the second output driving 14, described the first power tube 15 and described the second power tube 16 can be because can't turn-off the repeated stock that suffers large electric current, thereby affect the useful life of chip, even directly chip is burnt out.
The utility model content
The purpose of this utility model is in order to overcome the deficiencies in the prior art, a kind of D class power amplifier chips is provided, it can solve because the high potential pulsewidth of over-current signal is excessively low, cause over-current signal by the filtering of mistake pulsewidth, cause the output of first on D class power amplifier chips driving and the second output to drive the technical problem that to turn-off.
A kind of technical scheme that realizes above-mentioned purpose is: a kind of D class power amplifier chips comprises that PWM modulation module, the first output drive, the second output driving, load and current foldback circuit; The output that the output that described the first output drives arranges the first power tube, described the second output driving arranges the second power tube, and described current foldback circuit is provided with at least one filter;
Voltage difference between two inputs of described PWM modulation module can regulated between the rail to rail voltage difference, when the voltage difference between two inputs of described PWM modulation module is the rail to rail voltage difference, described PWM modulation module receives external audio input signal, continues the first mutual anti-phase full width of cloth pwm signal of output and the second full width of cloth pwm signal.
Further, two inputs of described PWM modulation module respectively side connect a switch, the other switch that connects of one of them input is mains switch, the other switch that connects of another input is earthed switch, described mains switch and described earthed switch are opened simultaneously, and the voltage difference between two inputs of described PWM modulation module is the rail to rail voltage difference.
Further, the resistance of similar resistance is set respectively on two inputs of described PWM modulation module, two described switches are connected on the input of two described resistance correspondingly.
Further, described current circuit is in parallel with described load excessively, and described current foldback circuit comprises the first over-current detection module, Logic control module and the second over-current detection module of successively series connection.
Further, built-in the first filter of described the first over-current detection module and described the second over-current detection module difference.
Further, built-in the second filter of described Logic control module.
Further, described mains switch be connected earthed switch and be connected with described Logic control module respectively, between wherein said Logic control module and the described mains switch reverser is set.
Further, described Logic control module drives with being connected to export to drive with the first output and is connected respectively.
Adopted the technical scheme of a kind of D class power amplifier chips of the present utility model, namely the voltage difference between two inputs of the PWM modulation module on the D class power amplifier chips can be 0 to the technical scheme of regulating between the rail to rail voltage difference.Its technique effect is: it can protect the high potential pulsewidth of over-current signal; make over-current signal not by the filtering of the mistake of the filter on current foldback circuit pulsewidth; the summary responses of Logic control module to large electric current have been guaranteed; described the first output driving is closed in shutoff and described the second output drives; protect the first power tube and the second power tube not to be subjected to the impact of large electric current, thereby guaranteed the safe operation of D class power amplifier chips.
Description of drawings
Fig. 1 is the circuit diagram of the D class power amplifier chips of prior art.
Fig. 2 is the oscillogram of the audio input signal of input PWM modulation module.
Fig. 3 is the oscillogram of the pulse signal of load output.
Fig. 4 is the oscillogram of over-current signal.
Fig. 5 is the circuit diagram of a kind of D class power amplifier chips of the present utility model.
Embodiment
See also Fig. 5, inventor of the present utility model be in order to understand the technical solution of the utility model better, below by embodiment particularly, and is described in detail by reference to the accompanying drawings:
What Fig. 5 showed is the circuit diagram of a kind of D class of the utility model power amplifier chips, and this D class power amplifier chips comprises that amplification module 11, PMW modulation module 12, the first output drive the 13, second output driving 14, load 17 and current foldback circuit 2.The output of described the first output driving 13 arranges the first power tube 15, and the output of described the second output driving 14 arranges the second power tube 16, and described the first power tube 15 and described the second power tube 16 are all formed by two output switch pipes serial connections.
The P output of described amplification module 11 be connected PMW modulation module 12 first resistance 110 of P input by successively series connection be connected resistance 111 and connect, the N output of described amplification module 11 be connected three resistance 112 and four resistance 113 of N input by successively series connection of PMW modulation module 12 and connect, the resistance of described the first resistance 110 and described the 3rd resistance 112 is equal, and the resistance of described the second resistance 111 and described the 4th resistance 113 equates.
Described the first output drives the P output of the described PMW modulation module 12 of 13 connections, and described the second output driving 14 connects the N output of described PMW modulation module 12.The P end of described load 17 connects described the first power tube 15, and the N end of described load 17 connects described the second power tube 16.Described the first power tube 15 takes back the P input of described PWM modulation module 12 by the first tieback resistance 18 in addition, make described the first output drive 13 and can carry out signal feedback to described PWM modulation module 12, described the second power tube 16 takes back the N input of described PWM modulation module 12 by the second tieback resistance 19, making described the second output drive 14 can carry out signal feedback to described PWM modulation module 12.
Described current foldback circuit 2 comprises the first over-current detection module 21, Logic control module 23 and the second over-current detection module 22 of successively series connection.This current foldback circuit 2 is in parallel with described load 17.Wherein said the first over-current detection module 21 connects the P end of described load 17, and described the second over-current detection module 22 connects the N end of described load 17.Section Point on the described Logic control module 23 and described the first output drive 13 be connected the second output and drive 14 and be connected respectively.Built-in the first filter of difference on described the first over-current detection module 21 and described the second over-current detection module 22, described Logic control module 22 built-in the second filters.
Described D class power amplifier chips also comprises: mains switch 24 and earthed switch 25.The other input that is connected on described the second resistance 111 of one end of described mains switch 24, the power end of another termination D class power amplifier chips, the therefore described mains switch 24 other P inputs that are connected on described PWM modulation module 12, the other input that is connected on described the 4th resistance 113 of one end of described earthed switch 25, the earth terminal of another termination D class power amplifier chips, the therefore described earthed switch 25 other N inputs that are connected on described PWM modulation module 12.The purpose that described the second resistance 111 and described the 4th resistance 113 are set is in order to protect described mains switch 24, described earthed switch 25 and described PWM modulation module 12.First node on the described Logic control module 23 respectively with described earthed switch 25 be connected mains switch 24 and be connected, between wherein said Logic control module 23 and the described mains switch 24 reverser 26 is set.
The purpose of design is like this: because described mains switch 24 and described earthed switch 25 are when opening simultaneously, the N input of described PWM modulation module 12 is pulled to the earth terminal of D class power amplifier chips, and namely the voltage of the N input of described PWM modulation module 12 equals the voltage of D class power amplifier chips earth terminal.The P input of described PWM modulation module 12 is pulled to the power end of D class power amplifier chips, be the voltage that the voltage of the P input of described PWM modulation module 12 equals D class power amplifier chips power end, produce a rail to rail voltage difference between the P input of described PWM modulation module and the N input.The audio input signal that this moment, described PWM modulation module 12 received through described amplification module 11 amplifications carries out full width of cloth PMW modulation, and described PWM modulation module 12 is exported mutually anti-phase the first full width of cloth pwm signal and second expires width of cloth pwm signal.
Under the overcurrent protection state, the course of work of the current foldback circuit of described D class power amplifier chips is:
First node on the described Logic control module 23 is exported the first skip signal, opens described mains switch 24 and described earthed switch 25.Because the other mains switch 24 that is connected on the P input of described PWM modulation module 12 connects the power end of D class power amplifier chips, the earthed switch 25 that the side is connected on the N input of described PWM modulation module 12 connects the earth terminal of D class power amplifier chips, so described mains switch 24 and described earthed switch 25 are opened simultaneously, produce a rail to rail voltage difference between the P input of described PWM modulation module 12 and the N input, the P output of described PWM modulation module 12 continues output the first full width of cloth pwm signal, and the N output of described PWM modulation module 12 continues output the second full width of cloth pwm signal.The described first full width of cloth pwm signal and the described second full width of cloth pwm signal are mutually anti-phase.
After waiting for a period of time, the Section Point output start signal on the described Logic control module 23 is opened described the first output driving 13 and described the second output and is driven 14, and described the first power tube 15 and described the second power tube 16 are also opened thereupon.Described the first output drives 13 and drives the P end that the described first full width of cloth pwm signal loads described load 17, and the P end of described load 17 is pulled to the power end of described D class power amplifier chips.Described the second output drives 14 and drives the N end that the described second full width of cloth pwm signal loads described load 17, and the N end of described load 17 is pulled to the earth terminal with described D class power amplifier chips, forms the rail to rail voltage difference between the P end of described load 17 and the N end.Finally make described load 17 continue the full width of cloth pulse signal of output.
If this moment, described high potential level of expiring width of cloth pulse signal was lower than the overcurrent threshold value b of setting, the OC+ over-current signal of described the first over-current detection module 21 interior generations, and by the first filters in described the first over-current detection module 21 described OC+ over-current signal is carried out the first pulsewidth filtering, the OC-over-current signal of described the second over-current detection module 22 interior generations, and by the first filters in described the second over-current detection module 22 described OC-over-current signal is carried out the first pulsewidth filtering.And then by the second filters in the described Logic control module 23 described OC+ over-current signal and described OC-over-current signal are carried out the second pulsewidth filtering.Through twice pulsewidth filtering, no longer include the burr that the high potential pulsewidth is lower than filter threshold a in described OC+ over-current signal and the described OC-over-current signal.
Because the high potential pulsewidth of the described first full width of cloth pwm signal and the described second full width of cloth pwm signal has guaranteed the high potential pulsewidth of described full width of cloth pulse signal, the high potential pulsewidth that the high potential pulsewidth of described full width of cloth pulse signal has guaranteed described OC+ over-current signal and described OC-over-current signal is all greater than described filter threshold a, and described OC+ over-current signal and described OC-over-current signal can be by the filtering of mistake pulsewidth in the first pulsewidth filtering and the second pulsewidth filtering.Then 23 pairs of described OC+ over-current signals of described Logic control module and described OC-over-current signal carry out the signal conversion, then described the first output driving 13 of the Section Point of described Logic control module 23 output shutoff and described the second output drive 14 cut-off signals, and described the first power tube 15 and described the second power tube 16 be thereupon shutoff also.After waiting for certain hour, the Section Point of described Logic control module 23 is exported start signal again, again open the first output and drive the 13 and second output driving 14, described the first over-current detection module 21 and described the second over-current detection module 22 are carried out over-current detection again, if detecting the high potential level of described full width of cloth pulse signal, described the first over-current detection module 21 and described the second over-current detection module 22 be higher than overcurrent threshold value b, after then postponing some seconds, first node on the described Logic control module 23 is exported the second skip signal, turn-off described mains switch 24 and described earthed switch 25, this moment, whole D class power amplifier chips recovered normal operating conditions, the P output of described PWM modulation module 12 is exported the first pwm signal, the N output of described PWM modulation module 12 is exported the second pwm signal, described load 17 output pulse signals.If the high potential level that described the first over-current detection module 21 and described the second over-current detection module 22 detect described pulse signal is lower than overcurrent threshold value b, then again turn-offs described the first output driving 13 and described the second output and drive 14.Described D class power amplifier chips enters the overcurrent protection state again.
Those of ordinary skill in the art will be appreciated that, above embodiment illustrates the utility model, and be not to be used as restriction of the present utility model, as long as in connotation scope of the present utility model, all will drop in claims scope of the present utility model variation, the modification of the above embodiment.
Claims (8)
1. a D class power amplifier chips comprises that PWM modulation module (12), the first output drive (13), the second output drives (14), load (17) and current foldback circuit (2); The output that the output that described the first output drives (13) arranges the first power tube (15), described the second output driving (14) arranges the second power tube (16), and described current foldback circuit (2) is provided with at least one filter;
It is characterized in that: the voltage difference between (12) two inputs of described PWM modulation module can be regulated between the rail to rail voltage difference 0, when the voltage difference between (12) two inputs of described PWM modulation module is the rail to rail voltage difference, described PWM modulation module receives external audio input signal, continues the first mutual anti-phase full width of cloth pwm signal of output and the second full width of cloth pwm signal.
2. a kind of D class power amplifier chips according to claim 1, it is characterized in that: (12) two inputs of described PWM modulation module respectively side connect a switch, the other switch that connects of one of them input is mains switch (24), the other switch that connects of another input is earthed switch (25), described mains switch (24) and described earthed switch (25) are opened simultaneously, and the voltage difference between (12) two inputs of described PWM modulation module is the rail to rail voltage difference.
3. a kind of D class power amplifier chips according to claim 2 is characterized in that: the resistance of similar resistance is set respectively on two inputs of described PWM modulation module (12), and two described switches are the other input that is connected on two described resistance correspondingly.
4. a kind of D class power amplifier chips according to claim 2; it is characterized in that: described excessively current circuit (2) is in parallel with described load (17), and described current foldback circuit (2) comprises the first over-current detection module (21), Logic control module (23) and the second over-current detection module (22) of successively series connection.
5. a kind of D class power amplifier chips according to claim 4 is characterized in that: described the first over-current detection module (21) and built-in the first filter of described the second over-current detection module (22) difference.
6. it is characterized in that: built-in the second filter of described Logic control module (23) according to claim 4 or 5 described a kind of D class power amplifier chips.
7. described a kind of D class power amplifier chips according to claim 4, it is characterized in that: described mains switch (24) be connected earthed switch (25) and be connected with described Logic control module (23) respectively, between wherein said Logic control module (23) and the described mains switch (24) reverser (26) is set.
8. a kind of D class power amplifier chips according to claim 4 is characterized in that: described Logic control module (23) and the first output drive (13) and are connected output driving (14) and is connected respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220491672.3U CN202841063U (en) | 2012-09-25 | 2012-09-25 | D-class power amplifier chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220491672.3U CN202841063U (en) | 2012-09-25 | 2012-09-25 | D-class power amplifier chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202841063U true CN202841063U (en) | 2013-03-27 |
Family
ID=47952659
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220491672.3U Expired - Lifetime CN202841063U (en) | 2012-09-25 | 2012-09-25 | D-class power amplifier chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202841063U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102843109A (en) * | 2012-09-25 | 2012-12-26 | 上海贝岭股份有限公司 | Class D power amplifier chip |
-
2012
- 2012-09-25 CN CN201220491672.3U patent/CN202841063U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102843109A (en) * | 2012-09-25 | 2012-12-26 | 上海贝岭股份有限公司 | Class D power amplifier chip |
| CN102843109B (en) * | 2012-09-25 | 2016-01-20 | 上海贝岭股份有限公司 | A kind of category D amplifier chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102843109B (en) | A kind of category D amplifier chip | |
| CN102682721B (en) | Light emitting diode (LED) backlight system and display device | |
| CN100530948C (en) | Digital amplifier | |
| CN101127509A (en) | Timer reset circuit for overcurrent protection of switching power amplifier | |
| CN103188851B (en) | Constant current driver circuit for LED | |
| CN102013802B (en) | BOOST circuit with short circuit protection function | |
| CN102957383A (en) | Class d amplifier and control method | |
| CN101567668A (en) | Voltage detection type overcurrent protection device applied to D-class amplifier | |
| CN102707179B (en) | A kind of fault detection device for inverter | |
| CN202841063U (en) | D-class power amplifier chip | |
| CN203423482U (en) | Power tube protection circuit and switch power supply circuit using the circuit | |
| CN104242611A (en) | Half-bridge IGBT driving module | |
| CN202918187U (en) | High power switch power supply possessing soft start and fault protection | |
| CN104331340A (en) | Watchdog circuit | |
| CN203014679U (en) | Improved fault safe DC-DC power supply equipment | |
| CN104753475B (en) | X class A amplifier As | |
| CN103187710A (en) | Current-limit and over-current double current loop protection circuit | |
| CN102594144A (en) | Current control type direct current voltage reduction circuit and power consumption reduction method thereof | |
| CN203588539U (en) | Teaching experiment facility for sinusoidal pulse width modulation (SPWM) single-phase inverter | |
| CN102843106B (en) | A kind of over-current protection method for category D amplifier chip | |
| CN209030117U (en) | A kind of single-phase Sinusoidal Inverter system adjusted based on feed forward approach | |
| CN203027246U (en) | Electrical level conversion circuit and pulse output circuit | |
| CN104836192A (en) | Input short-circuit protecting circuit for PWM (Pulse-Width Modulation) type audio power amplifier | |
| CN203645295U (en) | Device and system for switch value output protection | |
| CN204290936U (en) | Single channel turns two-way drive circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130327 |