CN202795017U - Serial communication distribution device based on FPGA (field programmable gate array) - Google Patents
Serial communication distribution device based on FPGA (field programmable gate array) Download PDFInfo
- Publication number
- CN202795017U CN202795017U CN2012204771777U CN201220477177U CN202795017U CN 202795017 U CN202795017 U CN 202795017U CN 2012204771777 U CN2012204771777 U CN 2012204771777U CN 201220477177 U CN201220477177 U CN 201220477177U CN 202795017 U CN202795017 U CN 202795017U
- Authority
- CN
- China
- Prior art keywords
- serial communication
- fpga
- data
- port com
- data buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Information Transfer Systems (AREA)
Abstract
The utility model discloses a serial communication distribution device based on an FPGA (field programmable gate array). The serial communication distribution device comprises an FPGA chip, and is characterized in that pins of the FPGA chip are a plurality of communication ports which can be connected with an upper computer and a plurality of control devices, baud rate generators, received data buffer areas, status registers, transmitted data buffer areas, control registers, receiving controllers and transmitting controllers are arranged in the FPGA chip, the number of the baud rate generators, the number of the received data buffer areas, the number of the status registers, the number of the transmitted data buffer areas, the number of the control registers, the number of the receiving controllers and the number of the transmitting controllers are respectively equal to that of the communication ports, the baud rate generators transmit and receive data at different rates, each status register comprises a receiving interrupt identification bit RI and transmitting interrupt identification bit TI, and multi-way analog switches for communicating different communication ports are further arranged in the FPGA chip. The communication distribution device realizes mutual communication of the upper computer and the control devices, and the data can be transmitted and received at different rates. The whole device is simple, practical, reliable, stable, low in cost, easy to implement and suitable for serial communication of various places and a plurality of nodes.
Description
Technical field
The utility model relates to a kind of serial communication distributor based on FPGA, in particular, relates in particular to a kind of serial communication distributor based on FPGA that a plurality of nodes are controlled simultaneously.
Background technology
Along with the development of the communication technology, the application of serial communication aspect Industry Control and real-time Communication for Power is very extensive; Especially for the control of point-to-points node of a master control, use very universal.The serial distributor major part that adopts at present all is to have integrated circuit to consist of, generally consisted of by microcontroller and peripheral processing module, and this form of the composition, the component number of employing is many, has the shortcoming that cost is high, volume is large, energy consumption is high.
Fpga chip had both solved the deficiency of custom circuit as a kind of semi-custom circuit, had overcome again the limited shortcoming of original programming device gate circuit number, was conducive to improve level of integrated system, reliability.
Summary of the invention
The utility model provides a kind of serial communication distributor based on FPGA that a plurality of nodes are controlled simultaneously in order to overcome the shortcoming of above-mentioned technical matters.
Serial communication distributor based on FPGA of the present utility model, the serial communication distributor is made of fpga chip, its special feature is: the pin of described fpga chip is set to a plurality of PORT COM that can be connected with host computer, opertaing device, be provided with the Baud rate generator, reception data buffer, status register, transmission data buffer, control register, reception controller and the transmit control device that all equate with the PORT COM number in the fpga chip, Baud rate generator is realized the transmitting-receiving of data under the different rates; Receive controller and be used for taking out the interior data of reception data buffer, the data that transmit control device is used for will sending in the data buffer are sent, and comprise receive interruption zone bit RI in the status register, send interrupt flag bit TI; Also be provided with the multiway analog switch that different PORT COM is communicated with in the fpga chip.
Adopt on-site programmable gate array FPGA can realize the hardware setting of serial communication distributor, make the pin of fpga chip form a plurality of PORT COM, so as with host computer and a plurality of opertaing device connecting communication.For reception and the forwarding capability of realizing data, one group of Baud rate generator, reception data buffer, status register, transmission data buffer, control register, reception controller and transmit control device are used for the digital received and sent of a PORT COM of management.Multiway analog switch is realized the connection between the different PORT COM.
Serial communication distributor based on FPGA of the present utility model, described PORT COM adopts the RS232 serial communication.RS232 is serial communication form comparatively commonly used.
Serial communication distributor based on FPGA of the present utility model, described PORT COM is connected with RS485 or RS422 communication module by level translator.If need to adopt RS485 or RS422 communication, needing increases level translator, in order to be converted into RS485 or RS422 level.
The beneficial effects of the utility model are: (1) serial communication distributor based on FPGA of the present utility model, form the serial communication distributor by adopting fpga chip to make, and each PORT COM all disposes data transmit-receive buffer zone separately, transceiver controller, state and control register, Baud rate generator and the multiway analog switch of connecting different PORT COM, effectively realized the mutual communication between host computer and a plurality of opertaing device, so that whole communication distributor has a circuit structure is succinct, rationally distributed, the advantage that the PORT COM data transmit-receive is stable.(2) because each PORT COM has oneself independently Baud rate generator, can effectively realize the transmitting-receiving of data under the different rates.(3) communication means of the serial communication distributor based on FPGA of the present utility model, state by detecting interrupt flag bit TI and RI, digital received and sent buffer zone have been realized the communication between host computer and the opertaing device effectively to temporary, the control of transceiver controller to receiving and sending of data.
Simultaneously, serial communication distributor of the present utility model and method also have the advantage simple, practical and reliable, stable, that traffic rate is high; Can the data that reach tens nodes be sent simultaneously.Traffic rate reaches as high as 115200 bit/s.
Description of drawings
Fig. 1, Fig. 2 are the inner structure schematic diagram of serial communication distributor of the present utility model;
Fig. 3 is the principle schematic that host computer utilizes serial communication distributor of the present utility model, level translator to be connected with opertaing device;
Fig. 4 is the principle schematic that host computer utilizes serial communication distributor of the present utility model directly to be connected with opertaing device.
Fig. 5 is the program flow diagram that host computer on the COMa port and the opertaing device on the COMb port communicate.
Among the figure: 1 Baud rate generator, 2 reception data buffers, 3 status registers, 4 send the data buffer, 5 control registers, 6 receive controller, 7 transmit control devices, 8 multiway analog switches, 9 level translators, 10 RS485 or RS422 communication module, 11 host computers, 12 opertaing devices, 13 PORT COM.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing and embodiment.
As shown in Figure 1 and Figure 2, provided the inner structure schematic diagram of serial communication distributor of the present utility model, the pin of fpga chip is set to a plurality of PORT COM 13 that are connected with host computer 11, opertaing device 12, in order to realize the transmitting-receiving of data.The internal circuit of fpga chip is set to Baud rate generator 1, reception data buffer 2, status register 3, sends data buffer 4, control register 5, receives controller 6, transmit control device 7 and multiway analog switch 8, and each PORT COM 13 has Baud rate generator 1, reception separately and sends data buffer, state and control register, reception and transmit control device, in order to realize reception and the forwarding capability of data.Multiway analog switch 8 is used for different PORT COM 13 is connected, realize data by a port repeat to another port.
Because each PORT COM 13 has Baud rate generator 1 separately, so different PORT COM 13 can adopt different speed to carry out the transmitting-receiving of data.Receive controller 6 and take out from reception data buffer 2 for the data that will receive, the data that send in the data buffer 4 send under the effect of transmit control device 7.Be provided with receive interruption zone bit RI in the status register 3, send interrupt flag bit TI, in order to the state of digital received and sent is detected.Adopt RS232 to carry out communication such as PORT COM, then host computer 11, opertaing device 12 are connected with PORT COM and get final product; If adopt RS485 or RS422 communication, then need to increase level translator 9.
As shown in Figure 3 and Figure 4, all provided the principle schematic that host computer utilizes serial communication distributor of the present utility model to be connected with opertaing device; Have additional level translator 9 among Fig. 3, in order to realize the communication of RS485 or RS232 bus form.Among Fig. 4, the COM1 of serial communication distributor of the present utility model～COMn PORT COM 13 is connected with n opertaing device 12 respectively, and host computer 11 also is connected with the serial communication distributor by 1 PORT COM 13.
As shown in Figure 5, provided the program flow diagram that host computer on the COMa port and the opertaing device on the COMb port communicate; Connect respectively COMa, COMb PORT COM, a＜b≤n if carry out host computer (11), the opertaing device (12) of data transmit-receive; Data receiving-transmitting method may further comprise the steps:
A. accepting state is judged, whether judges the receive interruption zone bit RI of COMa PORT COM by set, as not being set to 1, then continues to detect; As be set to 1, represent that then the data receiver of host computer is finished, execution in step b;
B. the data in the data receiver buffer zone of COMa PORT COM are taken out in receive data and RI zero clearing, with the receive interruption zone bit RI zero clearing of COMa PORT COM, discharge reception buffer zone, in order to receive new data;
C. shift to send data, the data that the data that will take out in the data receiver buffer zone of COMa are deposited into COMb send buffer zone;
D. be sent to opertaing device, judge whether the COMb PORT COM that is connected with opertaing device has the request of transmission, if do not have, then continue to wait for; If request is arranged, then the data in the data transmission buffer zone of COMb are sent on the opertaing device that links to each other with the COMb port execution in step e;
E. judge whether TI puts 1, whether judge the transmission interrupt flag bit TI of COMb port by set, if be not set to 1, continue to wait for; If be set to 1, then with the transmission interrupt flag bit TI zero clearing of COMb PORT COM, in order to send new data, the COMb PORT COM sends data and finishes;
F. accepting state is judged, whether judges the receive interruption zone bit RI of COMb PORT COM by set, as not being set to 1, then continues to detect; As be set to 1, represent that then the data receiver of host computer is finished, execution in step g;
G. the data in the data receiver buffer zone of COMb PORT COM are taken out in receive data and RI zero clearing, with the receive interruption zone bit RI zero clearing of COMb PORT COM, discharge reception buffer zone, in order to receive new data;
H. shift to send data, the data that the data that will take out in the data receiver buffer zone of COMb are deposited into COMa send buffer zone;
I. be sent to opertaing device, judge whether the COMa PORT COM that is connected with opertaing device has the request of transmission, if do not have, then continue to wait for; If request is arranged, then the data in the data transmission buffer zone of COMa are sent on the opertaing device that links to each other with the COMa port execution in step j;
J. judge whether TI puts 1, whether judge the transmission interrupt flag bit TI of COMa port by set, if be not set to 1, continue to wait for; If be set to 1, then with the transmission interrupt flag bit TI zero clearing of COMa PORT COM, in order to send new data, the COMa PORT COM sends data and finishes.
The utility model carries out lane assignment after the host computer data communication device that receives can being crossed processing, realizes sending serial data to a plurality of nodes; Simultaneously, can receive the data message that a plurality of nodes return according to interrupt priority level, deposit data in reception buffer zone, and data feedback is arrived host computer, make things convenient for the staff to the policer operation of node.Whole device is simple, practical and reliable, stable, with low cost, is easy to realize, the serial communication that is fit to multiple occasion, a plurality of nodes is used.
Claims (3)
1. serial communication distributor based on FPGA, the serial communication distributor is made of fpga chip, it is characterized in that: the pin of described fpga chip be set to can with host computer (11), a plurality of PORT COM (13) that opertaing device (12) is connected, be provided with the Baud rate generator (1) that all equates with the PORT COM number in the fpga chip, reception data buffer (2), status register (3), send data buffer (4), control register (5), receive controller (6) and transmit control device (7), Baud rate generator is realized the transmitting-receiving of data under the different rates; Receive controller and be used for taking out the interior data of reception data buffer, the data that transmit control device is used for will sending in the data buffer are sent, and comprise receive interruption zone bit RI in the status register, send interrupt flag bit TI; Also be provided with the multiway analog switch (8) that different PORT COM is communicated with in the fpga chip.
2. the serial communication distributor based on FPGA according to claim 1 is characterized in that: described PORT COM (13) employing RS232 serial communication.
3. the serial communication distributor based on FPGA according to claim 1, it is characterized in that: described PORT COM (13) is connected with RS485 or RS422 communication module by level translator (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204771777U CN202795017U (en) | 2012-09-19 | 2012-09-19 | Serial communication distribution device based on FPGA (field programmable gate array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204771777U CN202795017U (en) | 2012-09-19 | 2012-09-19 | Serial communication distribution device based on FPGA (field programmable gate array) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202795017U true CN202795017U (en) | 2013-03-13 |
Family
ID=47822252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012204771777U Expired - Fee Related CN202795017U (en) | 2012-09-19 | 2012-09-19 | Serial communication distribution device based on FPGA (field programmable gate array) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202795017U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915010A (en) * | 2012-09-19 | 2013-02-06 | 山东神戎电子股份有限公司 | FPGA (field programmable gate array)-based serial communication distributing device and communication method |
| CN113419437A (en) * | 2021-06-30 | 2021-09-21 | 四川虹美智能科技有限公司 | Intelligent home data synchronization method and device based on MVVM (multifunction vehicle management model) framework and MQTT (message queuing time) protocol |
-
2012
- 2012-09-19 CN CN2012204771777U patent/CN202795017U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102915010A (en) * | 2012-09-19 | 2013-02-06 | 山东神戎电子股份有限公司 | FPGA (field programmable gate array)-based serial communication distributing device and communication method |
| CN113419437A (en) * | 2021-06-30 | 2021-09-21 | 四川虹美智能科技有限公司 | Intelligent home data synchronization method and device based on MVVM (multifunction vehicle management model) framework and MQTT (message queuing time) protocol |
| CN113419437B (en) * | 2021-06-30 | 2022-04-19 | 四川虹美智能科技有限公司 | Intelligent home data synchronization method and device based on MVVM (multifunction vehicle management model) framework and MQTT (message queuing time) protocol |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101345629B (en) | Double on-site bus interface converter | |
| CN105051706A (en) | Device, method and system for operation of a low power PHY with a PCIe protocol stack | |
| CN103714024A (en) | Multi-serial port parallel processing framework based on SoC (System on a Chip) FPGA (Field Programmable Gata Array) | |
| CN203705861U (en) | Multi-serial port parallel processing framework based on FPGA | |
| CN103440219A (en) | Novel general bus transforming bridge IP core | |
| CN102915010A (en) | FPGA (field programmable gate array)-based serial communication distributing device and communication method | |
| CN106021152A (en) | Master-slave serial device concentrator and asynchronous duplex one-to-many serial communication method | |
| CN106789496A (en) | A kind of used group 1553B communication interface circuits of optical fiber for carrier rocket | |
| CN107204992B (en) | Multifunctional serial server and data transmission method | |
| CN103713543A (en) | Multi-serial-port parallel processing framework based on FPGA | |
| CN202795017U (en) | Serial communication distribution device based on FPGA (field programmable gate array) | |
| CN106781429A (en) | Intelligent electric meter, concentrator and meter register method | |
| CN102323856A (en) | Data glove based on acceleration sensors and ZigBee | |
| CN202257468U (en) | Data gloves based on acceleration sensors and ZigBee | |
| Shrestha et al. | Wireless communication between FPGA and microcontroller | |
| CN105530157A (en) | Method for sharing credit by multiple virtual links in AFDX (Avionics Full Duplex Switched Ethernet) network switch | |
| CN205788168U (en) | Master-slave mode serial equipment hub | |
| CN202677114U (en) | Industrial control main board based on MSP430 single chip microcomputer | |
| CN107239423A (en) | A kind of device based on extension IIC interfaces | |
| CN203982366U (en) | Based on ARM and FPGA serial port device flexibly at a high speed | |
| CN205942681U (en) | Serial communication interface that can dispose | |
| CN206894690U (en) | A kind of multifunctional serial port server | |
| CN202677389U (en) | Serial port expansion structure | |
| CN201876874U (en) | Chip module of communication interface | |
| CN204406391U (en) | A kind of data of optical fiber gyroscope R-T unit based on SPI |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130313 Termination date: 20150919 |
|
| EXPY | Termination of patent right or utility model |