CN202794943U - Digital quantity output circuit - Google Patents
Digital quantity output circuit Download PDFInfo
- Publication number
- CN202794943U CN202794943U CN201220472036.6U CN201220472036U CN202794943U CN 202794943 U CN202794943 U CN 202794943U CN 201220472036 U CN201220472036 U CN 201220472036U CN 202794943 U CN202794943 U CN 202794943U
- Authority
- CN
- China
- Prior art keywords
- digital quantity
- signal
- output circuit
- latch
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000006870 function Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
Images
Landscapes
- Bus Control (AREA)
Abstract
The utility model provides a digital quantity output circuit. The digital quantity output circuit comprises a processor and an output circuit, wherein a control signal is sent after the processor sends a digital quantity signal; and the output circuit is connected with the processor for carrying out output operation on the digital quantity signal.
Description
Technical field
The utility model relates to electronic circuit field, relates in particular to a kind of digital quantity output circuit.
Background technology
Under the applied environment of high reliability, the redundant method that all adopts digital output (Digital Output) circuit realizes reliably output, namely carry out repeated configuration by some parts to system, when a certain parts break down in the system, the work of trouble unit will be got involved and bear to the standby device of these parts in the system, thus the fault-time of system.But, because same parts have been carried out repeated configuration, so that DO circuit complexity and cost are high.
Existing control mode DO signal is by micro-control unit (Micro Control Unit, MCU) directly provide for MCU, if the procedural mistake that occurs MCU causes this DO signal that should not export to export to controlled device, thereby cause controlled device maloperation to occur, affect the normal operation of equipment.
The utility model content
The utility model provides a kind of digital quantity output circuit, and the technical matters that solve is the output that how to guarantee that the DO signal is correct.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
A kind of digital quantity output circuit comprises:
Processor after described processor sends digital quantity signal, transmits control signal;
Output circuit links to each other with described processor, and described digital quantity signal is carried out output function.
Preferably, described digital quantity output circuit also has following features: described output circuit comprises:
Storer, the storage digital quantity signal;
Control circuit links to each other with described storer with described processor, is used for after receiving control signal control store output digital quantity signal.
Preferably, described digital quantity output circuit also has following features:
Described storer is a latch, and wherein said control circuit links to each other with the end that latchs as the latch of storer, and after receiving control signal, to latching end transmission one pulse signal.
Preferably, described digital quantity output circuit also has following features: control circuit is a latch, and the control signal that wherein said processor sends is carried out twice counter-rotating in order to the latch of controlling as control circuit.
Preferably, described digital quantity output circuit also has following features: also comprise:
Buffer links to each other with described output circuit, the described digital quantity signal of buffer memory.
Preferably, described digital quantity output circuit also has following features: described buffer is latch.
Preferably, described digital quantity output circuit also has following features: described processor is micro-control unit MCU.
The circuit that the utility model provides after processor sends digital quantity signal, sends a control signal again by this processor, when whether realization works to processor, the again output of control figure amount signal realize simple scheme, and hardware cost is low.
Description of drawings
The structural representation of the digital quantity output circuit embodiment that Fig. 1 provides for the utility model;
Fig. 2 is another synoptic diagram of system shown in Figure 1 embodiment;
Fig. 3 is another synoptic diagram of system shown in Figure 2 embodiment;
The structural representation of the digital quantity output circuit application example one that Fig. 4 provides for the utility model;
The structural representation of the digital quantity output circuit application example two that Fig. 5 provides for the utility model.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with the accompanying drawings and the specific embodiments the utility model is described in further detail.Need to prove that in the situation of not conflicting, the embodiment among the application and the feature among the embodiment be combination in any mutually.
The structural representation of the digital quantity output circuit embodiment that Fig. 1 provides for the utility model.Embodiment illustrated in fig. 1, comprising:
Processor after described processor sends digital quantity signal, transmits control signal;
Output circuit links to each other with described processor, and described digital quantity signal is carried out output function.
From directly output is different after the DO signal generation in the prior art, in following circuit structure, the output of DO signal is controlled by output control circuit, just the DO signal is exported behind and if only if output circuit the receives corresponding signal, and the signal that this triggering output circuit carries out output function is that processor is controlled, after this processor sends digital quantity signal, if this processor can also produce correct control signal, namely still be in running status, represent that this processor is in normal operating conditions, this DO output is not maloperation so, by this control signal control DO output, has just finished once normal DO output so again; Corresponding, if there is the processor program mistake, maloperation causes the output of DO signal, because this processor can not produce control signal according to normal flow, the DO signal that this maloperation produces has guaranteed the Safety output of DO signal owing to there is not control signal finally can not export to controlled device.
As seen from the above, the DO signal output apparatus that provides of the utility model can guarantee the output safety of signal.
The below is described further the embodiment that the utility model provides:
Fig. 2 is another synoptic diagram of system shown in Figure 1 embodiment.Output circuit comprises described in the system shown in Figure 2 embodiment: storer and control circuit, wherein:
Storer, the storage digital quantity signal;
Control circuit links to each other with described storer with described processor, is used for after receiving control signal control store output digital quantity signal.
For output circuit, carry out temporary cache by storer to sent digital quantity signal, when latch the end detect pulse signal after, by control circuit this digital quantity is exported from storer again.
Wherein, described storer is a latch, and wherein said control circuit links to each other with the end that latchs as the latch of storer, and after receiving control signal, to latching end transmission one pulse signal.
Preferably, described control circuit is a latch, and the control signal that wherein said processor sends is carried out twice counter-rotating in order to the latch of controlling as control circuit.
Fig. 3 is another synoptic diagram of system shown in Figure 2 embodiment.Among the system shown in Figure 3 embodiment, described system also comprises:
Buffer links to each other with described output circuit, the described digital quantity signal of buffer memory.
That is, this digital quantity can directly send to output circuit in actual applications, also can be first by sending to output circuit after a buffer buffer memory a period of time again.
Preferably, simple in order to realize, described buffer is latch.
The below is described further the circuit that the utility model provides with concrete application example:
Application example one
The structural representation of the digital quantity output circuit application example one that Fig. 4 provides for the utility model.Circuit shown in Figure 2 comprises MCU, the first latch, the second latch and the 3rd latch, wherein the input end of the first latch links to each other with MCU, output terminal links to each other with the input end of the 3rd latch, wherein the input end of the second latch links to each other with MCU, output terminal links to each other with the end that latchs of the 3rd latch, wherein in as above circuit structure, flowing to of signal is specific as follows:
Behind MCU output DO signal, the first latch continues buffer memory to this DO signal, if MCU normal operation, then can send a control signal to the second latch, carry out twice counter-rotating in order to control the second latch, the variation of twice high-low level can appear in twice counter-rotating, thereby so that the second latch is exported a pulse signal, and this pulse signal finally can be exported to the 3rd latch, and through behind the first latch temporary, this digital quantity signal finally passes to the 3rd latch, in case the end that latchs of the 3rd latch detects this pulse signal, according to the characteristic of latches end, detect pulse signal and remove the characteristics that latch, digital quantity signal can be exported; On the contrary, if the DO signal is the output of the improper flow process of MCU, MCU carries out twice counter-rotating with regard to not controlling the second latch so, therefore the second latch can't send the signal that triggers output DO signal operation to the 3rd latch, even therefore the 3rd latch stores has the DO signal, finally can not export, guarantee the Safety output of DO signal.
Latch can adopt SN74LVC573 but be not limited to SN74LVC573, adopts SN74LVC573 in this example.
Need to prove, existing control mode DO signal is directly provided by MCU, if the operation of MCU mistake the address of DO output will cause the DO output error, in this application example because real output needs a series of operation, if the address of wrong access DO output only can cause the exporting change of the first latch in the MCU operational process, and the end that latchs of the 3rd latch does not change, and therefore output does not change, and guarantees the reliability of output.
By the improvement to DO signal output apparatus structure in the prior art, the DO output error that the program run-time error of avoiding causes improves reliability by latch, and implementation is simple.
Application example two
The structural representation of the digital quantity output circuit application example two that Fig. 5 provides for the utility model.Different from application example one is that this application example does not have the first latch among Fig. 2, but has MCU directly to link to each other with the 3rd latch, the digital quantity signal that is MCU output is directly exported to the 3rd latch, certainly, the specific implementation principle is still identical, repeats no more herein.
In sum, the circuit that the utility model provides is after processor sends digital quantity signal, again send a control signal by this processor, when whether realization works to processor, the again output of control figure amount signal, realize simple scheme, and hardware cost is low.
The above; it only is embodiment of the present utility model; but protection domain of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the described protection domain of claim.
Claims (7)
1. a digital quantity output circuit is characterized in that, comprising:
Processor after described processor sends digital quantity signal, transmits control signal;
Output circuit links to each other with described processor, and described digital quantity signal is carried out output function.
2. digital quantity output circuit according to claim 1 is characterized in that, described output circuit comprises:
Storer, the storage digital quantity signal;
Control circuit links to each other with described storer with described processor, is used for after receiving control signal control store output digital quantity signal.
3. digital quantity output circuit according to claim 2 is characterized in that:
Described storer is a latch, and wherein said control circuit links to each other with the end that latchs as the latch of storer, and after receiving control signal, to latching end transmission one pulse signal.
4. digital quantity output circuit according to claim 3 is characterized in that, control circuit is a latch, and the control signal that wherein said processor sends is carried out twice counter-rotating in order to the latch of controlling as control circuit.
5. digital quantity output circuit according to claim 2 is characterized in that, also comprises:
Buffer links to each other with described output circuit, the described digital quantity signal of buffer memory.
6. digital quantity output circuit according to claim 5 is characterized in that, described buffer is latch.
7. according to claim 1 to 6 arbitrary described digital quantity output circuits, it is characterized in that described processor is micro-control unit MCU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220472036.6U CN202794943U (en) | 2012-09-14 | 2012-09-14 | Digital quantity output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220472036.6U CN202794943U (en) | 2012-09-14 | 2012-09-14 | Digital quantity output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202794943U true CN202794943U (en) | 2013-03-13 |
Family
ID=47822178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220472036.6U Expired - Lifetime CN202794943U (en) | 2012-09-14 | 2012-09-14 | Digital quantity output circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202794943U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919464A (en) * | 2017-02-27 | 2017-07-04 | 郑州云海信息技术有限公司 | A kind of server board reset protective device and method |
| CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
| CN113936941A (en) * | 2021-09-10 | 2022-01-14 | 华为数字能源技术有限公司 | Switching device and power distribution system |
-
2012
- 2012-09-14 CN CN201220472036.6U patent/CN202794943U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106919464A (en) * | 2017-02-27 | 2017-07-04 | 郑州云海信息技术有限公司 | A kind of server board reset protective device and method |
| CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
| CN113936941A (en) * | 2021-09-10 | 2022-01-14 | 华为数字能源技术有限公司 | Switching device and power distribution system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102064962B (en) | Method for implementing input and output assemblies of ATS (Automatic Train Supervision) system based on named pipeline communication | |
| CN105573239A (en) | High speed backboard bus communication control device and method | |
| CN202794943U (en) | Digital quantity output circuit | |
| CN109932966B (en) | Real-time efficient data transmission method based on M-LVDS bus | |
| CN103530215B (en) | A kind of self checking method of internal integrated circuit main frame, device and main frame | |
| CN103281226A (en) | MVB bus device address configuration system and method based on TCN | |
| CN103941625A (en) | Can bus data transmission monitoring system | |
| CN101188488B (en) | Control method and device for half duplex communication receiving/transmission | |
| CN112822039B (en) | Main and standby mode switching method for dual-machine hot standby system | |
| CN102156795B (en) | Simulation information system of digital transformer station based on transformer station configuration description file | |
| CN203260219U (en) | Simulated merging unit simulation device | |
| CN204633800U (en) | The switch of a kind of administrative unit and the two redundancy of crosspoint | |
| CN103391223B (en) | A kind of IEC101 protocol massages fast automatic detecting method | |
| CN213457745U (en) | 64-way high-speed GPIO control board based on HSC serial bus interface | |
| CN102609388B (en) | Slave node circuit, communication method and communication device | |
| CN107347003B (en) | Method and device for automatically switching communication lines and wind generating set | |
| CN104135411A (en) | Device and method of implementing multi-node communication based on RS232 interface | |
| CN109032978A (en) | A kind of document transmission method based on BMC, device, equipment and medium | |
| CN204089864U (en) | A kind of gateway for connecting MVB and CAN | |
| CN204323342U (en) | Electric locomotive traction control unit | |
| CN104617664B (en) | Method for switching double intelligent terminal device remote communication quantity in intelligent substation | |
| CN204517786U (en) | Digital output unit and digital output card | |
| CN105446863A (en) | Electronic device with recording capability and circuit status recording method | |
| CN102955545A (en) | Computer | |
| CN221485885U (en) | Full-time automatic control watchdog circuit and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100176, No. 3, building 21, prosperous street, Daxing District economic and Technological Development Zone, Beijing, four or five Patentee after: BEIJING HOLLYSYS AUTOMATION & DRIVE Co.,Ltd. Address before: 100176, No. 3, building 21, prosperous street, Daxing District economic and Technological Development Zone, Beijing, four or five Patentee before: Beijing HollySys Automation Technologies Co.,Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 100176, No. 1, building 2, No. 5 middle Sheng Road, Beijing economic and Technological Development Zone, 1510-1515 Patentee after: BEIJING HOLLYSYS AUTOMATION & DRIVE Co.,Ltd. Address before: 100176, No. 3, building 21, prosperous street, Daxing District economic and Technological Development Zone, Beijing, four or five Patentee before: BEIJING HOLLYSYS AUTOMATION & DRIVE Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20201123 Address after: 315000 5-7, No.38, building 7, East Zone, Ningbo new material innovation center, high tech Zone, Ningbo City, Zhejiang Province Patentee after: NINGBO HELISHI INTELLIGENT TECHNOLOGY Co.,Ltd. Address before: 100176, No. 1, building 2, No. 5 middle Sheng Road, Beijing economic and Technological Development Zone, 1510-1515 Patentee before: BEIJING HOLLYSYS AUTOMATION & DRIVE Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210408 Address after: 100176 Floor 5 510-1515, No. 1 Building, No. 2 Courtyard, Dishengzhong Road, Daxing District Economic and Technological Development Zone, Beijing Patentee after: BEIJING HOLLYSYS AUTOMATION & DRIVE Co.,Ltd. Address before: 5-7, No.38, building 7, East District, Ningbo new material innovation center, Ningbo hi tech Zone, 315000, Zhejiang Province Patentee before: NINGBO HELISHI INTELLIGENT TECHNOLOGY Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130313 |
|
| CX01 | Expiry of patent term |